CN104092466B - Assembly line successive approximation analog-to-digital converter - Google Patents
Assembly line successive approximation analog-to-digital converter Download PDFInfo
- Publication number
- CN104092466B CN104092466B CN201410298216.0A CN201410298216A CN104092466B CN 104092466 B CN104092466 B CN 104092466B CN 201410298216 A CN201410298216 A CN 201410298216A CN 104092466 B CN104092466 B CN 104092466B
- Authority
- CN
- China
- Prior art keywords
- electric capacity
- switch
- amplifier
- surplus
- negative
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention relates to an assembly line successive approximation analog-to-digital converter which can eliminate offset voltage of an allowance amplifier. A capacitor is added to a signal channel between the input end of a comparator and the input end of the allowance amplifier and is used for storing the offset voltage of the allowance amplifier without changing the working principle of a single-level circuit. By means of the assembly line successive approximation analog-to-digital converter, errors which are caused by the offset voltage of the allowance amplifier to the whole circuit can be reduced.
Description
Technical field
The present invention relates to IC design field is and in particular to a kind of streamline gradually-appoximant analog-digital converter.
Background technology
Currently, in order to adapt to computer, communication and multimedia technology develop rapidly and high-technology field numeral
Change process is constantly accelerated, and ADC has very big change on technique, properity, towards low-power consumption, at a high speed, high score
The direction of resolution is developed.Streamline gradually-appoximant analog-digital converter had both simultaneously conventional pipeline analog-digital converter and tradition by
The secondary advantage approaching analog-digital converter, have the characteristics that high accuracy, at a high speed, low-power consumption.
Surplus amplifier is the nucleus module of streamline gradually-appoximant analog-digital converter, and its performance directly decides modulus and turns
The overall performance of parallel operation.Many non-ideal factors of surplus amplifier all can produce error to whole circuit, and one of them is very heavy
The factor wanted is the input offset voltage of amplifier, and the output of surplus amplifier is transferred in the closed loop gain that it can be multiplied by amplifier
End, in whole circuit produce error, therefore the elimination of surplus offset voltage of amplifier it is critical that.
Document " Chun C.Lee, A SAR-Assisted Two-Stage Pipeline ADC, IEEE Journal Of
A kind of flowing water of single ended input is proposed in Solid-State Circuits, 2011, VOL.46, NO.4, pp.859～869 "
Line gradually-appoximant analog-digital converter.This analog-digital converter one is divided into two-stage, and the resolution of the first order is 6bit, the second level point
Resolution is 7bit.Referring to the drawings 1, give the schematic diagram of first order circuit.Its operation principle is：Work process is divided into three ranks
Section, sample phase, conversion stage and amplification stage.
In sample phase, switch S and switch SP closure, switch H disconnects, in capacitance network the top crown of all electric capacity connect defeated
Enter signal Vin, the bottom crown ground connection of all electric capacity.On electric capacity, the electric charge of storage is：
Q=26C*Vin
In the conversion stage, switch S, switch SP and switch H disconnect, and in capacitance network, the top crown of all electric capacity is according to numeral
The value of code di selects to be connected to reference voltage Vref or ground.If di is high level, corresponding electric capacity 2 (6-i) C is connected to reference voltage
On Vref, if di is low level, corresponding electric capacity 2 (6-i) C is connected on the ground.The bottom crown of all electric capacity connects comparator input terminal.
Now, on electric capacity, the electric charge of storage is：
Q'=(d125C+d224C+......+d6C)*(Vref-Vcom)+(26C-d125C-d224C-......-d6C)*(0-
Vcom)
Vcom is the voltage of comparator input terminal, according to law of conservation of charge：
Q=Q'
Can draw：
Vcom=-Vin+(d12-1+d22-2+......+d62-6)*Vref
After six clock cycle, digital code d1 to d6 all quantifies to complete, and circuit enters amplification stage.
In amplification stage, switch S and switch SP and disconnect, switch H closure, the company of the top crown of all electric capacity in capacitance network
Connect that method is the same with the conversion stage, the bottom crown of all electric capacity is connected to the negative-phase input of surplus amplifier.According to empty short spy
Property, the voltage of amplifier negative-phase input is equal to the voltage of normal phase input end, and now, on electric capacity, the electric charge of storage is：
Q "=(d125C+d224C+......+d6C)*(Vref-0)+(26C-d125C-d224C-......-d6C)*(0-0)+
4C*(Vres-0)
According to law of conservation of charge：
Q=Q "
Can draw：
Vres=16* [Vin-(d12-1+d22-2+......+d62-6)*Vref]
Above-mentioned formula derivation does not have the offset voltage considering surplus amplifier it is assumed that surplus amplifier positive inputs
There is an offset voltage Vos at end, and the derivation in sample phase and conversion stage is just the same with above-mentioned derivation, but,
In amplification stage, according to empty short characteristic, the voltage of amplifier negative-phase input is equal to the voltage Vos of normal phase input end, then
Now, on electric capacity, the electric charge of storage is：
Q " '=(d125C+d224C+......+d6C)*(Vref-Vos)+(26C-d125C-d224C-......-d6C)*(0-
Vos)+4C*(Vres-Vos)
According to law of conservation of charge：
Q=Q " '
Can draw：
Vres=16* [Vin-(d12-1+d22-2+......+d62-6)*Vref]+17Vos
It can be seen that the single-level circuit that above-mentioned document proposes does not have the offset voltage eliminating surplus amplifier, this imbalance
Voltage produces error in residual signal, affects the performance of whole analog-digital converter.
Content of the invention
Technical problem to be solved
In place of the deficiencies in the prior art, the present invention proposes a kind of surplus offset voltage of amplifier of can eliminating
Streamline gradually-appoximant analog-digital converter.Add in signal path between comparator input terminal and surplus amplifier in
One electric capacity, for the offset voltage of memory margin amplifier, and does not change the operation principle of single-level circuit.
Technical scheme
A kind of streamline gradually-appoximant analog-digital converter, including M level pipelining-stage circuit, the resolution of every grade of circuit is Ni
Position, i=1,2......M；Described pipelining-stage circuit includes switched capacitor network, comparator and surplus amplifier；Switching capacity
Network includes positive capacitance network and negative capacitance network；It is characterized in that in comparator input terminal and surplus amplifier in
Between add an electric capacity, for the offset voltage of memory margin amplifier；Physical circuit is as follows：
The positive capacitance network being connected with comparator normal phase input end passes through to switch S3 and electric capacity C1 and surplus amplifier
Negative-phase input be connected, the top crown of electric capacity C1 is connected on common mode electrical level Vcm by switching S5；Defeated with comparator negative
Enter to hold the negative capacitance network being connected to be connected with the normal phase input end of surplus amplifier with electric capacity C2 by switching S4, electric capacity
The top crown of C2 is connected on common mode electrical level Vcm by switching S6；The negative-phase input of surplus amplifier, the bottom crown of electric capacity C3
It is connected with the input of switch S9, the positive output end of surplus amplifier, the outfan of switch S9 and the outfan switching S11
It is connected, the top crown of electric capacity C3 is connected with the input of switch S11, the top crown of electric capacity C3 is connected to altogether by switching S7
On mould level Vcm；The normal phase input end of surplus amplifier, the bottom crown of electric capacity C4 are connected with the input of switch S10, surplus
The negative output end of amplifier, switch S10 outfan with switch S12 outfan be connected, the top crown of electric capacity C4 with open
The input closing S12 is connected, and the top crown of electric capacity C4 is connected on common mode electrical level Vcm by switching S8.
The size of described electric capacity C1 and electric capacity C2 is 2NiC, C are the size of a specific capacitance.
The size of described electric capacity C3 and electric capacity C4 is C, and C is the size of a specific capacitance.
Beneficial effect
A kind of streamline gradually-appoximant analog-digital converter proposed by the present invention, reduces the imbalance electricity due to surplus amplifier
The error that pressure produces to whole circuit.
Brief description
A kind of single-level circuit principle of the streamline gradually-appoximant analog-digital converter proposing in Fig. 1 background of invention
Figure.
A kind of streamline gradually-appoximant analog-digital converter structural representation proposing in Fig. 2 embodiment of the present invention.
The single-level circuit schematic diagram of the analog-digital converter proposing in Fig. 3 embodiment of the present invention.
Specific embodiment
In conjunction with embodiment, accompanying drawing, the invention will be further described：
The present embodiment is the one 13 streamline gradually-appoximant analog-digital converters enough eliminating surplus offset voltage of amplifier
Overall structure diagram, as shown in Figure 2.This analog-digital converter comprises altogether level Four, the first order, the second level, third level knot
Structure is identical, all comprises the gradually-appoximant analog-digital converter of a 4bit and the multiplying digital-to-analog converter of a 4bit, concrete principle
Shown in figure refer to the attached drawing 3.The fourth stage only comprises the gradually-appoximant analog-digital converter of a 5bit.In order to prevent due to various unreasonablys
Think that the output result of first three grade of multiplying digital-to-analog converter that factor leads to exceeds the input range of next stage, produce uncorrectable
Error, the amplification of front three-level is reduced half, and that is, amplification is reduced to 8 by original 16, so, the number of level Four circuit
The folded addition of word output code is exactly the digital output code of whole analog-digital converter.
It is the single-level circuit schematic diagram of analog-digital converter as shown in Figure 3, including switched capacitor network, comparator and surplus
Amplifier；Switched capacitor network includes positive capacitance network and negative capacitance network.In comparator input terminal and surplus amplifier
An electric capacity is added, for the offset voltage of memory margin amplifier between input；Physical circuit is as follows：With comparator positive
The positive capacitance network that input is connected is connected with the negative-phase input of surplus amplifier with electric capacity C1 by switching S3, electricity
The top crown holding C1 is connected on common mode electrical level Vcm by switching S5；The negative electric capacity being connected with comparator negative-phase input
Network is connected with the normal phase input end of surplus amplifier with electric capacity C2 by switching S4, and the top crown of electric capacity C2 passes through to switch S6
It is connected on common mode electrical level Vcm；Electric capacity C1 and electric capacity C2 size are 2NiC (C is the size of a specific capacitance), for storing
The offset voltage of surplus amplifier.The negative-phase input of surplus amplifier, the bottom crown of electric capacity C3 and the input phase switching S9
Connect, the positive output end of surplus amplifier, the outfan of switch S9 are connected with the outfan of switch S11, and electric capacity C3's is upper
Pole plate is connected with the input of switch S11, and the top crown of electric capacity C3 is connected on common mode electrical level Vcm by switching S7；Surplus
The normal phase input end of amplifier, the bottom crown of electric capacity C4 are connected with the input of switch S10, the negative output of surplus amplifier
End, the outfan of switch S10 are connected with the outfan of switch S12, and the top crown of electric capacity C4 is connected with the input of switch S12
Connect, the top crown of electric capacity C4 is connected on common mode electrical level Vcm by switching S8.The size of electric capacity C3 and electric capacity C4 is that (C is one to C
The size of individual specific capacitance).
The removing method of surplus offset voltage of amplifier is discussed in detail below.Whole circuit work process is divided into three ranks
Section：Sample phase, conversion stage and amplification stage.
In sample phase, clock Φ 1, Φ 1e, Φ 1f are high level, and clock Φ 2 is low level.Switch S1, S2, S5, S6,
S7, S8, S9, S10 close, and switch S3, S4, S11, S12 disconnect.In positive capacitance network, the top crown of all electric capacity connects input letter
Number Vip, bottom crown meets common mode electrical level Vcm.In negative capacitance network, the top crown of all electric capacity connects input signal Vin, bottom crown
Meet common mode electrical level Vcm.Electric capacity C1, C2, C3 and C4 have been connected between surplus amplifier in and common mode electrical level Vcm.With A node
On connected electric capacity, the electric charge of storage is:
QA=24C*(Vcm-Vip)
On the electric capacity being connected with B node, the electric charge of storage is:
QB=24C*(Vcm-Vip)
On the electric capacity being connected with C node, the electric charge of storage is:
QC=C1* (Vcm-Vopa)
Vopa is the common-mode voltage of surplus amplifier in, and on the electric capacity being connected with D node, the electric charge of storage is:
QD=C2* [Vcm-(Vopa+Vos)]
On the electric capacity being connected with E node, the electric charge of storage is:
QE=C1* (Vopa-Vcm)+C3*(Vopa-Vcm)
On the electric capacity being connected with F node, the electric charge of storage is:
QF=C2* (Vopa+Vos-Vcm)+C4*(Vopa+Vos-Vcm)
In the conversion stage, clock Φ 1, Φ 1e, Φ 1f, Φ 2 are low level.Switch S1, S2, S3, S4, S5, S6, S7,
S8, S9, S10, S11, S12 disconnect.In capacitance network, the top crown of all electric capacity selects to be connected to reference according to the value of digital code di
On voltage Vrefp or Vrefn.If the value of di is high level, in positive capacitance network, the top crown of all electric capacity is connected to reference
On voltage Vrefp, in negative capacitance network, the top crown of all electric capacity is connected in reference voltage Vref n.If the value of di is low electricity
Flat, then in positive capacitance network, the top crown of all electric capacity is connected in reference voltage Vref n, all electric capacity in negative capacitance network
Top crown be connected in reference voltage Vref p.The top crown of electric capacity C1, C2, C3 and C4 is hanging, and bottom crown connects surplus amplifier
Input.Now on electric capacity C1, C2, C3 and C4, the electric charge of storage is constant, and on circuit node C, D, E and F, the electric charge of storage is constant.
On the electric capacity being connected with A node, the electric charge of storage is:
Q'A=(d123C+d222C+d321C+d420C)*(VA-Vrefp)
+(24C-d123C-d222C-d321C-d420C)*(VA-Vrefn)
On the electric capacity being connected with B node, the electric charge of storage is:
Q'B=(d123C+d222C+d321C+d420C)*(VB-Vrefn)
+(24C-d123C-d222C-d321C-d420C)*(VB-Vrefp)
According to law of conservation of charge：
QA=Q'A
QB=Q'B
Can draw：
VA-VB=-(Vip-Vin)+(d1+d22-1+d32-2+d42-3-1)*(Vrefp-Vrefn)
After four clock cycle, digital code d1 to d4 quantifies to complete, and enters amplification stage.
In amplification stage, clock Φ 1, Φ 1e, Φ 1f are low level, and clock Φ 2 is high level.Switch S1, S2, S5, S6,
S7, S8, S9, S10 disconnect, switch S3, S4, S11, S12 closure.In capacitance network, the top crown of all electric capacity is according to digital code di
Value select be connected on reference voltage Vref p or Vrefn, method of attachment with change the stage as.The top crown of electric capacity C1 is connected to
The normal phase input end of comparator, the top crown of electric capacity C2 is connected to the negative-phase input of comparator, and the top crown of electric capacity C3 is connected to remaining
The positive output end of amount amplifier, the top crown of electric capacity C4 is connected to the negative output end of surplus amplifier, electric capacity C1, C2, C3 and
The bottom crown of C4 connects the input of surplus amplifier.
Due to switch S3 closure, circuit node A, C connect into a node, storage on the electric capacity being connected with A, C node
Electric charge is:
Q”AC=(d123C+d222C+d321C+d420C)*(VAC-Vrefp)
+(24C-d123C-d222C-d321C-d420C)*(VAC-Vrefn)+C1*(VAC-Vopa)
In the same manner, circuit node B, D connects into a node, and on the electric capacity being connected with B, D node, the electric charge of storage is:
Q”BD=(d123C+d222C+d321C+d420C)*(VBD-Vrefp)
+(24C-d123C-d222C-d321C-d420C)*(VBD-Vrefn)+C2*(VBD-Vopa-Vos)
On the electric capacity being connected with E node, the electric charge of storage is:
Q”E=C1* (Vopa-VAC)+C3*(Vopa-Vop)
On the electric capacity being connected with F node, the electric charge of storage is:
Q”F=C2* (Vopa+Vos-VBD)+C4*(Vopa+Vos-Von)
According to law of conservation of charge：
QA+QC=Q "AC
QB+QD=Q "BD
QE=Q "E
QF=Q "F
C1=C2
C3=C4
Can draw：
Make C1=mC, C3=nC, m>0, n>0, because the amplification of surplus amplifier is 8, so：
So n=1, n=1 substitution above formula can be obtained m=16, so C1=C2=16C, C3=C4=C.
Claims (1)
1. a kind of streamline gradually-appoximant analog-digital converter, including M level pipelining-stage circuit, the resolution of every grade of circuit is Ni position, i
=1,2......M；Described pipelining-stage circuit includes switched capacitor network, comparator and surplus amplifier；Switched capacitor network
Including positive capacitance network and negative capacitance network；It is characterized in that between comparator input terminal and surplus amplifier in
Add an electric capacity, for the offset voltage of memory margin amplifier；Physical circuit is as follows：
The positive capacitance network being connected with comparator normal phase input end passes through to switch the negative of S3 and electric capacity C1 and surplus amplifier
Phase input is connected, and the top crown of electric capacity C1 is connected on common mode electrical level Vcm by switching S5；With comparator negative-phase input
The negative capacitance network being connected is connected with the normal phase input end of surplus amplifier with electric capacity C2 by switching S4, electric capacity C2's
Top crown is connected on common mode electrical level Vcm by switching S6；The negative-phase input of surplus amplifier, the bottom crown of electric capacity C3 with open
The input closing S9 is connected, and the positive output end of surplus amplifier, the outfan of switch S9 are connected with the outfan of switch S11
Connect, the top crown of electric capacity C3 is connected with the input of switch S11, the top crown of electric capacity C3 is connected to common mode electricity by switching S7
On flat Vcm；The normal phase input end of surplus amplifier, the bottom crown of electric capacity C4 are connected with the input of switch S10, and surplus is amplified
The negative output end of device, switch S10 outfan with switch S12 outfan be connected, the top crown of electric capacity C4 with switch S12
Input be connected, the top crown of electric capacity C4 is connected on common mode electrical level Vcm by switching S8；
The size of described electric capacity C1 and electric capacity C2 is 2NiC, C are the size of a specific capacitance；
The size of described electric capacity C3 and electric capacity C4 is C, and C is the size of a specific capacitance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410298216.0A CN104092466B (en) | 2014-06-26 | 2014-06-26 | Assembly line successive approximation analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410298216.0A CN104092466B (en) | 2014-06-26 | 2014-06-26 | Assembly line successive approximation analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104092466A CN104092466A (en) | 2014-10-08 |
| CN104092466B true CN104092466B (en) | 2017-02-15 |
Family
ID=51640153
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410298216.0A Expired - Fee Related CN104092466B (en) | 2014-06-26 | 2014-06-26 | Assembly line successive approximation analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104092466B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105119603B (en) * | 2015-09-06 | 2018-04-06 | 西北工业大学 | Streamline gradually-appoximant analog-digital converter |
| US9413377B1 (en) * | 2015-12-15 | 2016-08-09 | Lncku Research And Development Foundation | Switched capacitor circuit and compensation method thereof, and analog to digital converter |
| US10476456B2 (en) * | 2016-10-04 | 2019-11-12 | Mediatek Inc. | Comparator having a high-speed amplifier and a low-noise amplifier |
| CN107528594A (en) * | 2017-08-25 | 2017-12-29 | 中国电子科技集团公司第二十四研究所 | Charge type streamline gradual approaching A/D converter and its control method |
| CN109217874B (en) * | 2018-11-16 | 2020-11-17 | 深圳锐越微技术有限公司 | Margin transfer loop, successive approximation type analog-to-digital converter and gain calibration method |
| CN113452371B (en) * | 2020-03-25 | 2023-07-04 | 智原微电子(苏州)有限公司 | Successive approximation register analog-to-digital converter and related control method |
| CN113572475A (en) * | 2021-09-23 | 2021-10-29 | 微龛(广州)半导体有限公司 | Cyclic conversion SAR ADC circuit and SAR ADC method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101217279A (en) * | 2008-01-11 | 2008-07-09 | 清华大学 | A low power consumption comparator with mistuning calibration function |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITRM20010407A1 (en) * | 2001-07-10 | 2003-01-10 | St Microelectronics Srl | HIGH SPEED ANALOG / DIGITAL CONVERTER, HIGH RESOLUTION LOW CONSUMPTION WITH SINGLE-ENDED INPUT. |
| US7764215B2 (en) * | 2008-12-31 | 2010-07-27 | Hong Kong Applied Science And Technology Research Institute Co., Ltd. | Multi-stage comparator with offset canceling capacitor across secondary differential inputs for high-speed low-gain compare and high-gain auto-zeroing |
-
2014
- 2014-06-26 CN CN201410298216.0A patent/CN104092466B/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101217279A (en) * | 2008-01-11 | 2008-07-09 | 清华大学 | A low power consumption comparator with mistuning calibration function |
Non-Patent Citations (1)
| Title |
|---|
| 《用于PET成像系统的流水线ADC设计》;薛菲菲等;《微电子学与计算机》;20130131;第30卷(第1期);第61-64页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104092466A (en) | 2014-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104092466B (en) | Assembly line successive approximation analog-to-digital converter | |
| CN105391451B (en) | Switching method when a kind of gradual approaching A/D converter and its analog-to-digital conversion | |
| CN105553479B (en) | A kind of binary capacitor array and its low power consumption switch method applied to nearly threshold value SAR ADC | |
| CN102801422A (en) | Successive approximation type analog/digital converter | |
| CN104168025B (en) | A kind of charge type streamline gradual approaching A/D converter | |
| CN101465649B (en) | Comparator with adjustable reference voltage | |
| CN103518329A (en) | Pre-charged capacitive digital-to-analog converter | |
| CN101729069B (en) | Successive approximation type analog-to-digital converter with binary fault tolerant mechanism | |
| CN105119603B (en) | Streamline gradually-appoximant analog-digital converter | |
| CN104967451A (en) | Successive approximation type analog-to-digital converter | |
| CN104467856A (en) | High-energy-efficiency capacitor array successive approximation type analog-digital converter and converting method thereof | |
| CN107888190B (en) | Successive approximation type analog-digital converter based on asymmetric differential capacitor array | |
| CN102970038A (en) | Gradual approach analog to digital converter for correcting unmatching of capacitor and method thereof | |
| CN111711453B (en) | Successive approximation type analog-to-digital converter | |
| CN103178855A (en) | Three-segment type capacitor array structure applied on high-precision successive approximation analog-digital converter (ADC) | |
| US20140002291A1 (en) | Analog to digital conversion architecture and method with input and reference voltage scaling | |
| CN207782773U (en) | A kind of gradual approaching A/D converter | |
| CN106160745A (en) | Analog-digital commutator and initial method thereof | |
| CN102970037B (en) | A kind of current source self-calibration circuit | |
| CN107395205B (en) | Successive approximation type analog-digital converter based on asymmetric differential capacitor array | |
| US20120133541A1 (en) | Analog-digital converter | |
| CN104135291B (en) | A kind of continuous proximity register analog-digital converter realized in pulse charge form | |
| CN104660262B (en) | Capacitance resistance mixed type SAR ADC | |
| CN108649956A (en) | A kind of gradual approaching A/D converter based on asymmetric differential capacitance array | |
| TWI477083B (en) | Successive approximation analog-to-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20170215 Termination date: 20210626 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |