CN107528594A - Charge type streamline gradual approaching A/D converter and its control method - Google Patents
Charge type streamline gradual approaching A/D converter and its control method Download PDFInfo
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- CN107528594A CN107528594A CN201710740060.0A CN201710740060A CN107528594A CN 107528594 A CN107528594 A CN 107528594A CN 201710740060 A CN201710740060 A CN 201710740060A CN 107528594 A CN107528594 A CN 107528594A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
- H03M1/468—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors in which the input S/H circuit is merged with the feedback DAC array
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Abstract
The present invention provides a kind of charge type streamline gradual approaching A/D converter, including：High-order capacitor array, for being sampled to input signal, it is additionally operable to charge and discharge；Bit capacitor array, its capacitance is identical with the capacitance of high-order capacitor array, for charge and discharge；ON-OFF control circuit, for controlling the working condition of high-low position capacitor array, it is additionally operable to the residual error voltage of high-order capacitor array being distributed to bit capacitor array with electric charge sharing mode；Comparator, for gradually being compared bit capacitor array in half period, high-order capacitor array is gradually compared in another half period, fiducial value is sequentially output；Approach by inchmeal deposits logic circuit, the switch of two selecting switch arrays for closing connection high-low position capacitor array according to fiducial value, until the corresponding switch for closing capacitor array obtains data signal.The present invention also provides the control method of the analog-digital converter, simplifies the design difficulty of circuit, reduces the area of circuit.
Description
Technical field
The invention belongs to technical field of integrated circuits, is related to analog signal or digital-to-analogue mixed signal, more particularly to one kind
Charge type streamline gradual approaching A/D converter and its control method.
Background technology
In recent years, with the further raising of performance of analog-to-digital convertor index, in particular with integrated circuit processing technique
Continuous development, the research to high-speed asynchronous gradual approaching A/D converter is also more and more deep.With IC manufacturing
The continuous evolution of technique, the design of high gain operational amplifier becomes more and more difficult, due to not needing operational amplifier, SAR
(Successive Approximation Register) structure ADC (Analog-to-Digital Converter) has day
Right low-power consumption advantage, particularly under nanoscaled process node, SAR (successive approximation register type) structure ADC (analog-to-digital conversion
Device) speed got back huge lifting.Therefore, high speed SAR structure ADCs turn into the study hotspot of current analog-digital converter.
In order to meet ADC overall high speed operation requirement, the work in series pattern of SAR structure ADCs is still a serious bottleneck,
In order to further improve ADC operating rate, occurs the ADC of mixed structure in recent years, such as：Piplined-SAR (streamline-
Successive approximation) structure ADC framework.
However, to still have residue amplifier design difficulty larger for traditional Piplined-SAR structure ADCs, power consumption compared with
Greatly, the imbalance of two stage comparator needs a series of problems, such as calibration.Therefore, traditional structure is unfavorable for mixed at high speed structure ADC
Realize.In order to better illustrate advantages of the present invention, the advantages of first analyzing a kind of traditional Piplined-SAR structure ADCs and lack
Point, in order to represent convenient, illustrate below all by taking 8 ADC as an example, meanwhile, original is operated instead of differential configuration with single-ended structure
Manage explanation.
Traditional Piplined-SAR ADC structures 1, as shown in figure 1, C is set as unit capacitor's capacity, its high-order and low level electricity
Hold array DAC1 and DAC2 respectively by the weight electric capacity that capacitor's capacity is 128C, 64C, 32C and the compensation electricity that capacitance is 32C
Hold and form, in high-order capacitor array DAC1, the top crown of electric capacity is connected with sampling switch S1 one end, while and comparator
COMP1 input is connected, and is also connected with residue amplifier RA input, sampling switch S1 another termination input voltage letter
Number VIN.Bit capacitor array DAC2 top crown is connected with reset switch S1N, at the same with comparator COMP2 input phase
Even, also it is connected with residue amplifier RA output end.
Traditional Piplined-SAR ADC structures 1 timing diagram corresponding when working, as shown in Figure 2：As sampling switch S1
During conducting, switch S1N shut-offs, high-order capacitor array DAC1 is in sample phase, and comparator COMP2 is first eliminated by signal cal2
Imbalance is calibrated, and hereafter, bit capacitor array DAC2 is in the Approach by inchmeal stage.When bit capacitor array completes Approach by inchmeal
After process, sampling switch S1 shut-offs, switch S1N is turned on, and bit capacitor array DAC2 is in reset state, and comparator COMP1 leads to
Cross signal cal1 and first eliminate imbalance and calibrated, hereafter, high-order capacitor array DAC1 is in Approach by inchmeal state.When high-order electric capacity
After array DAC1 completes Approach by inchmeal process, switch S1N shut-offs, control signal S2 causes residue amplifier RA to be in work shape
State, residual error voltage caused by high-order capacitor array is handled, hereafter, switch S1 conductings, high-order capacitor array enters again
Enter sample phase, ADC completes the one action cycle.The advantages of this structure, is, by the capacitor array of traditional SAR structure ADCs
It is divided into high-order capacitor array DAC1 and bit capacitor array DAC2, centre is attached with a residue amplifier RA, by a high position
After residual error voltage is handled by RA caused by capacitor array DAC1, bit capacitor array DAC2, this structure knot are passed to
The advantages of the advantages of having closed Piplined structure ADC high speeds and SAR structure ADC low-power consumption.
However, the shortcomings that this structure, is：On the one hand, to use to a residue amplifier RA, with integrated circuit
The gradual renewal of manufacturing process, under nanoscaled process, the design of residue amplifier becomes more and more difficult.On the other hand, this
Kind structure has used two comparators, therefore, it is necessary to mistuning calibration function be carried out to the two comparators, so as to eliminate offset error.
Simultaneously, it is necessary to introduce two groups of different reference voltages, based on above-mentioned three aspect factor, design difficulty is added.
The content of the invention
In view of the above the shortcomings that prior art, it is an object of the invention to provide a kind of charge type streamline gradually to force
Plesiotype analog-digital converter and its control method, for solving the analog-digital converter of Piplined-SAR structures in the prior art true
Under the advantages of protecting high speed and low-power consumption, the problem of complex circuit designs are spent can not be reduced.
In order to achieve the above objects and other related objects, the present invention provides a kind of charge type streamline successive approximation modulus
Converter, including：
High-order capacitor array, for sampling input voltage signal, it is additionally operable to carry out charge and discharge to electric capacity；
Bit capacitor array, its capacitance is identical with the capacitance of high-order capacitor array, for being filled, being put to electric capacity
Electricity；
ON-OFF control circuit, its input are connected with the output end of the high-low position capacitor array, for controlling high-order electricity
Hold array, the working condition of bit capacitor array, be additionally operable to the residual error voltage of the high-order capacitor array with the shared side of electric charge
Formula is distributed to bit capacitor array；
One comparator, its input are connected with the output end of the ON-OFF control circuit, for right in half period
Bit capacitor array is gradually compared, and high-order capacitor array is gradually compared in other half period, by fiducial value
It is sequentially output；
Approach by inchmeal deposits logic circuit, and its input is connected with the output end of the comparator, for according to the ratio
It is all until closing compared with the switch of two selecting switch arrays of the fiducial value closure connection high-low position capacitor array of device output
The switch of two selecting switch arrays of capacitor array obtains the data signal of input voltage signal conversion.
The present invention also provides a kind of control method of charge type streamline gradual approaching A/D converter, including：
Charge type streamline successive approximation modulus device controls low potential capacitor array gradually to force according to ON-OFF control circuit
Closely；Wherein, comparator is gradually compared bit capacitor array in half period, until closing all capacitor arrays two
The switch of selecting switch array obtains the digital code of the LSB corresponding to input voltage signal conversion output bit capacitor array；
Control circuit control low potential capacitor array ground connection resets, the high potential capacitor array sampling；
When the ON-OFF control circuit controls high potential capacitor array Approach by inchmeal；Wherein, comparator was at other half week
High-order capacitor array is gradually compared in phase, exports the digital code of the MSB corresponding to high-order capacitor array, and the high position
The top crown of capacitor array generates residual error voltage；
When the ON-OFF control circuit control high potential capacitor array be connected with low potential capacitor array, by the high potential
Capacitor array residual error voltage is distributed to bit capacitor array with electric charge sharing mode, untill a cycle is completed.
As described above, the present invention charge type streamline gradual approaching A/D converter and its control method, have with
Lower beneficial effect：
Control comparator to be toggled between high-order capacitor array and bit capacitor array by ON-OFF control circuit, make
Comparator within the whole work period without idle state, improve the operating efficiency of comparator；Simultaneously, it is not necessary to eliminate two
Imbalance between comparator and calibrated, save ADC conversion times；Because the capacitance of weight electric capacity is smaller, and only adopt
With a comparator, the parasitic capacitance increase problem of step on capacitor array caused by two comparators is avoided, is improved
ADC precision and speed, the design difficulty of circuit is simplified, reduce the area of circuit.
Brief description of the drawings
Fig. 1 is shown as the present invention and provides a kind of existing analog-digital converter schematic diagram of Piplined-SAR structures 1；
Fig. 2 is shown as the present invention and provides a kind of existing analog-digital converter timing diagram of Piplined-SAR structures 1；
Fig. 3 is shown as a kind of analog-digital converter schematic diagram of charge type Piplined-SAR structures provided by the invention；
Fig. 4 is shown as a kind of timing diagram of the analog-digital converter of charge type Piplined-SAR structures provided by the invention；
Fig. 5 is shown as a kind of working condition of the analog-digital converter of charge type Piplined-SAR structures provided by the invention
Decompose explanation figure；
Fig. 6 is shown as a kind of control method stream of charge type streamline gradual approaching A/D converter provided by the invention
Cheng Tu.
Component label instructions：
1 high-order capacitor array
2 bit capacitor arrays
3 ON-OFF control circuits
4 comparators
5 Approach by inchmeal deposit logic circuit
6 two selecting switch arrays
Embodiment
Illustrate embodiments of the present invention below by way of specific instantiation, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through specific realities different in addition
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.It should be noted that in the case where not conflicting, following examples and implementation
Feature in example can be mutually combined.
It should be noted that the diagram provided in following examples only illustrates the basic structure of the present invention in a schematic way
Think, only show the component relevant with the present invention in schema then rather than according to component count, shape and the size during actual implement
Draw, kenel, quantity and the ratio of each component can be a kind of random change during its actual implementation, and its assembly layout kenel
It is likely more complexity.
Referring to Fig. 3, be a kind of analog-digital converter schematic diagram of charge type Piplined-SAR structures provided by the invention,
With reference to the schematic diagram of first embodiment (structure 1), equally by taking the analog-digital converter of 8 SAR structures as an example, the present embodiment includes：
High-order capacitor array 1, for sampling input voltage signal, it is additionally operable to carry out charge and discharge to electric capacity；
Wherein, the high-order capacitor array DAC1 includes multiple high weight electric capacity and the first compensating electric capacity, wherein, it is described most
The capacitance of low powerful electric capacity is identical with the first compensating electric capacity capacitance；One end connection input voltage letter of sampling switch
Number, its other end connects the upper step of electric capacity in the high-order capacitor array, and the lower step of multiple high weight electric capacity is corresponding
Respective two selecting switch arrays are connected, the lower step of first compensating electric capacity connects the first reference voltage.
Because the present embodiment is preferably 8 ADC, three weight electric capacity are from left to right successively in this high-order capacitor array
For 128C, 64C, 32C, compensating electric capacity is identical with the capacitance of the weight electric capacity of lowest order, is also 32C, wherein, C is unit electricity
Hold capacitance, and corresponding two selecting switch arrays are three groups, correspond to the higher level of three weight electric capacity, in this application electric capacity respectively
Plate is the pole plate above electric capacity in circuit diagram, and lower step is the pole plate below electric capacity in circuit diagram.
Bit capacitor array 2, its capacitance is identical with the capacitance of high-order capacitor array, for being filled, being put to electric capacity
Electricity；
Wherein, the bit capacitor array DAC2 includes multiple low weight electric capacity and the second compensating electric capacity, wherein, described
Two compensating electric capacities and the capacitance sum of multiple low weight electric capacity are equal to the capacitance of high-order capacitor array；One end of reset switch
Ground connection, its other end connect the upper step of electric capacity in the bit capacitor array, the lower step pair of multiple low weight electric capacity
Respective two selecting switch arrays should be connected, the lower step of second compensating electric capacity connects the first reference voltage.
Wherein, because high-order capacitor array DAC1 is identical with bit capacitor array DAC2 capacitance, multiple low weight electricity
Capacitance 8C, 4C, 2C, 1C and capacitance of appearance are 241C compensating electric capacity, and corresponding two selecting switch arrays are four groups, point
Dui Ying not four weight electric capacity.
In the present embodiment, the selecting switch of two selecting switch arrays connects the first reference voltage V refp respectively
It is high according to the corresponding fiducial value exported of each electric capacity with the second reference voltage V refn, the Approach by inchmeal deposit logic circuit
The electric capacity of low Reverse Turning Control capacitor array is closed into the first reference voltage V refp or the second reference voltage V refn, wherein, first
Reference voltage V refp magnitude of voltage is more than the second reference voltage V refn magnitude of voltage.
ON-OFF control circuit 3, its input is connected with the output end of the high-low position capacitor array, for controlling a high position
The working condition of capacitor array 1, bit capacitor array 2, it is additionally operable to the residual error voltage of the high-order capacitor array being total to electric charge
The mode of enjoying is distributed to bit capacitor array；
Wherein, the ON-OFF control circuit includes first switch S1, second switch S2 and the 3rd switch S3, wherein, first
Switch S1 and sampling switch Sc is controlled by same clock signal, the switch S3 alternate conduction control ratios of the first switch S1 and the 3rd
Input compared with device toggles between high-order capacitor array 1 and bit capacitor array 2.
Specifically, in an ADC work period, two comparators in structure 1 shown in analog-digital converter are in ADC half
It is to be in idle state in the individual work period.The present invention is opened by the first switch S1 and the 3rd that is connected with comparator COMP inputs
S3 alternate conduction and shut-off is closed, realizes comparator COMP between high-order capacitor array DAC1 and bit capacitor array DAC2
Toggle so that in an ADC work period, comparator is all in working condition, so that a comparator only is used,
The operating efficiency of comparator is improved, avoids engineering problem caused by comparator imbalance elimination process.
When and only described first switch S1 and sampling switch Sc close when, the high-order capacitor array 1 is to input voltage
Signal is sampled, and the bit capacitor array 2 is sequentially communicated comparator 4 and Approach by inchmeal deposit logic circuit 5 is carried out gradually
Approach and produce low four-digit number code；When the first switch S1 and sampling switch Sc is closed and reset switch Sr is closed, institute
Higher level's plate earthing of bit capacitor array 2 is stated, the high-order capacitor array 1 is sequentially communicated comparator 4 and Approach by inchmeal deposit is patrolled
Collect circuit 5 and carry out the high four-digit number code of Approach by inchmeal generation.
When after generating high four-digit number code and when only described second switch S2 is turned on, the high-order capacitor array 1 is with electricity
Lotus sharing mode divides residual error voltage equally electric capacity bit capacitor array 2.
One comparator 4, its input are connected with the output end of the ON-OFF control circuit, for right in half period
Bit capacitor array is gradually compared, and high-order capacitor array is gradually compared in other half period, by fiducial value
It is sequentially output；
Approach by inchmeal deposits logic circuit 5, and its input is connected with the output end of the comparator, for according to the ratio
Compared with the switch of two selecting switch arrays 6 of the fiducial value closure connection high-low position capacitor array of device 4, until closing all electricity
The switch for holding two selecting switch arrays of array obtains the data signal of input voltage signal conversion.
In the present embodiment, the digit of the analog-digital converter of SAR structures can be set according to demand, do not repeated one by one herein.
Comparator is controlled to be toggled between high-order capacitor array and bit capacitor array by ON-OFF control circuit so that comparator
Without idle state within the whole work period, the operating efficiency of comparator is improved；Simultaneously, it is not necessary to eliminate two comparators it
Between imbalance and calibrated, save ADC conversion times；Because the capacitance of weight electric capacity is smaller, and only with a ratio
Compared with device, avoiding the parasitic capacitance of step on capacitor array caused by two comparators increases problem, improves ADC precision
With speed, the design difficulty of circuit is simplified, reduces the area of circuit.
Referring to Fig. 4, be shown as a kind of analog-digital converter of charge type Piplined-SAR structures provided by the invention
Timing diagram, and Fig. 5, it is shown as a kind of work of the analog-digital converter of charge type Piplined-SAR structures provided by the invention
State decomposition explanation figure, including：
High-order capacitor array DAC1 and bit capacitor array DAC2 total capacitance size is identical, by a complete cycle
It is divided into P1, P2, P3 and P4 four-stage.Within the P1 stages, when ADC is in sample phase, sampling switch Sc and first switch
S1 is turned on, and reset switch Sr, second switch S2 and the 3rd switch S3 disconnect, and high-order capacitor array DAC1 is to input voltage signal
VIN is sampled, and comparator COMP positive input is connected with bit capacitor array DAC2, and bit capacitor array DAC2 passes through
Comparator COMP and Approach by inchmeal deposit logic circuit SAR Logic carry out Approach by inchmeal, complete conversion and produce low 4-digit number
Code is (from up to low level gradually step magnitude of voltage on more each electric capacity, if comparator COMP positive input voltage is more than
Negative input, its output valve are " 1 ", are caused in two selecting switch arrays of capacitance connection in bit capacitor array DAC2
First reference voltage Vref p, if on the contrary, comparator COMP positive input voltage is not more than negative input, its is defeated
It is " 0 " to go out value, causes the second reference voltage in two selecting switch arrays of capacitance connection in bit capacitor array DAC2
Vrefn, three weight electric capacity are deposited the Reverse Turning Control of logic circuit by Approach by inchmeal).Hereafter, within the P2 stages, sampling is opened
Close Sc turn on first switch S1 and reset switch Sr is also switched on, the 3rd switch S3 and second switch S2 disconnections, by closing the
Three switch S3, bit capacitor array DAC2 top crown are reset to ground.Next, within the P3 stages, first switch S1, second
Switch S2, reset switch Sr and sampling switch Sc are in off-state, and the only the 3rd switch S3 is in the conduction state, comparator
COMP positive input is connected with high-order capacitor array DAC1, and high-order capacitor array DAC1 is by comparator COMP and gradually forces
Nearly deposit logic circuit SAR Logic carry out Approach by inchmeal, and completion conversion produces high four-digit number code and (gradually compared from up to low level
Step magnitude of voltage on more each electric capacity, if comparator COMP positive input voltage is more than negative input, its output valve
For " 1 ", cause the first reference voltage Vref p in two selecting switch arrays of capacitance connection in high-order capacitor array DAC1,
On the contrary, if comparator COMP positive input voltage is not more than negative input, its output valve is " 0 ", causes a high position
The second reference voltage Vref n in two selecting switch arrays of capacitance connection in capacitor array DAC1；Four weight electric capacity are equal
By the Reverse Turning Control of Approach by inchmeal deposit logic circuit).Meanwhile generate residual error electricity in high-order capacitor array DAC2 top crown
Press Vr.Within the P4 stages, after high four-digit number code produces, second switch S2 conductings, rest switch (first switch S1, the 3rd
Switch S3, reset switch Sr and sampling switch Sc) it is off, due to high-order capacitor array DAC1 and bit capacitor array
DAC2 capacitance size is identical, shares principle (principle of charge conservation) from electric charge, now capacitor array DAC1 and electric capacity
The voltage of array DAC2 top crowns is 0.5Vr, thus completes an ADC work period.Due in bit capacitor array DAC2
It is 241C compensating electric capacities provided with capacitance, compensate for decay of the residual error voltage from Vr to 0.5Vr, meanwhile, bit capacitor array
The capacitance of DAC2 highest order weight electric capacity is 8C, rather than 16C, and remaining weight electric capacity is reduced by binary scale.It is so that electric
After lotus is shared, bit capacitor array DAC2 can carry out Approach by inchmeal by normal mode.
Wherein, the preferred dynamic latch comparator of comparator, power consumption can be effectively reduced, and Approach by inchmeal deposit logic is electric
Road is preferably asynchronous logic, can effectively improve the conversion speed of circuit and reduce converted power consumption.
On the other hand, due to second switch S2 presence, by turning on second switch S2, can be to residual error voltage at
Reason, its effect is similar with the effect of residue amplifier in Piplined structure ADCs, but is realized using switch, and traditional
Piplined-SAR structure ADCs are compared, and greatly reduce the complexity and power consumption of circuit, so as to significantly reduce the design of circuit
Difficulty, reduce the area of circuit.Further, by sampling switch Sc, first switch S1 and the 3rd switch S3, by high-order electric capacity
Array DAC1 and bit capacitor array DAC2 accesses the input of comparator in turn so that a ratio has only been used in whole ADC
Compared with device, compared with traditional Piplined-SAR structure ADCs, reduce the number of comparator, therefore, for single channel design
Speech, it is not necessary to imbalance is done to comparator and is eliminated, simplifies the design difficulty of circuit, reduces the area of circuit.
In addition, embodiments of the invention are preferably the analog-digital converter of 8 SAR structures, but charge type streamline is gradually
The digit for approaching type analog-to-digital converter is not limited solely to 8, can according to said structure according to user's request make lower-order digit or
The analog-digital converter of seniority top digit this type, is not repeated one by one herein.
Referring to Fig. 6, it is a kind of controlling party of charge type streamline gradual approaching A/D converter provided by the invention
Method flow chart, including：
Step S1, high potential capacitor array start to sample to input voltage signal, ON-OFF control circuit control low potential electricity
Hold array Approach by inchmeal；Wherein, comparator is gradually compared bit capacitor array in half period, all until closing
The switches of two selecting switch arrays of capacitor array, obtain the LSB corresponding to bit capacitor array conversion input voltage signal
Digital code；
Specifically, control circuit makes bit capacitor array sample input voltage signal, Approach by inchmeal deposit logic
It is (0, V that circuit, which controls the initial connected mode of the bit capacitor array,REFP, VREFP……VREFP), wherein, VREFPVoltage
More than Vrefn, i.e., high level, low level are represented respectively, comparing the difference of the initial voltage of sampled voltage and bit capacitor array is
It is no to be more than zero, the peak of the bit capacitor array is determined according to comparative result；
Similarly, bit capacitor array is gradually compared from high to low in half period, the ratio exported according to comparator
Compared with the switch that value closes all two selecting switch arrays of capacitor array, the second peak, the 3rd peak ... are determined respectively
The value of minimum, obtain the digital code of the LSB corresponding to bit capacitor array conversion input voltage signal.
Step S2, control circuit control low potential capacitor array ground connection reset, and the high potential capacitor array is to input electricity
Signal is pressed to complete sampling；
Specifically, when the control low potential capacitor array ground connection reset of control circuit control circuit, high-order capacitor array is also made
Complete to send out input voltage signal and sample.
Step S3, when the ON-OFF control circuit controls high potential capacitor array Approach by inchmeal；Wherein, comparator is in addition
High-order capacitor array is gradually compared in half period, exports the digital code of the MSB corresponding to high-order capacitor array, and institute
The top crown for stating high-order capacitor array generates residual error voltage；
Specifically, Approach by inchmeal deposit logic circuit control the high-order capacitor array initial connected mode be (0,
VREFP, VREFP……VREFP), whether the difference for comparing the initial voltage of sampled voltage and high-order capacitor array is more than zero, according to comparing
As a result the peak of the high-order capacitor array is determined；
Similarly, high-order capacitor array is gradually compared from high to low in another half period, closed successively according to comparative result
The switch of two selecting switch arrays of high-order capacitor array is closed, until closing all two selecting switch arrays of capacitor array
Switch, the digital code of the MSB corresponding to high-order capacitor array conversion input voltage signal is obtained, meanwhile, in high-order capacitor array
Top crown generate residual error voltage.
Step S4, when the ON-OFF control circuit control high potential capacitor array be connected with low potential capacitor array, by institute
State high potential capacitor array residual error voltage to be distributed to bit capacitor array with electric charge sharing mode, until a cycle completion is
Only.
Specifically, because high-order capacitor array is identical with the capacitance size of bit capacitor array, principle is shared by electric charge
(principle of charge conservation) understands that now the voltage of capacitor array and capacitor array top crown is 0.5Vr, thus completes the one of ADC
The individual work period.Due to provided with capacitance being 241C compensating electric capacities in bit capacitor array, compensate for residual error voltage from Vr to
0.5Vr decay, meanwhile, the capacitance of the highest order weight electric capacity of bit capacitor array is 8C, rather than 16C, remaining weight electricity
Hold and reduced by binary scale.So that after electric charge is shared, bit capacitor array can carry out Approach by inchmeal by normal mode.
In the present embodiment, the present invention provide Piplined-SAR structures analog-digital converter relative to prior art and
Speech, production cost is less expensive, is more suitable for popularization and application.Such as：The analog-digital converter of structure 1 needs two comparators, a fortune
Amplifier is calculated, and the offset voltage for needing to eliminate between two comparators is calibrated, and need reference voltage to be also required to
Two groups.And the circuit structure of the present invention only needs a comparator, without calibration comparator offset voltage, without operational amplifier,
Only need one group of reference voltage to be worth as the reference voltage, not only increase ADC precision and speed, the design for simplifying circuit is difficult
Degree, reduce the area of circuit.
In summary, the present invention controls comparator in high-order capacitor array and bit capacitor array by ON-OFF control circuit
Between toggle so that comparator without idle state, improves the operating efficiency of comparator within the whole work period；Together
When, it is not necessary to eliminate the imbalance between two comparators and calibrated, save ADC conversion times；Due to weight electric capacity
Capacitance is smaller, and only with a comparator, the parasitism for avoiding step on capacitor array caused by two comparators is electric
Hold increase problem, improve ADC precision and speed, simplify the design difficulty of circuit, reduce the area of circuit.So
The present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.It is any ripe
Know the personage of this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
- A kind of 1. charge type streamline gradual approaching A/D converter, it is characterised in that including：High-order capacitor array, for sampling input voltage signal, it is additionally operable to carry out charge and discharge to electric capacity；Bit capacitor array, its capacitance is identical with the capacitance of high-order capacitor array, for carrying out charge and discharge to electric capacity；ON-OFF control circuit, its input are connected with the output end of the high-low position capacitor array, for controlling high-order electric capacity battle array Row, the working condition of bit capacitor array, it is additionally operable to the residual error voltage of the high-order capacitor array with electric charge sharing mode point Cloth is to bit capacitor array；One comparator, its input are connected with the output end of the ON-OFF control circuit, in half period to low level Capacitor array is gradually compared, and high-order capacitor array is gradually compared in other half period, by fiducial value successively Output；Approach by inchmeal deposits logic circuit, and its input is connected with the output end of the comparator, for according to the comparator The switch of two selecting switch arrays of the fiducial value closure connection high-low position capacitor array of output, until closing all electric capacity The switch of two selecting switch arrays of array obtains the data signal of input voltage signal conversion.
- 2. charge type streamline gradual approaching A/D converter according to claim 1, it is characterised in that the high position Capacitor array includes multiple high weight electric capacity and the first compensating electric capacity, wherein, the capacitance of the minimum powerful electric capacity with First compensating electric capacity capacitance is identical；One end connection input voltage signal of sampling switch, its other end connection high-order electricity Hold the upper step of electric capacity in array, the lower step of multiple high weight electric capacity correspondingly connects respective two selecting switch battle arrays Row, the lower step of first compensating electric capacity connect the first reference voltage.
- 3. charge type streamline gradual approaching A/D converter according to claim 1, it is characterised in that the low level Capacitor array includes multiple low weight electric capacity and the second compensating electric capacity, wherein, second compensating electric capacity and multiple low weight electricity The capacitance sum of appearance is equal to the capacitance of high-order capacitor array；One end ground connection of reset switch, the connection of its other end are described low The upper step of electric capacity, the lower step of multiple low weight electric capacity correspondingly connect respective two selecting switch in the capacitor array of position Array, the lower step of second compensating electric capacity connect the first reference voltage.
- 4. the charge type streamline gradual approaching A/D converter according to Claims 2 or 3, it is characterised in that described The selecting switch of two selecting switch arrays connects the first reference voltage and the second reference voltage, the Approach by inchmeal deposit respectively Logic circuit is closed into the first base according to the electric capacity of the corresponding fiducial value height Reverse Turning Control capacitor array exported of each electric capacity Quasi- voltage or the second reference voltage, wherein, the magnitude of voltage of the first reference voltage is more than the magnitude of voltage of the second reference voltage.
- 5. charge type streamline gradual approaching A/D converter according to claim 1, it is characterised in that the switch Control circuit includes first switch, second switch and the 3rd switch, the output of the bit capacitor array and high-order capacitor array The corresponding both ends for being connected to second switch in end, the both ends of the second switch correspondingly connect first switch, the 3rd switch, wherein, The first switch is controlled with sampling switch by same clock signal, the first switch and the 3rd switch alternate conduction control The input of comparator toggles between high-order capacitor array and bit capacitor array.
- 6. charge type streamline gradual approaching A/D converter according to claim 5, it is characterised in that when and only When the first switch closes with sampling switch, the high-order capacitor array samples to input voltage signal, the low level Capacitor array is sequentially communicated comparator and Approach by inchmeal deposit logic circuit carries out Approach by inchmeal and produces low four-digit number code；Work as institute When stating first switch with sampling switch closure and reset switch closure, higher level's plate earthing of the bit capacitor array is described High-order capacitor array is sequentially communicated comparator and Approach by inchmeal deposit logic circuit carries out Approach by inchmeal and produces high four-digit number code.
- 7. charge type streamline gradual approaching A/D converter according to claim 5, it is characterised in that when generation is high The second switch is turned on after four-digit number code and only, the high-order capacitor array is divided equally residual error voltage with electric charge sharing mode To electric capacity bit capacitor array.
- 8. a kind of charge type streamline gradual approaching A/D converter using described in any one in claim 1 to 7 Control method, including：High potential capacitor array starts to sample to input voltage signal, and ON-OFF control circuit control low potential capacitor array is gradually forced Closely；Wherein, comparator is gradually compared bit capacitor array in half period, until closing all capacitor arrays two The switch of selecting switch array, obtain the digital code of the LSB corresponding to bit capacitor array conversion input voltage signal；The control circuit control low potential capacitor array ground connection resets, and the high potential capacitor array is complete to input voltage signal Into sampling；When the ON-OFF control circuit controls high potential capacitor array Approach by inchmeal；Wherein, comparator is in other half period High-order capacitor array is gradually compared, exports the digital code of the MSB corresponding to high-order capacitor array, and the high-order electric capacity The top crown of array generates residual error voltage；When the ON-OFF control circuit control high potential capacitor array be connected with low potential capacitor array, by the high potential electric capacity Array residual error voltage is distributed to bit capacitor array with electric charge sharing mode, untill a cycle is completed.
- 9. the control method of charge type streamline gradual approaching A/D converter according to claim 8, the comparison Device is gradually compared bit capacitor array in half period, until closing all two selecting switch arrays of capacitor array Switch, obtain bit capacitor array conversion input voltage signal corresponding to LSB digital code the step of, including：It is (0, V that Approach by inchmeal deposit logic circuit, which controls the initial connected mode of the bit capacitor array,REFP, VREFP…… VREFP), whether the difference for comparing the initial voltage of sampled voltage and bit capacitor array is more than zero, according to determining comparative result The peak of bit capacitor array；Similarly, bit capacitor array is gradually compared in half period, bit capacitor is closed according to comparative result successively The switch of two selecting switch arrays of array, the switch until closing all two selecting switch arrays of capacitor array, is obtained The digital code of LSB corresponding to bit capacitor array conversion input voltage signal.
- 10. the control method of charge type streamline gradual approaching A/D converter according to claim 8, the comparison Device is gradually compared high-order capacitor array in other half period, exports the number of the MSB corresponding to high-order capacitor array Character code, and the step of the top crown of the high-order capacitor array generates residual error voltage, including：It is (0, V that Approach by inchmeal deposit logic circuit, which controls the initial connected mode of the high-order capacitor array,REFP, VREFP…… VREFP), whether the difference for comparing the initial voltage of sampled voltage and high-order capacitor array is more than zero, according to determining comparative result The peak of high-order capacitor array；Similarly, high-order capacitor array is gradually compared from high to low in another half period, height is closed according to comparative result successively The switch of two selecting switch arrays of position capacitor array, until closing opening for all two selecting switch arrays of capacitor array Close, obtain the digital code of the MSB corresponding to high-order capacitor array conversion input voltage signal, meanwhile, in high-order capacitor array Top crown generates residual error voltage.
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