CN113162624B - Analog-to-digital converter with pooling function - Google Patents
Analog-to-digital converter with pooling function Download PDFInfo
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- CN113162624B CN113162624B CN202110599642.8A CN202110599642A CN113162624B CN 113162624 B CN113162624 B CN 113162624B CN 202110599642 A CN202110599642 A CN 202110599642A CN 113162624 B CN113162624 B CN 113162624B
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- 238000011176 pooling Methods 0.000 title claims abstract description 64
- 238000006243 chemical reaction Methods 0.000 claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 24
- 238000005070 sampling Methods 0.000 claims description 21
- 230000003139 buffering effect Effects 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 abstract description 12
- 230000006870 function Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000013528 artificial neural network Methods 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013527 convolutional neural network Methods 0.000 description 1
- 238000013135 deep learning Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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Abstract
The invention discloses an analog-to-digital converter with a pooling function, and belongs to the technical field of integrated circuits. The analog-to-digital converter comprises a pooling circuit and an analog-to-digital conversion circuit, wherein the pooling circuit and the analog-to-digital conversion circuit share a capacitor array, and the data matrix can be pooled and read in an analog domain by introducing less power consumption and area, so that the dimension of the data matrix is reduced. The invention effectively reduces the working times of the analog-digital conversion circuit, omits frequent comparison operation of a digital domain, reduces the consumption of storage space and greatly improves the operation efficiency of the integrated chip technology.
Description
Technical Field
The invention relates to an analog-to-digital converter with a pooling function, and belongs to the technical field of integrated circuits.
Background
The convolution algorithm commonly used in the current image identification needs to intensively process a large amount of regular operations and generate a large amount of intermediate data. Based on the traditional von neumann computing architecture, the computing and storage functions are separated, and huge data throughput can bring about huge power consumption overhead; and with the rapid improvement of the performance of the processor, the performance gap between the processor and the memory is larger and larger, and the problem of accessing the memory power consumption wall is more and more prominent. Therefore, researchers have proposed a computing architecture with a memory as a core, namely a memory-computing integrated architecture, and the problem of accessing memory power consumption walls is solved or weakened from the aspect of memory by performing computing fusion. The architecture is often applied to deep learning neural networks, and can efficiently realize vector matrix multiplication.
The typical convolutional neural network architecture consists of a convolutional layer, a pooling layer, a full-connection layer and the like, and the basic calculation flow is as follows: the input matrix (usually from an image) is transmitted into a network, the convolution layer and the pooling layer jointly complete feature extraction of input data, and the full connection layer synthesizes feature information and performs functions such as classification. The convolution operation in the convolution neural network can be performed in the analog domain by using the integrated architecture of memory operation, the feature extraction of the input matrix is completed, but the dimension is still high, and the data is usually subjected to pooling processing, wherein the maximum pooling operation has the effect of replacing a certain area of the input matrix with a value, if the operation result after the convolution operation is output to the digital circuit through the reading circuit, as shown in fig. 1, the pooling processing is performed in the digital domain, frequent comparison operation is required, and a large amount of power consumption and storage space are consumed, so that the operation efficiency of the integrated memory chip is affected.
Disclosure of Invention
In order to improve the operation efficiency of the integrated chip technology, the invention provides an analog-to-digital converter with a pooling function, which comprises: the device comprises a pooling circuit and an analog-to-digital conversion circuit, wherein the pooling circuit is connected with the analog-to-digital conversion circuit; the analog-to-digital conversion circuit is of a general capacitor SAR ADC structure and comprises an SAR comparison control module and a capacitor array DAC; the pooling circuit and the analog-to-digital conversion circuit share a capacitor array DAC; the pooling circuit compares the voltages of the input signals, and samples and holds the maximum value to realize maximum pooling; the analog-to-digital conversion circuit is used for converting the held pooling result into a digital signal and outputting the digital signal.
Optionally, the pooling circuit includes: a comparator Comp, a capacitor array DAC, a sampling switch S1 and a reset switch S2;
the output end of the comparator Comp is connected with the control end of the sampling switch S1, and the output ends of the sampling switches S1 and S2 are connected with the upper polar plate VP of the DAC capacitor array and the inverting input end of the comparator Comp.
Optionally, the comparator Comp adopts a dynamic latch structure, and when Clkc is low level, the sampling signal Sample is reset to 0; when Clkc is at high level, comparing input signal VIN with holding signal VH, and latching and outputting comparison result Sample to control sampling switch S1 to be turned on or off.
Optionally, the upper plate VP of the capacitor array DAC maintains a maximum value.
Optionally, the sampling switch S1 is configured to control whether to Sample the input signal, and when the Sample signal is high, S1 is turned on; when the Sample signal is low, S1 is off.
Optionally, the reset switch S2 is configured to control whether to reset the holding voltage VP of the DAC to 0, and when the rst signal is high, S2 is turned on; when the Rst signal is low, S2 is turned off.
Optionally, the analog-to-digital converter further includes a voltage buffer unit Buf.
Optionally, the Buf input end is connected to the upper plate VH of the DAC capacitor array, and the output end is connected to the inverting input end of the comparator Comp. The Buf is used for carrying out following buffering on the voltage signal VP held by the DAC, and the output signal VH is connected with the Comp reverse input end and is used for isolating the influence of the kick noise of the comparator on the held signal VP.
The invention has the beneficial effects that:
compared with the prior art, the analog-to-digital converter with the pooling function has the following advantages: the analog-to-digital converter designed by the invention integrates a pooling function, the pooling circuit and the analog-to-digital conversion circuit share a capacitor array, and the data matrix can be pooled and read in an analog domain by introducing less power consumption and area, so that the dimension of the data matrix is reduced. The invention effectively reduces the working times of the analog-digital conversion circuit, omits frequent comparison operation of a digital domain, reduces the consumption of storage space and greatly improves the operation efficiency of the integrated chip technology.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a memory architecture based on ADC readout.
Fig. 2 is a block diagram of an analog-to-digital converter with pooling.
Fig. 3 is a schematic diagram of a general architecture of a memory based on a Pooling ADC readout.
Fig. 4 is a block diagram of an analog-to-digital converter with a buffering unit and a pooling function.
FIG. 5 is a timing diagram illustrating the operation of a 2x2 sized pooling core according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings.
Embodiment one:
referring to fig. 2, the analog-to-digital converter includes a pooling circuit and an analog-to-digital conversion circuit, wherein the pooling circuit is connected with the analog-to-digital conversion circuit; the analog-to-digital conversion circuit is of a general capacitor SAR ADC structure and comprises an SAR comparison control module and a capacitor array DAC; the pooling circuit and the analog-to-digital conversion circuit share a capacitor array DAC.
When Clks is high, the analog-to-digital conversion circuit is in a stage to be sampled; when clk is low, the analog-to-digital conversion circuit is in the conversion stage.
The pooling circuit compares the voltages of the input signals, and samples and holds the maximum value to realize maximum pooling; the analog-to-digital conversion circuit is used for converting the held pooling result into a digital signal and outputting the digital signal.
The pooling circuit comprises a comparator Comp, a capacitor array DAC, a sampling switch S1 and a reset switch S2; the output end of the comparator Comp is connected with the control end of the sampling switch S1, and the output ends of the sampling switches S1 and S2 are connected with the upper polar plate VP of the DAC capacitor array and the inverting input end of the comparator Comp.
The comparator Comp adopts a dynamic latch structure, and when Clkc is low level, the sampling signal Sample is reset to 0; when Clkc is at high level, comparing input signal VIN with holding signal VH, and latching and outputting comparison result Sample to control sampling switch S1 to be turned on or off.
The upper plate VP of the capacitor array DAC maintains a maximum value.
The sampling switch S1 is used for controlling whether to Sample an input signal, and when the Sample signal is high, the S1 is conducted; when the Sample signal is low, S1 is off.
The reset switch S2 is configured to control whether to reset the holding voltage VP of the DAC to 0, and when the rst signal is high, S2 is turned on; when the Rst signal is low, S2 is turned off.
Compared with the prior analog-to-digital converter which performs pooling processing in a digital domain, the analog-to-digital converter with pooling function provided by the invention realizes pooling operation on convolution operation results in an analog domain, and can further reduce dimension and further reduce the calculated amount in the digital domain. The invention combines the pooling function on the basis of the analog-to-digital conversion circuit, can pool the data matrix in the analog domain and read out, reduces the dimension of the data matrix, effectively reduces the working times of the analog-to-digital conversion circuit, omits frequent comparison operation in the digital domain, reduces the consumption of storage space, and further improves the operation efficiency of the integrated chip technology of memory calculation.
The general architecture diagram of the integrated architecture of the analog-digital converter with the pooling function is shown in fig. 3, and compared with the existing integrated architecture of the analog-digital converter based on ADC reading, the existing architecture can realize convolution operation and reading, and then perform pooling operation in the digital domain. Based on the integrated overall architecture of the analog-to-digital converter with the pooling function, the pooling operation can be performed on the convolution operation result before the convolution operation result is read out, so that the working times of the analog-to-digital conversion circuit are reduced, the speed requirement of the analog-to-digital conversion circuit is further reduced, and the low-power consumption design is facilitated. Meanwhile, the output under the framework based on the invention is convolution and pooling results, compared with the existing framework, the pooling operation of the digital domain is omitted, and a large amount of storage space is saved.
Embodiment two:
referring to fig. 4, the analog-to-digital converter with pooling function provided in this embodiment adopts an analog-to-digital converter structure with buffering unit and pooling function.
The voltage buffer unit Buf is introduced on the basis of the structure of the analog-to-digital converter shown in fig. 2 provided in the first embodiment, the input end of the Buf is connected with the upper polar plate VH of the DAC capacitor array, and the output end of the Buf is connected with the inverting input end of the comparator Comp. The Buf is used for carrying out following buffering on the voltage signal VP held by the DAC, and the output signal VH is connected with the Comp reverse input end and is used for isolating the influence of the kick noise of the comparator on the held signal VP.
The invention provides an analog-digital converter with a pooling function, taking a pooling core with a size of 2x2 as an example, and a working time sequence chart is shown in figure 5. There are 4 positive input signals VIN (V1, V2, V3, V4) per cycle, 4 comparisons are made, and the maximum pooled result is digitally quantized out. The specific working process is as follows:
a reset phase: the RST signal is high, the reset switch S2 is conducted, and the upper polar plate voltage VP of the DAC is reset to 0; the Clks signal is high, and the analog-to-digital conversion circuit ends the last conversion state and enters a state to be sampled.
(II) pooling stage: RST signal is set to 0, and reset switch S2 is turned off; the first time Clkc is switched to high level, the comparator compares the first input signal V1 with VH, and since vh=vp=0, the comparator output signal Sample is high level, the sampling switch S1 is turned on, and the DAC samples and holds the input signal V1, that is, vh=vp=v1. After the second input signal V2 is established, clkc is switched to a high level for the second time, the comparator compares the input signal V2 with the holding signal V1, if V2> V1, the comparator outputs Sample to be a high level, the sampling switch S1 is turned on, and the DAC samples and holds the input signal V2, that is, vh=vp=v2; if V2< V1, the comparator output Sample is low, the sampling switch S1 remains off, and the DAC remains on, i.e., vh=vp=v1. The comparison of the input signals V3 and V4 is then done in turn on the same principle and the input signal is sampled or held in the previous state.
(III) an analog-to-digital conversion stage: after the circuit finishes the pooling operation, the Clks signal is switched to a low level, and the analog-to-digital conversion circuit quantifies the pooling result held by the DAC and outputs an N-bit digital signal.
The analog-to-digital converter with the pooling function is also suitable for pooling cores with other sizes, only needs to correspond the pooling process Clkc signals to the switching times of the input signals, and each period has m positive input signals VIN (V1-Vm), and performs m times of comparison in total, and performs digital quantization output on the maximum pooling result.
The analog-to-digital converter designed by the invention integrates a pooling function, the pooling circuit and the analog-to-digital conversion circuit share a capacitor array, and the data matrix can be pooled and read in an analog domain by introducing less power consumption and area, so that the dimension of the data matrix is reduced. The invention effectively reduces the working times of the analog-digital conversion circuit, omits frequent comparison operation of a digital domain, reduces the consumption of storage space and greatly improves the operation efficiency of the integrated chip technology.
Some steps in the embodiments of the present invention may be implemented by using software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (1)
1. An analog-to-digital converter with pooling, the analog-to-digital converter comprising: the device comprises a pooling circuit and an analog-to-digital conversion circuit, wherein the pooling circuit is connected with the analog-to-digital conversion circuit; the analog-to-digital conversion circuit is of a general capacitor SAR ADC structure and comprises an SAR comparison control module and a capacitor array DAC; the pooling circuit and the analog-to-digital conversion circuit share a capacitor array DAC; the pooling circuit compares the voltages of the input signals, and samples and holds the maximum value to realize maximum pooling; the analog-to-digital conversion circuit is used for converting the held pooling result into a digital signal and outputting the digital signal;
the pooling circuit includes: a comparator Comp, a capacitor array DAC, a sampling switch S1 and a reset switch S2;
the output end of the comparator Comp is connected with the control end of the sampling switch S1, and the output ends of the sampling switch S1 and the reset switch S2 are connected with the upper polar plate VP of the DAC capacitor array and the inverting input end of the comparator Comp;
the comparator Comp adopts a dynamic latch structure, and when Clkc is low level, the sampling signal Sample is reset to 0; when Clkc is at a high level, comparing the magnitude of an input signal VIN with that of a holding signal VH, and latching and outputting a comparison result Sample to control the on or off of a sampling switch S1;
the maximum value of the upper polar plate VP of the capacitor array DAC is kept;
the sampling switch S1 is used for controlling whether to Sample an input signal, and when the Sample signal is high, the S1 is conducted; when the Sample signal is low, S1 is disconnected;
the reset switch S2 is configured to control whether to reset the holding voltage VP of the DAC to 0, and when the rst signal is high, S2 is turned on; when the Rst signal is low, S2 is disconnected;
the analog-to-digital converter further comprises a voltage buffer unit Buf;
the input end of the Buf is connected with the upper polar plate VH of the DAC capacitor array, and the output end of the Buf is connected with the inverting input end of the comparator Comp; the Buf is used for carrying out following buffering on the voltage signal VP held by the DAC, and the output signal VH is connected with the Comp reverse input end and is used for isolating the influence of the kick noise of the comparator on the held signal VP.
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| CN104079298A (en) * | 2014-06-24 | 2014-10-01 | 复旦大学 | Successive approximation type analog-to-digital converter of self-calibration bridge-connection capacitor structure |
| CN107231153A (en) * | 2017-05-09 | 2017-10-03 | 大连理工大学 | Gradually-appoximant analog-digital converter for monolithic integrated sensor |
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| US10135453B2 (en) * | 2016-01-06 | 2018-11-20 | Disruptive Technologies Research As | SAR ADC with threshold trigger functionality for reduced power consumption |
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|---|---|---|---|---|
| CN104079298A (en) * | 2014-06-24 | 2014-10-01 | 复旦大学 | Successive approximation type analog-to-digital converter of self-calibration bridge-connection capacitor structure |
| CN107231153A (en) * | 2017-05-09 | 2017-10-03 | 大连理工大学 | Gradually-appoximant analog-digital converter for monolithic integrated sensor |
| CN107528594A (en) * | 2017-08-25 | 2017-12-29 | 中国电子科技集团公司第二十四研究所 | Charge type streamline gradual approaching A/D converter and its control method |
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