CN113162624A - Analog-digital converter with pooling function - Google Patents
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- CN113162624A CN113162624A CN202110599642.8A CN202110599642A CN113162624A CN 113162624 A CN113162624 A CN 113162624A CN 202110599642 A CN202110599642 A CN 202110599642A CN 113162624 A CN113162624 A CN 113162624A
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- 238000011176 pooling Methods 0.000 title claims abstract description 67
- 238000006243 chemical reaction Methods 0.000 claims abstract description 33
- 239000003990 capacitor Substances 0.000 claims abstract description 17
- 238000005070 sampling Methods 0.000 claims description 21
- 230000003139 buffering effect Effects 0.000 claims description 5
- 239000011159 matrix material Substances 0.000 abstract description 13
- 230000006870 function Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 6
- 238000004364 calculation method Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000013527 convolutional neural network Methods 0.000 description 2
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- 238000013528 artificial neural network Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013135 deep learning Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
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Abstract
The invention discloses an analog-digital converter with a pooling function, and belongs to the technical field of integrated circuits. The analog-to-digital converter comprises a pooling circuit and an analog-to-digital conversion circuit, the pooling circuit and the analog-to-digital conversion circuit share a capacitor array, and a data matrix can be pooled and read out in an analog domain by introducing less power consumption and area, so that the dimension of the data matrix is reduced. The invention effectively reduces the working times of the analog-digital conversion circuit, omits the frequent comparison operation of a digital domain, reduces the consumption of storage space and greatly improves the operation efficiency of the storage and computation integrated chip technology.
Description
Technical Field
The invention relates to an analog-digital converter with a pooling function, and belongs to the technical field of integrated circuits.
Background
The convolution algorithm commonly used in the image recognition at present needs to intensively process a large amount of regular operations and generate a large amount of intermediate data. Based on the traditional von neumann computing architecture, computing and storage functions are separated, and huge data throughput brings huge power consumption expense; and with the rapid improvement of the performance of the processor, the performance difference between the processor and the memory is larger and larger, and the problem of the access power consumption wall is more and more prominent. Therefore, researchers have proposed a computing architecture with a memory as a core, that is, a storage and computation integrated architecture, and from the storage perspective, the memory access power consumption wall is solved or weakened by performing computation fusion. The framework is often applied to a deep learning neural network, and vector matrix multiplication can be efficiently realized.
The typical convolutional neural network architecture consists of convolutional layers, pooling layers, full-link layers and the like, and the basic calculation flow is as follows: the input matrix (usually from an image) is transmitted into a network, and the convolutional layer and the pooling layer jointly complete the functions of feature extraction of input data, comprehensive feature information of the full-link layer, classification and the like. The convolution operation in the convolutional neural network can be performed in the analog domain by using the storage and computation integrated architecture, so that the feature extraction of the input matrix is completed, the dimensionality is still high, and the data is usually subjected to pooling processing, wherein the maximum pooling operation is used for replacing a certain region of the input matrix with a value, if the operation result after the convolution operation is output to a digital circuit through a reading circuit, as shown in fig. 1, the pooling processing is performed in the digital domain, frequent comparison operation is required, a large amount of power consumption and storage space are consumed, and the operation efficiency of the storage and computation integrated chip is affected.
Disclosure of Invention
In order to improve the operation efficiency of the storage and computation integrated chip technology, the invention provides an analog-to-digital converter with a pooling function, which comprises: the device comprises a pooling circuit and an analog-to-digital conversion circuit, wherein the pooling circuit is connected with the analog-to-digital conversion circuit; the analog-to-digital conversion circuit is of a capacitive SAR ADC universal structure and comprises an SAR comparison control module and a capacitive array DAC; the pooling circuit and the analog-to-digital conversion circuit share a capacitor array DAC; the pooling circuit compares the voltages of input signals and samples and holds the maximum value to realize maximum pooling; and the analog-to-digital conversion circuit is used for converting the kept pooling result into a digital signal to be output.
Optionally, the pooling circuit includes: a comparator Comp, a capacitor array DAC, a sampling switch S1 and a reset switch S2;
the output end of the comparator Comp is connected with the control end of a sampling switch S1, and the output ends of the sampling switches S1 and S2 are connected with the upper plate VP of the DAC capacitor array and the inverting input end of the comparator Comp.
Optionally, the comparator Comp adopts a dynamic latch structure, and when Clkc is at a low level, the sampling signal Sample is reset to 0; when Clkc is at high level, compare the magnitude of the input signal VIN with the holding signal VH, and latch the comparison result Sample out, controlling the sampling switch S1 to be turned on or off.
Optionally, the upper plate VP of the capacitor array DAC holds a maximum value.
Optionally, the sampling switch S1 is configured to control whether to Sample the input signal, and when the Sample signal is high, S1 is turned on; when the Sample signal is low, S1 is turned off.
Optionally, the reset switch S2 is configured to control whether to reset the hold voltage VP of the DAC to 0, and when the Rst signal is high, S2 is turned on; when the Rst signal is low, S2 is off.
Optionally, the analog-to-digital converter further includes a voltage buffer unit Buf.
Optionally, the Buf input terminal is connected to the upper electrode plate VH of the DAC capacitor array, and the output terminal is connected to the inverting input terminal of the comparator Comp. Buf is used for following the buffering with voltage signal VP that DAC kept, and output signal VH connects Comp's inverting input end for the influence of the kickback noise of isolated comparator to keeping signal VP.
The invention has the beneficial effects that:
compared with the prior art, the analog-digital converter with the pooling function has the following advantages: the analog-to-digital converter designed by the invention integrates a pooling function, a pooling circuit and an analog-to-digital conversion circuit share a capacitor array, and a data matrix can be subjected to pooling operation and read out in an analog domain by introducing less power consumption and area, so that the dimension of the data matrix is reduced. The invention effectively reduces the working times of the analog-digital conversion circuit, omits the frequent comparison operation of a digital domain, reduces the consumption of storage space and greatly improves the operation efficiency of the storage and computation integrated chip technology.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a general architecture of a memory based ADC readout.
Fig. 2 is a block diagram of an analog-to-digital converter having a pooling function.
Fig. 3 is a schematic diagram of a general architecture of a memory based Pooling ADC readout.
Fig. 4 is a structural diagram of an analog-to-digital converter with a buffering unit and a pooling function.
FIG. 5 is a timing diagram illustrating the operation of a pooling core of size 2 × 2 according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment is as follows:
referring to fig. 2, the analog-to-digital converter includes a pooling circuit and an analog-to-digital conversion circuit, wherein the pooling circuit is connected to the analog-to-digital conversion circuit; the analog-to-digital conversion circuit is of a capacitive SAR ADC universal structure and comprises an SAR comparison control module and a capacitive array DAC; the pooling circuit and the analog-to-digital conversion circuit share a capacitor array DAC.
When Clks is high, the analog-to-digital conversion circuit is in a stage to be sampled; when Clks is low, the analog-to-digital conversion circuit is in the conversion phase.
The pooling circuit compares the voltages of input signals and samples and holds the maximum value to realize maximum pooling; and the analog-to-digital conversion circuit is used for converting the kept pooling result into a digital signal to be output.
The pooling circuit comprises a comparator Comp, a capacitive array DAC, a sampling switch S1 and a reset switch S2; the output end of the comparator Comp is connected with the control end of a sampling switch S1, and the output ends of the sampling switches S1 and S2 are connected with the upper plate VP of the DAC capacitor array and the inverting input end of the comparator Comp.
The comparator Comp adopts a dynamic latch structure, and when Clkc is at a low level, the sampling signal Sample is reset to 0; when Clkc is at high level, compare the magnitude of the input signal VIN with the holding signal VH, and latch the comparison result Sample out, controlling the sampling switch S1 to be turned on or off.
The upper plate VP of the capacitor array DAC holds the maximum value.
The sampling switch S1 is used for controlling whether to Sample the input signal, and when the Sample signal is high, S1 is conducted; when the Sample signal is low, S1 is turned off.
The reset switch S2 is used for controlling whether the holding voltage VP of the DAC is reset to 0, and when the Rst signal is high, S2 is conducted; when the Rst signal is low, S2 is off.
Compared with the existing analog-to-digital converter which performs pooling processing in a digital domain, the analog-to-digital converter with the pooling function provided by the invention can perform pooling operation on convolution operation results in an analog domain, so that the dimension can be further reduced, and the calculation amount of the digital domain can be further reduced. The invention integrates the pooling function on the basis of the analog-digital conversion circuit, can perform pooling operation on the data matrix in the analog domain and read out the data matrix, reduces the dimension of the data matrix, effectively reduces the working times of the analog-digital conversion circuit, saves frequent comparison operation of the digital domain, reduces the consumption of storage space and further improves the operation efficiency of the storage-computation-integrated chip technology.
A schematic diagram of a storage-computation-integrated architecture based on an analog-to-digital converter with a pooling function is shown in fig. 3, and compared with the existing storage-computation-integrated architecture based on ADC reading, the existing architecture can realize convolution operation and reading, and then perform pooling operation in a digital domain. Based on the storage and calculation integrated overall architecture of the analog-to-digital converter with the pooling function, the convolution operation result can be pooled before being read out, the working times of the analog-to-digital conversion circuit are reduced, the speed requirement of the analog-to-digital conversion circuit is further reduced, and low-power-consumption design is facilitated. Meanwhile, the output under the framework based on the invention is the result of convolution and pooling, and compared with the existing framework, the pooling operation of a digital domain is omitted, so that a large amount of storage space is saved.
Example two:
referring to fig. 4, the analog-to-digital converter with pooling function of the present embodiment adopts an analog-to-digital converter structure with pooling function with a buffer unit.
In the first embodiment, a voltage buffering unit Buf is introduced on the basis of the structure of the analog-to-digital converter shown in fig. 2, the input terminal of the Buf is connected to the upper plate VH of the DAC capacitor array, and the output terminal of the Buf is connected to the inverting input terminal of the comparator Comp. Buf is used for following the buffering with voltage signal VP that DAC kept, and output signal VH connects Comp's inverting input end for the influence of the kickback noise of isolated comparator to keeping signal VP.
The analog-to-digital converter with pooling function provided by the invention takes a pooling core with the size of 2x2 as an example, and the operation timing chart is shown in fig. 5. There are 4 positive input signals VIN (V1, V2, V3, V4) per cycle, 4 comparisons are made, and the maximum pooling result is digitally quantized and output. The specific working process is as follows:
a reset stage: RST signal is high, reset switch S2 is conducted, and upper plate voltage VP of DAC resets to 0; when the Clks signal is high, the analog-to-digital conversion circuit finishes the last conversion state and enters a state to be sampled.
(II) a pooling stage: RST signal is set to 0, and reset switch S2 is turned off; clkc switches to high level for the first time, the comparator compares the first input signal V1 with VH, and since VH ═ VP ═ 0, the comparator output signal Sample is high level, the sampling switch S1 is turned on, and the DAC samples and holds the input signal V1, that is, VH ═ VP ═ V1. When the second input signal V2 is completely established, Clkc switches to high level for the second time, the comparator compares the input signal V2 with the hold signal V1, if V2> V1, the comparator outputs Sample as high level, the sampling switch S1 is turned on, and the DAC samples and holds the input signal V2, that is, VH ═ VP ═ V2; if V2< V1, the comparator output Sample is low, the sampling switch S1 remains off, and the DAC still keeps the previous signal, i.e., VH ═ VP ═ V1. The comparison of the input signals V3 and V4 is then done in turn on the same principle and the input signal is sampled or held in the previous state.
(III) an analog-to-digital conversion stage: after the circuit finishes the pooling operation, the Clks signal is switched to low level, the analog-to-digital conversion circuit quantizes the pooling result kept by the DAC, and an N-bit digital signal is output.
The analog-to-digital converter with the pooling function provided by the invention is also suitable for pooling cores of other sizes, only needs to correspond the switching times of the input signals to the Clkc signal in the pooling process, has m positive input signals VIN (V1-Vm) in each period, performs m comparisons, and performs digital quantization output on the maximum pooling result.
The analog-to-digital converter designed by the invention integrates a pooling function, a pooling circuit and an analog-to-digital conversion circuit share a capacitor array, and a data matrix can be subjected to pooling operation and read out in an analog domain by introducing less power consumption and area, so that the dimension of the data matrix is reduced. The invention effectively reduces the working times of the analog-digital conversion circuit, omits the frequent comparison operation of a digital domain, reduces the consumption of storage space and greatly improves the operation efficiency of the storage and computation integrated chip technology.
Some steps in the embodiments of the present invention may be implemented by software, and the corresponding software program may be stored in a readable storage medium, such as an optical disc or a hard disk.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (8)
1. An analog-to-digital converter with pooling, the analog-to-digital converter comprising: the device comprises a pooling circuit and an analog-to-digital conversion circuit, wherein the pooling circuit is connected with the analog-to-digital conversion circuit; the analog-to-digital conversion circuit is of a capacitive SAR ADC universal structure and comprises an SAR comparison control module and a capacitive array DAC; the pooling circuit and the analog-to-digital conversion circuit share a capacitor array DAC; the pooling circuit compares the voltages of input signals and samples and holds the maximum value to realize maximum pooling; and the analog-to-digital conversion circuit is used for converting the kept pooling result into a digital signal to be output.
2. The analog-to-digital converter according to claim 1, wherein the pooling circuit comprises: a comparator Comp, a capacitor array DAC, a sampling switch S1 and a reset switch S2;
the output end of the comparator Comp is connected with the control end of a sampling switch S1, and the output ends of the sampling switches S1 and S2 are connected with the upper plate VP of the DAC capacitor array and the inverting input end of the comparator Comp.
3. The adc of claim 2, wherein the comparator Comp adopts a dynamic latch structure, and when Clkc is low, the sampling signal Sample is reset to 0; when Clkc is at high level, compare the magnitude of the input signal VIN with the holding signal VH, and latch the comparison result Sample out, controlling the sampling switch S1 to be turned on or off.
4. The analog-to-digital converter according to claim 3, characterized in that the upper plate VP of the capacitor array DAC holds a maximum value.
5. The ADC of claim 4, wherein the sampling switch S1 is used for controlling whether to Sample the input signal, and when the Sample signal is high, S1 is turned on; when the Sample signal is low, S1 is turned off.
6. The ADC of claim 5, wherein the reset switch S2 is used for controlling whether to reset the holding voltage VP of the DAC to 0, and when the Rst signal is high, S2 is turned on; when the Rst signal is low, S2 is off.
7. The analog-to-digital converter according to claim 6, characterized in that it further comprises a voltage buffer unit Buf.
8. The analog-to-digital converter according to claim 7, wherein the Buf input terminal is connected to the upper plate VH of the DAC capacitor array, and the output terminal is connected to the inverting input terminal of the comparator Comp; buf is used for following the buffering with voltage signal VP that DAC kept, and output signal VH connects Comp's inverting input end for the influence of the kickback noise of isolated comparator to keeping signal VP.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113949385A (en) * | 2021-12-21 | 2022-01-18 | 之江实验室 | Analog-to-digital conversion circuit for RRAM storage and calculation integrated chip complement quantization |
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| CN104079298A (en) * | 2014-06-24 | 2014-10-01 | 复旦大学 | Successive approximation type analog-to-digital converter of self-calibration bridge-connection capacitor structure |
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