KR102336896B1 - Analog-to-digital conversion device and image sensing device and method thereof - Google Patents

Abstract

According to an embodiment of the present invention, an analog-to-digital conversion device capable of realizing high-speed operation performance by first converting an MSB code based on a reference voltage corresponding to half of the entire ADC conversion range, and performing LSB conversion based on the same comprises: a comparator which receives a pixel signal through one terminal, receives a ramp signal applied from a ramp signal generating device through the other terminal, compares values of the two signals according to a control signal of a control unit, and outputs a comparison signal; the control unit which determines the MSB code according to the size of the pixel signal based on the reference voltage corresponding to a preset size among the entire A/D conversion range, and determines a start point of an LSB conversion operation according to the determined MSB code; and a counting unit which outputs counting information by counting a clock from the control unit from the time when the ramp signal falls until the time when the comparison signal is inverted.

Description

Analog-to-digital conversion device and image sensing device and method including same

The present invention relates to an analog-to-digital conversion apparatus and an image sensing apparatus and method including the same, and more particularly, to first determine an MSB code based on a reference voltage corresponding to a preset size among the entire ADC conversion range, and based on the The present invention relates to an analog-to-digital conversion device and an image sensor capable of realizing high-speed operation performance by performing low LSB conversion.

In general, CMOS image sensors (CIS) implemented in a CMOS process rapidly expand the market due to the advantages of low power consumption, low price, and small size compared to other competitive products (eg, solid-state imaging devices). is going In particular, the CMOS image sensor is gradually expanding its application range to the video field requiring high resolution and high frame rate through improved image quality, which was relatively insufficient compared to competing products.

At this time, unlike the solid-state image sensor, the CMOS image sensor needs to convert an analog signal (pixel signal) output from the pixel array into a digital signal. A high-resolution analog-to-digital converter (ADC: Analog to Digital Converter) is used.

Such CMOS image sensors can be classified into a method using a single analog-to-digital converter (Single ADC) and a method using a column analog-to-digital converter (Column ADC) according to an implementation method of the analog-to-digital converter.

The single analog-to-digital conversion method converts analog signals output from the pixel arrays of all columns into digital signals within a predetermined time using one analog-to-digital conversion device operating at high speed. Although there is an advantage of reducing the chip area, there is a disadvantage of large power consumption because the analog-to-digital converter must operate at high speed.

In contrast, the column analog-to-digital conversion method is a method in which an analog-to-digital conversion device (for example, a single-slop analog-to-digital conversion device) of a simple structure is arranged in each column, and the chip area of the CMOS image sensor is reduced. Although there is an increased disadvantage, since each analog-to-digital converter may operate at a low speed, there is an advantage in that power consumption is small.

The column analog-to-digital conversion method performs cross-correlation double sampling (CDS) on the analog output voltage, which is the output signal of the pixel array, and stores the resultant voltage, and also stores the resulting voltage in the ramp signal generated by the ramp signal generator. In response, a comparison signal for digital code generation is provided by comparing the stored voltage to a predetermined ramp signal in a cross-correlation double sampling operation.

In this case, it is important to improve the analog-to-digital conversion (ADC) characteristics in order for the CMOS image sensor to operate at high speed while implementing high resolution. However, in the conventional analog-to-digital conversion method (eg, single-slop analog-to-digital conversion device), the counter operation clock must be increased by a multiple of 2 in order to improve the resolution by 1 bit. Without a special method to reduce the number of operating clocks, it is difficult to realize high resolution, and it takes a lot of time to convert data to analog-to-digital, so it is difficult to implement at high speed, and accordingly, power consumption increases.

In an embodiment of the present invention, based on a reference voltage corresponding to a preset size among the entire ADC conversion range, the MSB code is determined according to the size of the pixel signal, and then the start point of the LSB conversion operation is determined according to the determined MSB code, An analog-to-digital converter and image sensor capable of high-speed operation at high resolution are provided.

An analog-to-digital conversion apparatus according to an embodiment of the present invention receives a pixel signal through one terminal, receives a ramp signal applied from a ramp signal generator through the other terminal, and converts the values of the two signals according to a control signal of a control unit. A comparator that compares and outputs a comparison signal, determines the MSB code according to the size of the pixel signal based on a reference voltage corresponding to a preset size among the entire A/D conversion range, and then starts the LSB conversion operation according to the determined MSB code and a control unit for determining , and a counting unit for outputting counting information by counting the clock from the control unit from the time when the ramp signal falls until the comparison signal is inverted.

The analog-to-digital conversion device according to an embodiment of the present invention is turned on when the pixel signal is less than the reference voltage, and sets the voltage of the non-inverting terminal of the comparator to the lower voltage of the entire A/D conversion range. It further includes a switch unit.

The analog-to-digital conversion device according to an embodiment of the present invention is turned off when the pixel signal is greater than the reference voltage, and sets the voltage of the non-inverting terminal of the comparator as a reference voltage among the entire A/D conversion range. It further includes a switch unit.

The analog-to-digital conversion apparatus according to an embodiment of the present invention further includes an error correction performing unit configured to correct an error by extending a ramping range of the ramp signal when a stabilization error of a ramp slope occurs during the MSB code conversion.

In the analog-to-digital conversion apparatus according to an embodiment of the present invention, when the pixel signal is greater than the reference voltage, the MSB code is determined to be '0', and the starting point of the LSB conversion operation is set as the starting point of the entire A/D conversion range. Set to the upper voltage.

In the analog-to-digital conversion apparatus according to an embodiment of the present invention, when the pixel signal is smaller than the reference voltage, the MSB code is determined as '1', and the starting point of the LSB conversion operation is the entire A/D conversion range. set to the lower voltage of

The analog-to-digital conversion apparatus and the image sensor according to an embodiment of the present invention determine the MSB code according to the size of the pixel signal based on the median value of the entire A/D conversion range, and then perform the LSB conversion operation according to the determined MSB code. By determining the starting point, there is an effect that it can operate at high resolution and high speed without increasing the clock of the counter.

The single-slop analog-to-digital conversion device and image sensor according to an embodiment of the present invention can be designed simply by having a CM switch in the structure of the existing analog-to-digital conversion device, so only a few switches and logic in the existing analog-to-digital converter It can be implemented by adding it, and if necessary, it can be easily returned to the original analog-to-digital conversion structure, so it has an effect that can be applied to various types of commercial application image sensors.

In addition, the single-slop analog-to-digital conversion apparatus and the image sensor according to an embodiment of the present invention have the effect of more effectively correcting the nonlinearity error than the conventional analog-to-digital conversion apparatus.

1 is a diagram for explaining the structure of a conventional single-slop analog-to-digital conversion device.
FIG. 2 is a timing diagram for explaining the operation of the conventional single-slop analog-to-digital converter of FIG. 1 .
3 is a diagram for explaining the structure of a single-slop analog-to-digital conversion apparatus according to an embodiment of the present invention.
4 is a timing diagram for explaining the operation of the proposed single-slop analog-to-digital conversion apparatus according to an embodiment of the present invention.
5 is a timing diagram for explaining the operation of the proposed single-slop analog-to-digital conversion apparatus according to another embodiment of the present invention.
6 is a diagram for explaining error correction of a proposed single-slop analog-to-digital conversion apparatus according to an embodiment of the present invention.
7 is a diagram for explaining error correction of a proposed single-slop analog-to-digital conversion apparatus according to another embodiment of the present invention.
8 is a diagram for describing two types of resetting a non-inverting node when a pixel signal is greater than a ramp signal according to an embodiment of the present invention.
9 is a diagram for describing two types of resetting a non-inverting node when a pixel signal is smaller than a ramp signal according to an embodiment of the present invention.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numbers regardless of reference numerals, and redundant description thereof will be omitted.

In the description of the embodiments disclosed herein, when a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but It should be understood that other components may exist in between.

In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in this specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical idea disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

1 is a diagram for explaining the structure of a conventional single-slop analog-to-digital conversion device.

Referring to FIG. 1 , a conventional single-slop analog-to-digital conversion device (analog-to-digital conversion device) includes a pixel array 10 for outputting a pixel signal corresponding to incident light, and for generating a ramp signal under the control of the controller. The ramp signal generating device 20 and the comparing unit 30 for comparing the value of the ramp signal applied from the ramp signal generating device 20 with the value of each pixel signal output from the pixel array 10 under the control of the controller , according to the control of the control unit, it may include a memory unit for respectively storing the counting information from the counting unit (40).

In general, CMOS image sensors compare the pixel signals (pixel output voltage) before and after the optical signal is incident in order to remove the offset value of the pixel itself so that only the pixel signal due to the incident light can be actually measured. This technique is called cross-correlation double sampling (CDS). This cross-correlation double sampling operation is performed by the comparator 30 .

The comparator 30 includes a plurality of comparators, the counting unit 40 includes a plurality of counters, and the memory unit includes a plurality of memories. That is, a comparator, a counter, and a memory are provided for each column. Operations of one comparator, counter, and memory will be described with reference to FIG. 2 .

FIG. 2 is a timing diagram for explaining the operation of the conventional single-slop analog-to-digital converter of FIG. 1 .

Referring to FIG. 2 , the comparator 30 receives a pixel signal output from one column of the pixel array through one terminal, and receives a ramp signal applied from the ramp signal generating device 20 through the other terminal, and receives control from the control unit. A comparison signal is output by comparing the values of the two signals according to the signal.

Since the ramp signal (VRAMP=VVINP) is a signal in which the voltage level decreases or increases at a constant level as time elapses after the start of initialization, a point in time at which the values of the two signals input to each comparator 30 coincide occurs. do. As the coincident timing passes, the value of the comparison signal output from each comparator 30 is inverted.

Accordingly, the counter counts the clock from the controller from the time when the ramp signal falls (tR0, tSO) to the moment when the comparison signal output from the comparator is inverted (tRST, tSIG) and outputs counting information. Here, each counter is initialized according to a reset control signal from the control unit.

Then, the memory stores the counting information from the counting unit 40 according to the load control signal from the control unit and outputs it to the column readout circuit.

However, since the analog-to-digital conversion method as described above has to increase the counter operation clock by multiples of 2 to improve the resolution by 1 bit, there is no special method to reduce the number of operation clocks of the counter required to improve the resolution. Not only is it difficult to implement in high resolution, but it also takes a lot of time to convert data to analog-to-digital, which makes it difficult to implement at high speed, and accordingly, power consumption increases.

Therefore, the analog-to-digital conversion apparatus according to an embodiment of the present invention determines the MSB code according to the size of the pixel signal based on the reference voltage corresponding to the preset size among the entire A/D conversion range, and then adds the MSB code to the determined MSB code. Accordingly, by determining the start point of the LSB conversion operation, it is possible to operate at a high resolution and at high speed without increasing the clock of the counter and to reduce power consumption.

3 is a diagram for explaining the structure of an analog-to-digital conversion apparatus according to an embodiment of the present invention.

Referring to FIG. 3 , an analog-to-digital conversion apparatus according to an embodiment of the present invention includes a plurality of sampling capacitors 51 , 52 , 53 , two comparators 61 and 62 , and a plurality of switches 71 , 72 and 73 . ), a counting unit 41 , and a control unit 80 .

In an embodiment, the analog-to-digital conversion device receives a pixel signal through one terminal, receives a ramp signal applied from the ramp signal generator through the other terminal, and compares the values of the two signals according to the control signal of the controller 80 . The comparator 61 for outputting a comparison signal to determine the MSB code according to the size of the pixel signal based on a preset reference voltage among the entire A/D conversion range, and then to determine the starting point of the LSB conversion operation according to the determined MSB code The control unit 80 and the counting unit 41 for outputting counting information by counting the clock from the control unit 80 from the time when the ramp signal falls until the comparison signal is inverted may include.

For example, the reference voltage may be a voltage corresponding to half of the entire A/D conversion range. This means that during A/D conversion, the size of the MSB step corresponds to half of the entire conversion range. In this case, MSB code conversion is first performed depending on whether the pixel signal belongs to the upper or lower portion with respect to the reference voltage, and thereafter, the LSB code conversion is sequentially performed for the MSB step section including the pixel signal.

During the MSB code conversion operation (PMSB), the analog-to-digital conversion of the MSB code conversion may be performed by a value obtained by dividing the total number of steps by the size of the MSB step. That is, when the total number of steps is constant, the number of A/D operations of MSB code conversion decreases as the MSB step is set larger, and the number of A/D operations of MSB code conversion increases as the MSB step is set smaller.

The controller 80 may adjust the size of the MSB step and the reference voltage according to a preset algorithm. The reference voltage may be variously set according to an embodiment, and may not necessarily be set to half of the entire A/D conversion range. The reference voltage may be variously set in consideration of the performance, operating environment, applied application, counter information, etc. of the analog-to-digital conversion device.

Since the analog-to-digital conversion apparatus according to an embodiment of the present invention can be configured by adding only the CM switch 71 to the conventional ADC, it has a structural advantage of being reversible compared to the conventional analog-to-digital conversion apparatus.

The CM switch 71 may be turned on when the pixel signal is smaller than the reference voltage, and may set the voltage of the non-inverting terminal of the comparator as the lower voltage of the entire A/D conversion range. Alternatively, if the pixel signal is greater than the reference voltage, it may be turned off, and the voltage of the non-inverting terminal of the comparator may be set as the reference voltage in the entire A/D conversion range.

The analog-to-digital conversion may consist of a first conversion of the MSB code conversion and a second conversion of the LSB code. The purpose of the first conversion is to reduce the resources of the entire ADC and improve the conversion speed of the analog-to-digital conversion device as a result by applying a binary weight search algorithm to the first conversion to determine a preset range among the entire conversion range in advance. .

Taking the case where the preset range is half of the full conversion range, based on half of the full A/D conversion range in the first conversion, the MSB code is first converted according to the size of the pixel signal (upper section: MSB = ' 0', subsection: MSB = '1'), LSB code conversion can be performed by dividing into two subsections.

Since analog-to-digital conversion is performed only on the remaining least significant bits (LSB) in the selected subsection according to the result of the MSB conversion thereafter, the actual conversion step for obtaining the MSB code is effectively reduced compared to the conventional single-slop analog-to-digital conversion method can be

4 is a timing diagram for explaining the operation of the analog-to-digital conversion device of the present invention. 5 is a timing diagram for explaining the operation of the proposed analog-to-digital conversion apparatus according to another embodiment of the present invention.

4 and 5 show the waveform of the analog-to-digital conversion device according to the embodiment of the present invention divided into two cases according to the position of the pixel signal. It is assumed that the common level of VINP and VRAMP is the same as in the ideal design, and conversion is performed through four stages of PMSB, PCM, PRZ and PLSB during the A/D conversion period. Specifically, the ramp signal generator performs MSB code conversion in PMSB, PCM, and PRZ and LSB code conversion in PLSB.

The conversion may be started by comparing the reference voltage VCM corresponding to a preset size among the entire conversion range and the pixel signal VINN=VSIG. During MSB code conversion (PMSB), ramp signal VRAMP is reduced from upper voltage VREFP to reference voltage VCM, and AC-coupled with non-inverting signal VINP. Accordingly, the MSB code conversion can be described as a result of comparing the non-inverted signal VINP and the inverted signal VINN.

According to the result of comparing the non-inverted signal (VINP) and the inverted signal (VINN), the MSB code determination and LSB code conversion can be performed by dividing into 1) VINP less than VINN and 2) VINP greater than VINN. can

First, a case in which VINP is smaller than VINN will be described with reference to the timing diagram of FIG. 4 .

Referring to FIG. 4 , when VINP < VINN, the final output (VCO) of the comparator is changed to logic high, and the conversion result (DMSB) of '0' is stored in 1-bit memory. After that, the RZ switch ΦRZ is activated (PRZ), and the ramp signal VRAMP returns to the upper voltage VRFEP so that VINP = VRFEP.

When the LSB switch ΦLSB is activated (PLSB), in the same way as the conventional analog-to-digital converter algorithm, A/D conversion is performed together with the LSB step to obtain the remaining bits of the upper section (VINP=VREFP-VRAMP_U) . The range of VRAMP_U may be from the upper voltage VREFP of the entire reference scale to the reference voltage VCM. The conversion result (DLSB) is stored in the latch of the (N-1) bit local counter. Full digital code (DFULL) can be obtained by merging DMSB with DLSB according to weight.

Referring to FIG. 5 , when VINP > VINN, the conversion result DMSB of '1' may be stored in a 1-bit memory and the CM switch ΦCM may be turned on (PCM). Thereafter, the node of the non-inverting signal VINP is reset to the lower voltage VREFN of the full reference.

During the period in which the RZ switch ΦRZ is activated PRZ, the non-inverting signal VINP becomes the full-scale reference voltage VCM while the ramp signal VRAMP returns to the upper voltage VRFEP. When the LSB switch (ΦLSB) is activated (PLSB), A/D conversion is performed in the subsection (VINP = VCM-dVRAMP_L). At this time, the range of VRAMP_L is from VCM to VREFN of the full reference.

Since the analog-to-digital conversion device according to an embodiment of the present invention can be designed with a CM switch in the existing analog-to-digital conversion device, it can be implemented by adding only a few switches and logic to the existing analog-to-digital conversion device, If necessary, it can be easily returned to the original analog-to-digital conversion device structure, so it can be applied to various types of commercial application image sensors.

In addition, in the analog-to-digital conversion apparatus according to an embodiment of the present invention, since the number of bits that can be reduced increases as the resolution required of the analog-to-digital conversion apparatus increases, it has an advantage that it can be effectively applied to a high-performance CIS.

In addition, since the analog-to-digital conversion apparatus according to an embodiment of the present invention operates only in two cases having an upper section and a lower section in the entire conversion range, error correction for nonlinearity is more effectively performed than other conventional analog-to-digital conversion apparatuses can do. Hereinafter, error correction for nonlinearity will be described in more detail with reference to FIGS. 6 and 7 .

6 is a diagram for explaining error correction of an analog-to-digital conversion apparatus according to an embodiment of the present invention. To this end, when a stabilization error of the ramp slope occurs during MSB code conversion, the controller may further include an error correction performing unit that corrects the error by extending the ramping range of the ramp signal.

The CM switch of the non-inverting node (VINP) may cause a difference in ramp slope between the top and bottom of the overall conversion during PLSB, but it does not affect the linearity of the analog-to-digital conversion and can be considered an offset error.

In contrast, the main cause of nonlinearity in analog-to-digital conversion according to an embodiment of the present invention can be explained as a setting error of the ramp slope during MSB code conversion (PMSB).

6 and 7 show two cases in which the waveforms of the 4-bit analog-to-digital conversion device are different. 6 and 7, as shown by a black line, it can be assumed that a stabilization error occurs because VINP cannot be accurately controlled as much as VCM.

In the case of FIG. 6 , although VINN is originally larger than VCM, VINP does not reach VCM, so the result (DMSB) of MSB code conversion is obtained as '1'. Therefore, since the result of MSB code conversion is '1', LSB code conversion is performed at the lower end of the entire range. In this case, since there is no zero crossing, which is the basis for counting, the LSB code conversion results in '0000'.

In order to solve this problem, the present invention extends the ramping range of VRAMP to cover the range of VCM like the blue line. If the ramping range is extended, the result of LSB code conversion appears as '1110'. As a result, the error-correcting 4-bit full code merges the results of MSB code conversion (DMSB = '1000') and LSB code conversion (DLSMB = '1110') according to the code weight to obtain a full code (DFULL = '0110'). can be obtained

7 is a diagram for explaining error correction of an analog-to-digital conversion apparatus according to another embodiment of the present invention.

In the case of FIG. 7, VINN is smaller than VCM, but the result (DMSB) of MSB code conversion is obtained as '0' as shown by the black line. In this case, LSB code conversion is performed in the upper section to get DLSB = '0111'.

VCM 범위를 커버하도록 확장될 수 있다. 결과적으로 LSB 코드 변환의 결과는 '1010'으로 얻어지며, 코드 가중치에 따라 MSB 코드 변환(DMSB = '0000') 및 LSB 코드 변환(DLSMB = '1010')의 결과를 병합하여 DFULL = '1010'의 4 비트 풀 코드를 얻을 수 있다.In an embodiment, in order to correct the error of the digital code, the ramping range of VRAMP is set as shown in the blue line as shown in FIG. 7 .

It can be extended to cover the VCM range. As a result, the result of LSB code conversion is obtained as '1010', and by merging the results of MSB code conversion (DMSB = '0000') and LSB code conversion (DLSMB = '1010') according to the code weight, DFULL = '1010' You can get the 4-bit full code of

Error correction of analog-to-digital conversion according to an embodiment of the present invention is performed by extending the ramping range of VCM to VCMR+ or VCMR-. In this design, steps for error correction can be inserted into the PLSB.

According to the software implementation, each component as well as the procedures and functions described in this specification may be implemented as a separate software module. Each of the software modules may perform one or more functions and operations described herein. The software code may be implemented as a software application written in a suitable programming language. The software code may be stored in a memory and executed by a controller or a processor.

8 is a diagram for describing two types of resetting a non-inverting node when a pixel signal is greater than a ramp signal according to an embodiment of the present invention.

In the first type (Type-1), the analog-to-digital conversion device of the present invention uses the CM switch of FIG. 3 to convert the voltage of the non-inverting node VINP to the upper voltage VREFP during the CM switch operation (PCM). can be set to

Alternatively, in the second type (Type-2), the analog-to-digital conversion device of the present invention may set the voltage of the non-inverting node VINP to the upper voltage VREFP without using the CM switch.

In the case of the first type (Type-1) in Fig. 8, the non-inverting node (VINP) is reset to the upper voltage (VREFP) through the CM switch (ΦCM), and in this process (PCM) the noise (kT/C) is can occur. In this case, since the noise is not sufficiently removed by the double CDS operation, a desired screen image cannot be obtained.

Therefore, in the analog-to-digital conversion apparatus according to an embodiment of the present invention, if the pixel signal is greater than the ramp signal, the voltage value of the non-inverting terminal VINP is constantly maintained without using the CM switch, and then set to the upper voltage. method can be used (Type-2).

9 is a diagram for describing two types of resetting a non-inverting node when a pixel signal is smaller than a ramp signal according to an embodiment of the present invention.

In the first type (Type-1), the analog-to-digital conversion device of the present invention can set the voltage of the non-inverting node VINP to the lower voltage VREFN without using a CM switch.

Alternatively, in the second type (Type-2), the analog-to-digital conversion device of the present invention uses the CM switch of FIG. 3 to convert the voltage of the non-inverting node VINP to the lower voltage ( VREFN).

In the case of the second type (Type-2) of FIG. 9 , the non-inverting node VINP is reset to the lower voltage VREFN through the CM switch ΦCM. In this process, photon shot noise may be generated as a main noise source, but it may provide improved noise performance than the allowable noise range of the conventional analog-to-digital converter.

Accordingly, when the pixel signal is smaller than the ramp signal, analog-to-digital conversion may be performed according to the second type (Type-2) operation in consideration of noise performance of the analog-to-digital conversion device.

In conclusion, the non-inverting node VINP is reset to the upper voltage VREFP according to Type-1 when the pixel signal is greater than the ramp signal, and type-2 when the pixel signal is smaller than the ramp signal. According to (Type-2), the non-inverting node VINP may be reset to the lower voltage VREFN. However, depending on the embodiment, both types may be used in each case of FIGS. 8 and 9 in consideration of ADC performance, and the embodiment is not limited thereto.

Embodiments of the present invention published in the present specification and drawings are merely provided for specific examples to easily explain the technical content of the present invention and help the understanding of the present invention, and are not intended to limit the scope of the present invention. It will be apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention may be implemented in addition to the embodiments disclosed herein.

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10: pixel array
20: ramp signal generator
30: comparison unit
40: counting unit
51, 52, 53: sampling capacitor
61, 62: comparator
71, 72, 73: switch
80: control unit

Claims (8)

a comparator that receives a pixel signal through one terminal, receives a ramp signal applied from a ramp signal generator through the other terminal, compares values of the two signals according to a control signal of a control unit, and outputs a comparison signal;
a control unit that determines an MSB code according to the size of a pixel signal based on a reference voltage corresponding to a preset size among the entire A/D conversion range, and determines a start point of an LSB conversion operation according to the determined MSB code; and
A counting unit for outputting counting information by counting the clock from the control unit from the time when the ramp signal falls until the comparison signal is inverted;
the control unit
An analog-to-digital conversion apparatus for adjusting the size of an MSB step according to a preset algorithm and performing the MSB code conversion operation by a value obtained by dividing the total number of steps by the size of the MSB step during the MSB code conversion operation.
According to claim 1,
A CM switch unit which is turned on when the pixel signal is smaller than the reference voltage and sets the voltage of the non-inverting terminal of the comparator to a lower voltage (V _{REFN ), which is the lowest value among the entire A/D conversion range;}
The CM switch unit is disposed between a capacitor disposed between the ramp signal generator and a non-inverting terminal of the comparator and a non-inverting terminal of the comparator.
According to claim 2, wherein the control unit,
When the pixel signal is smaller than the reference voltage, the MSB code is determined as '1', and a starting point of the LSB conversion operation is set as a reference voltage of the entire A/D conversion range.
According to claim 1,
a CM switch unit which is turned off when the pixel signal is greater than the reference voltage, and sets the voltage of the non-inverting terminal of the comparator to the reference voltage in the entire A/D conversion range;
The CM switch unit is disposed between a capacitor disposed between the ramp signal generator and a non-inverting terminal of the comparator and a non-inverting terminal of the comparator.
According to claim 4, wherein the control unit,
When the pixel signal is greater than the reference voltage, the MSB code is determined as '0', and the starting point of the LSB conversion operation is set to the _{upper voltage (V REFP ), which is the highest value among the entire A/D conversion range.} digital conversion device.
According to claim 1, wherein the control unit,
and an error correction performing unit for correcting the error by extending the ramping range so that the ramping range of the ramp signal covers the range of the reference voltage when a stabilization error of the ramp slope occurs during MSB code conversion; .
According to claim 1,
Further comprising a memory unit for storing the counting information received from the counting unit,
The memory unit includes a physically or logically separated storage area for storing the 1-bit MSB code.
According to claim 1, wherein the control unit,
An analog-to-digital converter for setting the size of the MSB step and the reference voltage according to the algorithm in consideration of at least one of performance, operating environment, applied application, and counter information of the analog-to-digital converter.

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