CN110535466A - A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus - Google Patents
A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus Download PDFInfo
- Publication number
- CN110535466A CN110535466A CN201910790646.7A CN201910790646A CN110535466A CN 110535466 A CN110535466 A CN 110535466A CN 201910790646 A CN201910790646 A CN 201910790646A CN 110535466 A CN110535466 A CN 110535466A
- Authority
- CN
- China
- Prior art keywords
- analog converter
- msb
- type digital
- surplus
- digital analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The present invention discloses a kind of over-sampling SAR ADC read based on noise shaping techniques and surplus, including FIR filter, the signal V sampled to pixelpix, by the transformation result signal V for the analog/digital A/D that high significance bit MSB type digital analog converter, low order LSB type digital analog converter exportDACIt makes the difference to obtain quantization error VR, then VPIX、VRWith VDACAccess comparator compares, and accesses Digital Logical Circuits later, completes surplus readout and is converted to digital code；Digital Logical Circuits is connect with register, accesses the MSB code D replicated in registerMSBWith read residual signal, after multiple repairing weld, the result of multiple repairing weld is finally reached into average logic circuit, obtains final output.The present invention realizes the raising of signal-to-noise ratio, so that SAR ADC improves effective resolution, reduces power consumption.
Description
Technical field
The present invention relates to image sensor technologies fields, are read more particularly to one kind based on noise shaping techniques and surplus
Over-sampling SAR ADC.
Background technique
With the steady-state growth to all kinds of personalization information technology device requirements such as smart phone, tablet computer, pass through society
Web Publishing is handed over to become all the fashion with personal picture is shared；Cmos image sensor (CMOS Image Sensor, CIS) is
Important component as Information Technology Equipment.Requirement due to people to picture quality is higher and higher, various low noises, speed
Degree high mode converter (Analog-Digital Converter, ADC) structure is used for CIS reading.
In order to realize the raising of ADC performance, there are many technical applications on ADC in recent years, is such as put using programmable-gain
Big device runs multiple ADC etc. parallel, but there is design the problems such as complicated, oversized, power consumption is excessively high for these schemes.It crosses and adopts
Sample technology is applied in the noise suppressed of ADC.Over-sampling is the intrinsic attribute of sigma-delta type ADC, and the formation of noise is special
Property be allowed to show preferable low-noise performance, but 1 quantizer inhibit quantizing noise needed for high over sampling ratio, this limitation
Conversion speed；On the other hand, Nyquist ADC (such as successive approximation register ADC and flowing water are improved using oversampling technique
Line ADC) the performances such as dynamic range, signal-to-noise ratio, can also realize over-sampling using the characteristic of these ADC high speeds, but its noise is whole
Shape ability lacks, and is not able to satisfy the demand of high s/n ratio Signal to Noise Ratio, SNR.
Summary of the invention
In view of the technical drawbacks of the prior art, it is an object of the present invention to provide one kind to be based on noise shaping techniques
The over-sampling SAR ADC read with surplus.
The technical solution adopted to achieve the purpose of the present invention is:
A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus, including with noise shaping function
FIR filter, the comparator connecting with FIR filter, high significance bit MSB type digital analog converter, low order LSB type digital-to-analogue turn
Parallel operation, Digital Logical Circuits, the register being connect with Digital Logical Circuits, the average logic circuit being connect with register, number
Word logic circuit and high significance bit MSB type digital analog converter, low order LSB type digital analog converter；
FIR filter, the signal V that pixel is sampledpix, and by high significance bit MSB type digital analog converter, it is low effectively
The transformation result signal V of the analog/digital A/D of position LSB type digital analog converter outputDACIt makes the difference to obtain quantization error VR, then
VPIX、VRWith VDACAccess comparator compares, and accesses Digital Logical Circuits later, completes surplus readout and is converted to digital generation
Code；Digital Logical Circuits is connect with register, accesses the MSB code D replicated in registerMSBWith reading residual signal, repeatedly adopt
After sample, the result of multiple repairing weld is finally reached into average logic circuit, obtains final output.
Wherein, high significance bit MSB type digital analog converter, low order LSB type digital analog converter are separately connected control signal,
It is worked with controlling the A/D converter of high significance bit MSB type digital analog converter, low order LSB type digital analog converter in MSB mode
Or LSB mode.
Wherein, FIR filter is twin-stage FIR filter.
The present invention is based on the over-sampling SAR ADC that noise shaping techniques and surplus are read, using with noise shaping ability
SAR ADC framework realize the raising of signal-to-noise ratio compared with conventional successive approach type ADC.The present invention is that have to make an uproar
Sound shaping and surplus read the energy-saving low-noise CIS of SAR ADC, using passive finite impulse response (FIR) (Finite
Impulse Response, FIR) filter progress noise shaping, so that SAR ADC improves effective resolution；Using surplus
Readout scheme reduces power consumption.Compared with traditional SAR ADC, structure proposed by the present invention can be effectively reduced noise.
Detailed description of the invention
Fig. 1 is the over-sampling SAR ADC structure chart of the invention read based on noise shaping techniques and surplus；
Fig. 2 is the working principle diagram that noise shaping and surplus are read to the SAR ADC combined.
Fig. 3 is the structure of twin-stage FIR filter in ADC proposed by the present invention.
Specific embodiment
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.It should be appreciated that described herein
Specific embodiment be only used to explain the present invention, be not intended to limit the present invention.
As shown in Figure 1, the present invention is based on the over-sampling SAR ADC that noise shaping techniques and surplus are read, comprising: FIR filter
Wave device 103, comparator 104, high significance bit MSB type digital analog converter 107, low order LSB type digital analog converter 108, number
Logic circuit 105, register 106, average logic circuit 111,101 are the signal V that pixel is sampledpix, 102 be simulation/number
The transformation result V of word A/DDAC, in high significance bit MSB type digital analog converter 107, low order LSB type digital analog converter 108
It generates, signal makes the difference to obtain quantization error V by FIR filter 103R, which can realize noise shaping function simultaneously.VPIX、
VRWith VDACAll access comparators 104 are compared, and access Approach by inchmeal Digital Logical Circuits 105, and signal completes surplus reading herein
Process out, and digital code is converted to, it is connected with register 106, replicates MSB code DMSB, can skip in noise coupling
MSB decision process；Digital Logical Circuits 105 and high significance bit MSB type digital analog converter 107, low order LSB type digital-to-analogue conversion
Device 108 connects, the D that will be replicated in register 106MSBIt is accessed with residual signal is read, 109,110 be control signal, and control height has
Imitate the A/D converter work of position MSB type digital analog converter 107, low order LSB type digital analog converter 108 in MSB mode or
LSB mode.Sample frequency is OSR times of nyquist frequency, and above sampling process is also repeated OSR times, finally will repeatedly be adopted
The result of sample reaches average logic circuit 111, obtains final output.
Fig. 2 illustrates the working principle that noise shaping and surplus are read to the SAR ADC combined.VPIX[i,j]With
VPIX[i,j+1]The picture element signal of respectively total pixel array the i-th row jth column and (j+1) column.During over-sampling, A/D conversion is carried out
Input pixel value be fixed VPIX[i,j], this process can carry out quantizing noise coupling to signal and be mentioned with realizing noise shaping
High SNR；Constant input VPIX[i,j]Whole digital codes can by the LSB of low level convert realize.Over-sampling is completed, reading movement
To a new pixel VPIX[i,j+1], replicate the D of surplus readout schemeMSBs[i,j], can skip the decision of MSB, obtain complete generation
Code.
Using twin-stage FIR filter, the low frequency quantization noise and comparator noise of SAR ADC can be reduced.Fig. 3 gives
The schematic diagram of the twin-stage FIR filter proposed, 301,302 be filter capacity CFIR1、CFIR2；303~312 be switch.
If using two-tap FIR filter to low-pass filter, NTF be may be calculated
Q (z) is the quantization error of A/D conversion.α1And α2It is the decaying generated in FIR filter quantization error sampling process
The factor.The m times sampling indicates that the noise coupling work of twin-stage FIR filter is as follows with Conv [m]: when Conv [m-1], other
Switch is opened, and 305,307 closures reset CFIR1, 305,306 are then turned on, is closed 303,304, remaining difference VR[m-1]In CFIR1On adopt
Sample.When Conv [m], other switches are opened, 311,312 closures, VR[m-1]With C when Conv [m-2]FIR2The remaining difference V sampledR[m-2]
It is connected to comparator input terminal, remaining potential difference is coupled on current pixel voltage, obtains VPIX+VR[m-1]+VR[m-2]。Conv[m]
Afterwards, 306,308 closure resets CFIR2, open other switches, closure 309,310, new remaining difference VR[m]It is up-sampled in CFIR2, this
C in the processFIR1Remaining difference V before upper holdingR[m-1], to carry out next secondary coupling.
The present invention carries out over-sampling to the input signal of SAR ADC using the rate for being significantly larger than nyquist frequency, can
SNR and resolution ratio are improved, while the requirement of frequency overlapped-resistable filter can also be reduced, simplifies ADC structure；Using FIR filter, to defeated
The signal entered carries out noise shaping, can inhibit the low frequency component of quantization error, improves signal-to-noise ratio；It is constant defeated during over-sampling
The analog-to-digital conversion entered only needs several LSB conversions it is achieved that MSB Switching Power Supply therefore can be saved.After the completion of sampling, need
Complete code is read, applies surplus readout scheme at this time, replicates MSB code, still has very maximum probability to skip determining for MSB
Plan；At this point, the design cycle substantially reduces, reading speed is accelerated.
The above is only a preferred embodiment of the present invention, it is noted that for the common skill of the art
For art personnel, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications
Also it should be regarded as protection scope of the present invention.
Claims (3)
1. a kind of over-sampling SAR ADC read based on noise shaping techniques and surplus, which is characterized in that including whole with noise
The FIR filter of shape function, the comparator being connect with FIR filter, high significance bit MSB type digital analog converter, low order LSB
Type digital analog converter, Digital Logical Circuits, the register being connect with Digital Logical Circuits, the average logic being connect with register
Circuit, Digital Logical Circuits and high significance bit MSB type digital analog converter, low order LSB type digital analog converter；
FIR filter, the signal V that pixel is sampledPix,And by high significance bit MSB type digital analog converter, low order LSB
The transformation result signal V of the analog/digital A/D of type digital analog converter outputDACIt makes the difference to obtain quantization error VR,Then VPIX、VRWith
VDACAccess comparator compares, and accesses Digital Logical Circuits later, completes surplus readout and is converted to digital code；Number
Logic circuit is connect with register, accesses the MSB code D replicated in registerMSBWith read residual signal, after multiple repairing weld, most
The result of multiple repairing weld is reached into average logic circuit afterwards, obtains final output.
2. the over-sampling SAR ADC read according to claim 1 based on noise shaping techniques and surplus, which is characterized in that
High significance bit MSB type digital analog converter, low order LSB type digital analog converter are separately connected control signal, high effectively with control
The A/D converter work of position MSB type digital analog converter, low order LSB type digital analog converter is in MSB mode or LSB mode.
3. the over-sampling SAR ADC read according to claim 1 based on noise shaping techniques and surplus, which is characterized in that
FIR filter is twin-stage FIR filter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910790646.7A CN110535466A (en) | 2019-08-26 | 2019-08-26 | A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910790646.7A CN110535466A (en) | 2019-08-26 | 2019-08-26 | A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110535466A true CN110535466A (en) | 2019-12-03 |
Family
ID=68664220
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910790646.7A Pending CN110535466A (en) | 2019-08-26 | 2019-08-26 | A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110535466A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900988A (en) * | 2020-07-28 | 2020-11-06 | 电子科技大学 | Combined type third-order noise shaping successive approximation type analog-to-digital converter |
| CN112713898A (en) * | 2020-12-21 | 2021-04-27 | 湖南国科微电子股份有限公司 | Noise shaping SAR ADC and SOC |
| CN115866428A (en) * | 2022-11-30 | 2023-03-28 | 天津大学 | Correlated multiple sampling readout circuit similar to sigma-delta |
| CN115866428B (en) * | 2022-11-30 | 2024-05-03 | 天津大学 | Correlated multiple sampling readout circuit similar to sigma-delta |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140091960A1 (en) * | 2012-09-29 | 2014-04-03 | Nicholas P. Cowley | Methods and arrangements for high-speed analog-to-digital conversion |
| US20140210653A1 (en) * | 2013-01-25 | 2014-07-31 | Technische Universiteit Eindhoven | Data-driven noise reduction technique for Analog to Digital Converters |
| CN109412597A (en) * | 2018-10-29 | 2019-03-01 | 清华大学深圳研究生院 | A kind of gradual approaching A/D converter and D conversion method of second-order noise shaping |
| CN109889199A (en) * | 2019-02-20 | 2019-06-14 | 哈尔滨工程大学 | A kind of Σ Δ type with chopped wave stabilizing and SAR type mixed type ADC |
-
2019
- 2019-08-26 CN CN201910790646.7A patent/CN110535466A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140091960A1 (en) * | 2012-09-29 | 2014-04-03 | Nicholas P. Cowley | Methods and arrangements for high-speed analog-to-digital conversion |
| US20140210653A1 (en) * | 2013-01-25 | 2014-07-31 | Technische Universiteit Eindhoven | Data-driven noise reduction technique for Analog to Digital Converters |
| CN109412597A (en) * | 2018-10-29 | 2019-03-01 | 清华大学深圳研究生院 | A kind of gradual approaching A/D converter and D conversion method of second-order noise shaping |
| CN109889199A (en) * | 2019-02-20 | 2019-06-14 | 哈尔滨工程大学 | A kind of Σ Δ type with chopped wave stabilizing and SAR type mixed type ADC |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900988A (en) * | 2020-07-28 | 2020-11-06 | 电子科技大学 | Combined type third-order noise shaping successive approximation type analog-to-digital converter |
| CN112713898A (en) * | 2020-12-21 | 2021-04-27 | 湖南国科微电子股份有限公司 | Noise shaping SAR ADC and SOC |
| CN112713898B (en) * | 2020-12-21 | 2022-12-09 | 湖南国科微电子股份有限公司 | Noise shaping SAR ADC and SOC |
| CN115866428A (en) * | 2022-11-30 | 2023-03-28 | 天津大学 | Correlated multiple sampling readout circuit similar to sigma-delta |
| CN115866428B (en) * | 2022-11-30 | 2024-05-03 | 天津大学 | Correlated multiple sampling readout circuit similar to sigma-delta |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105391451B (en) | Switching method when a kind of gradual approaching A/D converter and its analog-to-digital conversion | |
| CN107395206B (en) | Successive approximation type digital-to-analog converter with feedback advance setting and corresponding Delta-SigmaADC framework | |
| CN102045067B (en) | Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC | |
| CN105007079B (en) | The fully differential increment method of sampling of gradual approaching A/D converter | |
| CN103152049A (en) | Successive approximation register type ADC (analog-digital converter) | |
| CN109194333B (en) | Composite structure successive approximation analog-to-digital converter and quantization method thereof | |
| CN107493104A (en) | Successive approximation register analog-to-digital converter and analog-to-digital signal conversion method thereof | |
| CN105811986B (en) | A kind of Approach by inchmeal adc circuit of high-speed transitions | |
| CN109379082B (en) | Successive approximation analog-to-digital converter | |
| KR20190069634A (en) | Successive approximation register analog-digital converting apparatus and system, and cmos image sensor thereof | |
| CN110190854B (en) | Two-step SAR ADC-oriented shared reference voltage realization circuit and method | |
| CN110380730B (en) | Capacitor array switching method applied to low-voltage SAR ADC | |
| CN108631778A (en) | Gradually-appoximant analog-digital converter and conversion method | |
| CN110661530B (en) | Analog-to-digital converter and quantization method based on code word recombination | |
| CN110535466A (en) | A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus | |
| KR20190071536A (en) | Successive approximation register analog digital converter and operating method thereof | |
| CN111371457A (en) | Analog-to-digital converter and three-level switching method applied to SAR ADC | |
| CN101207384B (en) | Analog-to-digital converting system | |
| CN111934689B (en) | High-precision analog-to-digital converter and conversion method | |
| CN103427841B (en) | A kind of system and method improving row parallel single-slope ADC switching rate | |
| CN111641413A (en) | Capacitive array switching method of high-energy-efficiency SAR ADC | |
| Shaker et al. | A 6-bit 130-MS/s low-power tracking ADC in 90 nm CMOS | |
| CN215420236U (en) | Quantizer circuit for SAR ADC | |
| CN113676183B (en) | High-precision low-power-consumption SAR ADC based on two steps | |
| CN113922819A (en) | One-step two-bit successive approximation type analog-to-digital converter based on background calibration |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20230818 |