CN110535466A - A kind of over-sampling SAR ADC read based on noise shaping techniques and surplus - Google Patents

Abstract

The invention discloses an over-sampling SAR ADC based on noise shaping technology and margin readout, which includes an FIR filter, and the signal V _pix sampled by a pixel is composed of a high-significant bit MSB type digital-to-analog converter and a low-significant bit LSB type digital-to-analog converter. The analog/digital A/D conversion result signal V _DAC output by the digital-to-analog converter is differenced to obtain the quantization error V _R , and then V _PIX , _VR and V _DAC are connected to a comparator for comparison, and then connected to a digital logic circuit to complete the remainder Quantity readout process and converted into digital code; the digital logic circuit is connected to the register, and the MSB code D _MSB copied in the register is connected to the read margin signal. After multiple sampling, the result of multiple sampling is finally transmitted to the average value logic circuit to get the final output. The invention improves the signal-to-noise ratio, improves the effective resolution of the SAR ADC, and reduces power consumption.

Description

An Oversampling SAR ADC Based on Noise Shaping Technique and Margin Readout

technical field

The invention relates to the technical field of image sensors, in particular to an oversampling SAR ADC based on noise shaping technology and margin readout.

Background technique

With the steady growth of demand for various personalized information technology equipment such as smartphones and tablet computers, it has become very popular to publish and share personal pictures through social networks; CMOS Image Sensor (CMOS Image Sensor, CIS) has become An important part of. Due to people's higher and higher requirements on image quality, various low-noise, high-speed Analog-Digital Converter (Analog-Digital Converter, ADC) structures are used for CIS readout.

In order to improve the performance of ADCs, many technologies have been applied to ADCs in recent years, such as using programmable gain amplifiers and running multiple ADCs in parallel. However, these solutions have problems such as complex design, large size, and high power consumption. Oversampling technology has been applied in the noise suppression of ADC. Oversampling is an inherent attribute of Σ-Δ ADC, and its noise formation characteristics make it exhibit better low-noise performance, but the high oversampling ratio required by a 1-bit quantizer to suppress quantization noise limits the conversion speed; On the other hand, oversampling technology can be used to improve the dynamic range and signal-to-noise ratio of Nyquist ADCs (such as successive approximation register ADCs and pipeline ADCs). The lack of shaping capability cannot meet the requirements of high signal-to-noise ratio Signal to Noise Ratio, SNR.

Contents of the invention

The purpose of the present invention is to provide an over-sampling SAR ADC based on noise shaping technology and margin readout, aiming at the technical defects existing in the prior art.

The technical scheme adopted for realizing the purpose of the present invention is:

An oversampling SAR ADC based on noise shaping technology and margin readout, including an FIR filter with noise shaping function, a comparator connected with the FIR filter, a high significant bit MSB type digital-to-analog converter, a low significant bit LSB digital-to-analog converter, digital logic circuit, register connected to digital logic circuit, average number logic circuit connected to register, digital logic circuit and high significant bit MSB type digital-to-analog converter, low significant bit LSB type digital-to-analog converter ;

The FIR filter is used to make a difference between the signal _Vpix sampled by the pixel and the analog/digital A/D conversion result signal V _DAC output by the high-significant bit MSB type digital-to-analog converter and the low-significant bit LSB type digital-to-analog converter. Get the quantization error V _R , then V _PIX , _VR and V _DAC are connected to the comparator for comparison, and then connected to the digital logic circuit to complete the margin reading process and convert it into digital code; the digital logic circuit is connected to the register and connected to the register The MSB code D _MSB copied in and the readout margin signal are sampled multiple times, and finally the result of multiple sampling is transmitted to the average number logic circuit to obtain the final output.

Among them, the high significant bit MSB type digital-analog converter and the low significant bit LSB type digital-analog converter are respectively connected with control signals to control the A/C of the high significant bit MSB type digital-analog converter and the low significant bit LSB type digital-analog converter. D converter works in MSB mode or LSB mode.

Wherein, the FIR filter is a two-stage FIR filter.

The present invention is based on the oversampling SAR ADC of the noise shaping technology and margin readout, adopts the successive approximation ADC architecture with noise shaping ability, and realizes the improvement of the signal-to-noise ratio compared with the traditional successive approximation ADC. The present invention is an energy-saving and low-noise CIS with noise shaping and margin readout successive approximation ADC, adopts passive finite impulse response (Finite Impulse Response, FIR) filter to carry out noise shaping, makes SAR ADC improve effective resolution; Quantity readout scheme reduces power consumption. Compared with the traditional SAR ADC, the structure proposed by the invention can effectively reduce the noise.

Description of drawings

Fig. 1 is the oversampling SAR ADC structural diagram based on noise shaping technology and margin readout of the present invention;

Figure 2 is a schematic diagram of the operation of a SAR ADC that combines noise shaping and margin readout.

Fig. 3 is the structure of the dual-stage FIR filter in the ADC proposed by the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

As shown in Figure 1, the oversampling SAR ADC based on noise shaping technology and margin readout of the present invention includes: FIR filter 103, comparator 104, high significant bit MSB type digital-to-analog converter 107, low significant bit LSB type Digital-to-analog converter 108, digital logic circuit 105, register 106, average number logic circuit 111, 101 is the signal Vpix sampled by the pixel, 102 is the conversion result V _DAC of analog/digital A/ _D , in the high significant bit MSB type The digital-to-analog converter 107 and the low-significant-bit LSB type digital-to-analog converter 108 are generated, and the signal is differenced by the FIR filter 103 to obtain the quantization error V _R , and this module can also realize the noise shaping function. V _PIX , _VR and V _DAC are all connected to the comparator 104 for comparison, and connected to the successive approximation digital logic circuit 105, where the signal completes the process of reading the margin, and converts it into a digital code, which is connected to the register 106 to copy the MSB The code D _MSB can skip the MSB decision-making process during noise coupling; the digital logic circuit 105 is connected with the high-significant bit MSB-type digital-to-analog converter 107 and the low-significant bit LSB-type digital-to-analog converter 108, and copies D in the register 106 _MSB and readout margin signal access, 109, 110 are control signals, control the A/D converter of high significant bit MSB type digital-to-analog converter 107, low significant bit LSB type digital-to-analog converter 108 to work in MSB mode or LSB mode. The sampling frequency is OSR times the Nyquist frequency, and the above sampling process is also repeated OSR times, and finally the multiple sampling results are transmitted to the average logic circuit 111 to obtain the final output.

Figure 2 illustrates the operation of a SAR ADC combining noise shaping and margin readout. V _PIX[i,j] and V _PIX[i,j+1] are the pixel signals of row i, column j and column (j+1) of the total pixel array, respectively. During oversampling, the input pixel value for A/D conversion is fixed V _PIX[i,j] , this process will perform quantization noise coupling on the signal to achieve noise shaping and improve SNR; constant input V _{PIX[i, j]} All digital codes can be realized by low-order LSB conversion. After oversampling is done, the readout moves to a new pixel V _PIX[i,j+1] , copying the D _MSBs[i,j] of the margin readout scheme, skipping the MSB decision, and getting the complete code.

The low-frequency quantization noise and comparator noise of the SAR ADC can be reduced by using a dual-stage FIR filter. Fig. 3 shows the schematic diagram of the proposed two-stage FIR filter, 301, 302 are filter capacitors C _FIR1 , C _FIR2 ; 303-312 are all switches.

If a two-tap FIR filter is used for the low-pass filter, NTF can be calculated as

Q(z) is the quantization error of A/D conversion. α ₁ and α ₂ are the attenuation factors produced during the sampling process of the quantization error of the FIR filter. The m-th sampling is denoted by Conv[m], and the noise coupling of the two-stage FIR filter works as follows: when Conv[m-1], other switches are opened, 305, 307 are closed, C _FIR1 is reset, and then 305, 306 are opened, Closing 303, 304, the residual V _R[m-1] is sampled on C _FIR1 . When Conv[m], other switches are turned on, 311 and 312 are closed, and when VR _[m-1] and Conv[m-2], the residual difference VR _[m-2] sampled by C _FIR2 is connected to the input terminal of the comparator , the residual voltage is coupled to the current pixel voltage to obtain V _PIX +V _R[m-1] +V _R[m-2] . After Conv[m], 306 and 308 are closed, C _FIR2 is reset, other switches are turned on, 309 and 310 are closed, the new residual V _R[m] is sampled on CFIR2, and the previous residual is maintained on C _FIR1 during this process V _R[m-1] for the next coupling.

The present invention uses a rate much higher than the Nyquist frequency to oversample the input signal of the SAR ADC, which can improve the SNR and resolution, and at the same time reduce the requirements of the anti-aliasing filter and simplify the ADC structure; FIR filtering is adopted In the process of oversampling, the analog-to-digital conversion of constant input can be realized with only a few LSB conversions, so the MSB switching power supply can be saved . After the sampling is completed, the complete code needs to be read out. At this time, the margin readout scheme is applied to copy the MSB code, and there is still a high probability of skipping the MSB decision. At this time, the design cycle is greatly reduced and the readout speed is accelerated.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, these improvements and Retouching should also be regarded as the protection scope of the present invention.

Claims (3)

1. a kind of over-sampling SAR ADC read based on noise shaping techniques and surplus, which is characterized in that including whole with noise The FIR filter of shape function, the comparator being connect with FIR filter, high significance bit MSB type digital analog converter, low order LSB Type digital analog converter, Digital Logical Circuits, the register being connect with Digital Logical Circuits, the average logic being connect with register Circuit, Digital Logical Circuits and high significance bit MSB type digital analog converter, low order LSB type digital analog converter；

FIR filter, the signal V that pixel is sampled_Pix,And by high significance bit MSB type digital analog converter, low order LSB The transformation result signal V of the analog/digital A/D of type digital analog converter output_DACIt makes the difference to obtain quantization error V_R,Then V_PIX、V_RWith V_DACAccess comparator compares, and accesses Digital Logical Circuits later, completes surplus readout and is converted to digital code；Number Logic circuit is connect with register, accesses the MSB code D replicated in register_MSBWith read residual signal, after multiple repairing weld, most The result of multiple repairing weld is reached into average logic circuit afterwards, obtains final output.

2. the over-sampling SAR ADC read according to claim 1 based on noise shaping techniques and surplus, which is characterized in that High significance bit MSB type digital analog converter, low order LSB type digital analog converter are separately connected control signal, high effectively with control The A/D converter work of position MSB type digital analog converter, low order LSB type digital analog converter is in MSB mode or LSB mode.

3. the over-sampling SAR ADC read according to claim 1 based on noise shaping techniques and surplus, which is characterized in that FIR filter is twin-stage FIR filter.