CN104363019B - A kind of production line analog-digital converter and its capacitor mismatch error calibration method - Google Patents
A kind of production line analog-digital converter and its capacitor mismatch error calibration method Download PDFInfo
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- CN104363019B CN104363019B CN201410475044.XA CN201410475044A CN104363019B CN 104363019 B CN104363019 B CN 104363019B CN 201410475044 A CN201410475044 A CN 201410475044A CN 104363019 B CN104363019 B CN 104363019B
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Abstract
The embodiment of the invention discloses a kind of easy calibration program for being directed to production line analog-digital converter capacitor mismatch error, on the basis of tradition is without calibration production line analog-digital converter structure, the calibration level of calibration capacitance mismatch error is needed by level MDAC structures and level calibration switch structure composition, meanwhile increase capacitor mismatch error digital calibration circuit.During calibration level capacitance error extraction work, 2 kinds of specific inputs are given to calibration level sampling capacitance by level calibration switch structure, rood to 2 digital codes comprising capacitor mismatch error, calibration level capacitor mismatch error is extracted further according to it and carries out digital calibration.The capacitor mismatch error calibration program structure is extremely simple, additional element addition extremely less, SECO it is extremely simple, can effectively calibrate because caused by capacitance mismatch static characteristic decline the problem of.
Description
Technical field
The present invention relates to the analog-digital converter for infrared focal plane array reading circuit, more particularly, to a kind of streamline
Analog-digital converter and its capacitor mismatch error calibration method.
Background technology
Reading circuit (ROIC) is uncooled infrared focal plane array（IRFPA）One of critical component, its main work(
Can be that the small-signal of infrared detector sensing is pre-processed（Such as integrate, amplify, filtering, sampling/holding）And array
The parallel/serial row conversion of signal.Depending on detector material therefor and the difference of working method, reading circuit structure changes therewith, with
Meet the signal to noise ratio that maximum is obtained under the requirement of frame frequency（SNR）.
ROIC belongs to numerical model analysis integrated technology.Pixel circuit partly belongs to analog circuit, and it is to metal-oxide-semiconductor channel width-over-length ratio
There is special requirement and more accurately designed than digital circuit, it is necessary to have.In addition, in order to increase the area of integrating capacitor, it is complicated
Circuit design in ROIC and be impermissible for.Advanced ROIC reads noise and raising frame refreshing frequency to reduce, will
The function elements such as filter circuit, analog-to-digital conversion are integrated in chip piece, and this is the trend of ROIC development from now on.
Analog-digital converter is integrated into focal plane arrays (FPA), can not only simplify the Interface design of array and system, can also be incited somebody to action
Easily switched to the data signal of strong antijamming capability by the analog output signal of electromagnetic interference, improve the overall performance of system.
In the classical production line analog-digital converter without calibration, due to manufacturing process, capacitor mismatch error is not
Evitable, it limits effective compromise of resolution ratio and sampling rate to a certain extent, especially in big array, high frame frequency
Uncooled infrared focal plane array sensing technique in, the limitation of higher resolution and higher sampling rate be present.Therefore, deposit
The demand of the capacitor mismatch error of production line analog-digital converter in uncooled infrared focal plane array is calibrated.
The content of the invention
An object of the present invention is to provide a kind of capacitor mismatch error that can effectively calibrate production line analog-digital converter
Production line analog-digital converter and its capacitor mismatch error calibration method.
Technical scheme disclosed by the invention includes：
Provide a kind of production line analog-digital converter, it is characterised in that：Lost including at least two-stage analog-digital converter and electric capacity
With error digital calibration circuit 30, wherein：At least the 1st grade of analog-digital converter 10 includes calibration switch circuit 102 and MDAC circuits
100, the calibration switch circuit 102 includes first switch SC1With second switch SC2, the first switch SC1One end is connected to institute
MDAC circuits 100 are stated, the other end is connected to the first reference voltage+Vref/ 2, the second switch SC2One end is connected to the MDAC
Circuit 100, the other end are connected to the second reference voltage-Vref/2；The capacitor mismatch error digital calibration circuit 30 is connected to institute
State at least two-stage analog-digital converter；Wherein described at least two-stage analog-digital converter is according to the first reference voltage+Vref/ 2 outputs
First digital code, and according to the second reference voltage-Vref/ 2 the second digital codes of output；The capacitor mismatch error numeral school
Quasi- circuit 30 receives first digital code and second digital code, according to first digital code and second digital code
Obtain the capacitor mismatch error calibration code of the production line analog-digital converter and work as the normal work of the production line analog-digital converter
The data of the production line analog-digital converter conversion output are calibrated when making with the capacitor mismatch error calibration code.
In one embodiment of the present of invention, the MDAC circuits 100 include operational amplifier, sampling capacitance CSWith feedback electricity
Hold Cf, the sampling capacitance CSOne end respectively by switch element be connected to the production line analog-digital converter signal input
Hold Vin, the 3rd reference voltage+Vref, the 4th reference voltage-VrefAnd earth terminal, the other end are connected to the anti-of the operational amplifier
Phase input is simultaneously grounded by switch element.
In one embodiment of the present of invention, the feedback capacity CfOne end be connected to the anti-phase defeated of the operational amplifier
Enter end, the other end is connected to the signal input part V of the production line analog-digital converter by switch element respectivelyinWith the computing
The output end V of amplifierout。
In one embodiment of the present of invention, the first switch SC1One end is connected to the sampling capacitance CSDescribed one
End, the other end are connected to the first reference voltage+Vref/2；The second switch SC2One end is connected to the sampling capacitance CS
Described one end, the other end is connected to the second reference voltage-Vref/2。
In one embodiment of the present of invention, first reference voltage be the 3rd reference voltage half, institute
State the half that the second reference voltage is the 4th reference voltage.
Additionally provided in embodiments of the invention a kind of using foregoing production line analog-digital converter calibration capacitance mismatch mistake
The method of difference, it is characterised in that including：Make the sampling capacitance CSWith the feedback capacity CfParallel connection, and one end is grounded, separately
One end is connected to the inverting input of the operational amplifier；Switch switch element, make the sampling capacitance CSOne end connection
To the first reference voltage+Vref/ 2, the other end is connected to the inverting input of the operational amplifier, and makes the feedback
Electric capacity CfOne end be connected to the inverting input of the operational amplifier, the other end is connected to the output of the operational amplifier
End, so as to obtain the first digital code by least two-stage analog-digital converter；Make the sampling capacitance CSWith the feedback electricity
Hold CfParallel connection, and one end is grounded, and the other end is connected to the inverting input of the operational amplifier；Make the sampling capacitance CS
One end be connected to the second reference voltage-Vref/2, the other end is connected to the inverting input of the operational amplifier, and
Make the feedback capacity CfOne end be connected to the inverting input of the operational amplifier, the other end is connected to the computing and put
The output end of big device；So as to obtain the second digital code by least two-stage analog-digital converter；According to first digital code
The capacitor mismatch error calibration code of the production line analog-digital converter is obtained with second digital code；When the streamline modulus
During converter normal work, the number of the production line analog-digital converter conversion output is calibrated with the capacitor mismatch error calibration code
According to.
In embodiments of the invention, can calibrate needs to error caused by the level of capacitor mismatch error, and structure pole
Its simple, additional element is added extremely less, SECO is extremely simple, and numeric field calculates and calibration need to only pass through addition and subtraction
Realize, substantially reduce difficulty and the cycle of Design of Digital Circuit.By simulating, verifying, of the invention turns for streamline modulus
The calibration method of parallel operation capacitor mismatch error can effectively calibrate because caused by capacitance mismatch static characteristic decline the problem of.
Brief description of the drawings
Fig. 1 is the structured flowchart schematic diagram of the production line analog-digital converter of one embodiment of the invention.
Fig. 2 is the structural representation of the 1st grade of analog-digital converter of one embodiment of the invention.
Fig. 3 is the schematic diagram of the MDAC circuits in sampling phase state of one embodiment of the invention.
Fig. 4 is the schematic diagram that the MDAC circuits in phase state are kept in first of one embodiment of the invention.
Fig. 5 is the schematic diagram that the MDAC circuits in phase state are kept in second of one embodiment of the invention.
Fig. 6 is the schematic diagram of the calibration code of one embodiment of the invention.
Fig. 7 is effect diagram before transmission curve calibration be present in the case of positive sampling capacitance mismatch, the black in figure
Dotted line is preferable transmission curve, and solid black lines are transmission curve actual before and after calibration.
Fig. 8 is effect diagram after transmission curve calibration be present in the case of positive sampling capacitance mismatch, the black in figure
Dotted line is preferable transmission curve, and solid black lines are transmission curve schematic diagram actual before and after calibration.
Fig. 9 and Figure 10 is respectively that the production line analog-digital converter of the embodiment of the present invention has larger sampling capacitance mismatch calibration
The Simulink model emulation figures of static characteristic parameter DNL, INL of front and rear.
Embodiment
Below in conjunction with accompanying drawing describe in detail embodiments of the invention production line analog-digital converter concrete structure and its
The specific steps of capacitor mismatch error calibration method.
As shown in figure 1, in one embodiment of the present of invention, a kind of production line analog-digital converter turns including at least two-stage modulus
Parallel operation（For example, 10,12,14,16 etc. in Fig. 1）With capacitor mismatch error digital calibration circuit 30.
In embodiments of the invention, provided with calibration switch circuit, the calibration switch circuit can be arranged at least two-stage
In previous or several grade of analog-digital converter in analog-digital converter.
For example, as depicted in figs. 1 and 2, at least the 1st grade of analog-digital converter 10 includes calibration switch circuit 102 and MDAC
（Multiplying Digital to Analog Converter, multiplying-type digital analog converter）Circuit 100.Calibration switch electricity
Road 102 includes first switch SC1With second switch SC2, first switch SC1One end is connected to MDAC circuits 100, and the other end is connected to
First reference voltage+Vref/ 2, second switch SC2One end is connected to MDAC circuits 100, the other end be connected to the second reference voltage-
Vref/2。
Capacitor mismatch error digital calibration circuit 30 is connected to foregoing at least two-stage analog-digital converter.
In embodiments of the invention, at least two-stage analog-digital converter can be according to the first reference voltage+V for thisref/ 2 outputs the
One digital code, and can be according to the second reference voltage-Vref/ 2 outputs include the second digital code of sampling.First digital code and
Two digital codes all contain sampling capacitance error caused by sampling capacitance in the production line analog-digital converter.
Therefore, in embodiments of the invention, capacitor mismatch error digital calibration circuit 30 can receive first digital code
The capacitor mismatch error of production line analog-digital converter is obtained with the second digital code and according to first digital code and the second digital code
Calibration code.Capacitor mismatch error digital calibration circuit 30 can store these capacitor mismatch error calibration codes, and work as streamline
During analog-digital converter normal work, read these capacitor mismatch error calibration codes and calibrated with the capacitor mismatch error calibration code and flowed
The data of pipeline analog-to-digital converter conversion output.
In embodiments of the invention, production line analog-digital converter can also include Redundant signed digit calibration circuit 20, and this is superfluous
Remaining bit digital correcting circuit is located at this at least between two-stage analog-digital converter and capacitor mismatch error digital calibration circuit 30.That is,
This at least caused by two-stage analog-digital converter the first digital code and the second digital code can pass through Redundant signed digit calibration circuit 20
Correction after be input in capacitor mismatch error digital calibration circuit 30.
As shown in Fig. 2 in one embodiment of the present of invention, MDAC circuits 100 include operational amplifier, sampling capacitance CSWith
Feedback capacity Cf。
Sampling capacitance CSOne end the signal input part V of production line analog-digital converter is connected to by switch element respectivelyin、
3rd reference voltage+Vref, the 4th reference voltage-VrefAnd earth terminal, the other end are connected to the inverting input of operational amplifier
And it is grounded by switch element.
Feedback capacity CfOne end be connected to the inverting input of operational amplifier, the other end is connected by switch element respectively
It is connected to the signal input part V of production line analog-digital converterinWith the output end V of operational amplifierout。
First switch SC1One end is connected to sampling capacitance CSOne end, the other end is connected to the first reference voltage+Vref/2；
Second switch SC2One end is connected to sampling capacitance CSOne end, the other end is connected to the second reference voltage-Vref/2。
In previously described embodiments of the present invention, it can be seen that the first reference voltage is the half of the 3rd reference voltage, the
Two reference voltages are the half of the 4th reference voltage.
In one embodiment of the present of invention, the method for foregoing production line analog-digital converter calibration capacitance mismatch error is used
It can comprise the following steps.
It is possible, firstly, to by switching switch element（I.e. by controlling each switch element in the 1st grade of analog-digital converter 10
Disconnection and closure）, make sampling capacitance CSWith feedback capacity CfParallel connection, and one end is grounded, and the other end is connected to operational amplifier
Inverting input, as shown in Figure 3.This state is referred to as " sampling phase ".
Then, by switching switch element（I.e. by controlling the disconnected of each switch element in the 1st grade of analog-digital converter 10
Open and close are closed）Disconnection that can be by each switch element in the 1st grade of analog-digital converter 10 of control and closure, make sampling capacitance
CSOne end be connected to the first reference voltage+Vref/ 2, the other end is connected to the inverting input of operational amplifier, and makes feedback
Electric capacity CfOne end be connected to the inverting input of operational amplifier, the other end is connected to the output end of operational amplifier, such as Fig. 4
It is shown.This state is referred to as " first keeps phase ".Now, at least two-stage analog-digital converter work exports the first digital code
Dp1.First digital code Dp1In contain sampling capacitance error.
Then, by switching switch element, sampling capacitance C is madeSWith feedback capacity CfReturn to sampling phase.
Then, by controlling disconnection and the closure of each switch element in the 1st grade of analog-digital converter 10, sampling capacitance is made
CSOne end be connected to the second reference voltage-Vref/ 2, the other end is connected to the inverting input of operational amplifier, and makes feedback
Electric capacity CfOne end be connected to the inverting input of operational amplifier, the other end is connected to the output end of operational amplifier, such as Fig. 5
It is shown.This state is referred to as " second keeps phase ".Now, at least two-stage analog-digital converter work exports the second digital code
Dp2.Second digital code Dp2In contain sampling capacitance error.
Then, capacitor mismatch error digital calibration circuit 30 receives first digital code Dp1With the second digital code Dp2, and root
The capacitor mismatch error calibration code of production line analog-digital converter is obtained according to first digital code and the second digital code.For example, one
In embodiment, the capacitor mismatch error calibration code can be 2 (Dp1+ Vref /2)、2(Dp1 - Vref /2)。
When production line analog-digital converter normal work, capacitor mismatch error digital calibration circuit 30 can use the electric capacity
The data of mismatch error calibration code calibration production line analog-digital converter conversion output.
The production line analog-digital converter and the principle of foregoing method being briefly described as follows in the embodiment of the present invention.
Capacitor mismatch error can be expressed as-DCsVref/Cf, wherein D is in different input signal VinWhen be respectively-
1st, 0 ,+1, i.e., the 1.5bit of embodiments of the invention as shown in Figure 2 MDAC capacitor mismatch error are+Δ CsVref/CfWith-
ΔCsVref/Cf, so its corresponding calibration code isCode00WithCode10, calibration code schematic diagram is as shown in Figure 6.
In 2 particular calibration error extracting cycles of the embodiment of the present invention, the sampling phase in 2 cycles as shown in figure 3,
In the sampling phase of this 2 calibration error extracting cycles, the total electrical charge of two electric capacity is zero.
In 2 particular calibration error extracting cycles of the embodiment of the present invention, the holding phase in the 1st cycle（First keeps phase）
As shown in figure 4, obtain the first digital code Dp1（As mentioned before）；The holding phase in the 2nd cycle（Second keeps phase）As shown in figure 5,
Obtain the second digital code Dp2（As mentioned before）.
After 2 specific calibration error extracting cycles, obtained two digital codes comprising sampling capacitance mismatch error
It is separately stored in the register of capacitor mismatch error digital calibration circuit 30, and carries out computing wherein, the digital operation
Can only comprising the addition and subtraction on numeric field, required additional element extremely less, SECO it is extremely simple.The present invention one
In embodiment, 1.5bit calibration codesCode00、Code10Can be respectively 2 (Dp1+ Vref /2)、2(Dp1 - Vref /2)。
In embodiments of the invention, using keeping mutually access+Vref/ 2 and-Vref/ 2 method, can force rear class without
The output digital-to-analogue of the analog-digital converter of circuit is calibrated at 3/4 and 1/4, is realized by capacitor mismatch error digital calibration circuit 30
Calibration to capacitor mismatch error, in the 1.5bit of embodiment MDAC structures, by adding corresponding school to different sections
Quasi- code, realize the calibration of error；Directly perceived in transmission curve shows as moving for error.
Fig. 7 and Fig. 8 is respectively that the schematic diagram after preceding and calibration is calibrated in the case of positive sampling capacitance mismatch being present, in figure
Black dotted lines be preferable transmission curve, solid black lines are transmission curve schematic diagram actual before and after calibration.
Fig. 9 and Figure 10 is respectively that the production line analog-digital converter of the embodiment of the present invention has larger sampling capacitance mismatch calibration
The Simulink model emulation figures of static characteristic parameter DNL, INL of front and rear.It can be seen that there is very big lifting to static characteristic.
In embodiments of the invention, can calibrate needs to error caused by the level of capacitor mismatch error, and structure pole
Its simple, additional element is added extremely less, SECO is extremely simple, and numeric field calculates and calibration need to only pass through addition and subtraction
Realize, substantially reduce difficulty and the cycle of Design of Digital Circuit.By simulating, verifying, of the invention turns for streamline modulus
The calibration method of parallel operation capacitor mismatch error can effectively calibrate because caused by capacitance mismatch static characteristic decline the problem of.
Above by specific embodiment, the present invention is described, but the present invention is not limited to these specific implementations
Example.It will be understood by those skilled in the art that various modifications, equivalent substitution, change etc. can also be made to the present invention, these conversion
, all should be within protection scope of the present invention without departing from the spirit of the present invention.In addition, " the reality described in above many places
Apply example " represent different embodiments, naturally it is also possible to it is completely or partially combined in one embodiment.
Claims (6)
- A kind of 1. production line analog-digital converter, it is characterised in that：Including at least two-stage analog-digital converter and capacitor mismatch error number Word calibrates circuit（30）, wherein：At least the 1st grade of analog-digital converter（10）Including calibration switch circuit（102）With MDAC circuits（100）, the calibration switch Circuit（102）Including first switch（SC1）And second switch（SC2）, the first switch（SC1）One end is connected to the MDAC electricity Road（100）, the other end is connected to the first reference voltage（+Vref/2）, the second switch（SC2）One end is connected to the MDAC electricity Road（100）, the other end is connected to the second reference voltage（-Vref/2）；The capacitor mismatch error digital calibration circuit（30）It is connected at least two-stage analog-digital converter；Wherein described at least two-stage analog-digital converter is according to first reference voltage（+Vref/2）Export the first digital code, and root According to second reference voltage（-Vref/2）Export the second digital code；The capacitor mismatch error digital calibration circuit（30）Receive first digital code and second digital code, according to institute State the first digital code and second digital code obtain the production line analog-digital converter capacitor mismatch error calibration code and The streamline modulus is calibrated when the production line analog-digital converter normal work with the capacitor mismatch error calibration code to turn The data of parallel operation conversion output.
- 2. production line analog-digital converter as claimed in claim 1, it is characterised in that：The MDAC circuits（100）Including computing Amplifier, sampling capacitance（CS）And feedback capacity（Cf）, the sampling capacitance（CS）One end be connected to respectively by switch element The signal input part of the production line analog-digital converter（Vin）, the 3rd reference voltage（+Vref）, the 4th reference voltage（-Vref）With Earth terminal, the other end are connected to the inverting input of the operational amplifier and are grounded by switch element.
- 3. production line analog-digital converter as claimed in claim 2, it is characterised in that：The feedback capacity（Cf）One end connection To the inverting input of the operational amplifier, the other end is connected to the production line analog-digital converter by switch element respectively Signal input part（Vin）With the output end of the operational amplifier（Vout）.
- 4. production line analog-digital converter as claimed in claim 2, it is characterised in that：The first switch（SC1）One end is connected to The sampling capacitance（CS）Described one end, the other end is connected to first reference voltage（+Vref/2）；The second switch （SC2）One end is connected to the sampling capacitance（CS）Described one end, the other end is connected to the second reference voltage（-Vref/2）.
- 5. production line analog-digital converter as claimed in claim 2, it is characterised in that：First reference voltage is the described 3rd The half of reference voltage, second reference voltage are the half of the 4th reference voltage.
- 6. a kind of method using production line analog-digital converter calibration capacitance mismatch error as claimed in claim 2, its feature It is, including：Make the sampling capacitance（CS）With the feedback capacity（Cf）Parallel connection, and one end is grounded, and the other end is connected to the computing The inverting input of amplifier；Switch switch element, make the sampling capacitance（CS）One end be connected to first reference voltage（+Vref/2）, the other end The inverting input of the operational amplifier is connected to, and makes the feedback capacity（Cf）One end be connected to the operation amplifier The inverting input of device, the other end are connected to the output end of the operational amplifier, so as to be turned by least two-stage modulus Parallel operation obtains the first digital code；Make the sampling capacitance（CS）With the feedback capacity（Cf）Parallel connection, and one end is grounded, and the other end is connected to the computing The inverting input of amplifier；Make the sampling capacitance（CS）One end be connected to second reference voltage（-Vref/2）, the other end is connected to the fortune The inverting input of amplifier is calculated, and makes the feedback capacity（Cf）One end be connected to the anti-phase input of the operational amplifier End, the other end are connected to the output end of the operational amplifier；So as to obtain second by least two-stage analog-digital converter Digital code；The capacitor mismatch error of the production line analog-digital converter is obtained according to first digital code and second digital code Calibration code；When the production line analog-digital converter normal work, the streamline mould is calibrated with the capacitor mismatch error calibration code The data of number converter conversion output.
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| CN106571821B (en) * | 2015-10-13 | 2020-10-09 | 上海贝岭股份有限公司 | Foreground calibration method of pipeline ADC (analog to digital converter) |
| CN105577190B (en) * | 2015-12-23 | 2018-12-25 | 成都华微电子科技有限公司 | Capacitor linearity auto-correction method suitable for analog-digital converter |
| CN106209100B (en) * | 2016-08-04 | 2019-06-07 | 成都博思微科技有限公司 | A kind of LMS error correcting system and method applied to high-speed ADC |
| CN106230438A (en) * | 2016-08-04 | 2016-12-14 | 成都博思微科技有限公司 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
| CN110504966B (en) * | 2019-08-19 | 2022-12-09 | 苏州迅芯微电子有限公司 | Calibration system and method of analog-to-digital converter |
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| CN102177657A (en) * | 2008-08-12 | 2011-09-07 | 美国亚德诺半导体公司 | Correlation-based background calibration of pipelined converters with reduced power penalty |
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| CN103988435A (en) * | 2011-11-14 | 2014-08-13 | 美国亚德诺半导体公司 | Calibrating timing, gain and bandwidth mismatch in interleaved ADCs |
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