CN104038220A

CN104038220A - 16-bit pipelined analog-digital converter

Info

Publication number: CN104038220A
Application number: CN201310070652.8A
Authority: CN
Inventors: 朱樟明; 魏伟; 杨银堂; 刘敏杰
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2013-03-06
Filing date: 2013-03-06
Publication date: 2014-09-10
Anticipated expiration: 2033-03-06
Also published as: CN104038220B

Abstract

The invention provides a 16-bit pipelined analog-digital converter comprising a pre-posed sampling hold circuit, a first-stage multi-bits digital-analog converter, a second-stage multi-bits digital-analog converter, a third-stage multi-bits digital-analog converter, a fourth-stage multi-bits digital-analog converter and a fifth-stage flash analog-digital converter, which are connected in sequence. The 16-bit pipelined analog-digital converter further comprises a digital correction circuit respectively connected with the first-stage multi-bits digital-analog converter, the second-stage multi-bits digital-analog converter, the third-stage multi-bits digital-analog converter, the fourth-stage multi-bits digital-analog converter and the fifth-stage flash analog-digital converter. A digital correction technology is adopted in the analog-digital converters to enable the analog-digital converters to allow a comparator to have certain offset on the premise of not affecting the performance of the analog-digital converters. In addition, sub DAC error and inter-stage gain error in the MDACs caused by capacitor mismatch are eliminated through front-end analog calibration. The scheme of the invention can effectively shorten the calibration time.

Description

A kind of 16 flow-line modulus converters

Technical field

The present invention relates to technical field of composite signal integrated circuits, refer to especially a kind of 16 125MSPS CMOS flow-line modulus converters.

Background technology

Along with the development of modern communications technology and Digital Signal Processing, whole communication system has higher requirement in speed and precision to the interface circuit of analog signal and digital signal, therefore need to design the analog-to-digital conversion device of high-speed, high precision.

In existing structure, precision realizes higher than being difficult in more than 10 pipeline-type modulus converters, and this is owing to being subject to the matching restriction of capacitor on chip and the threshold value imbalance restriction of comparator.Analog-to-digital conversion device needs corresponding collimation technique and alignment technique.

In realizing process of the present invention, find that in prior art, there are the following problems: the alignment time that most of digital calibration techniques need to be very long realizes.

Summary of the invention

The technical problem to be solved in the present invention is to provide a kind of 16 125MSPS CMOS flow-line modulus converters, effectively shortens the time of calibration.

For solving the problems of the technologies described above, embodiments of the invention provide a kind of 16 flow-line modulus converters, comprising:

The preposition sampling hold circuit being linked in sequence, the first order, the second level, the third level, fourth stage long number digital to analog converter and level V quick flashing analog to digital converter, and the digital correction circuit being connected with the described first order, the second level, the third level, fourth stage long number digital to analog converter and described level V quick flashing analog to digital converter respectively; Wherein,

Described sampling hold circuit is sampled to input signal, and exports described input signal to first order long number digital to analog converter;

First order long number digital to analog converter is sampled to the output of described sampling hold circuit, and will quantize residue difference amplification output, completes the coding of the corresponding levels being exported to the output valve of controlled comparator simultaneously;

Second level long number digital to analog converter is sampled to the output of first order long number digital to analog converter, and will quantize residue difference amplification output, completes the coding of the corresponding levels being exported to the output valve of controlled comparator simultaneously;

Third level long number digital to analog converter is sampled to the output of second level long number digital to analog converter, completes the coding of the corresponding levels being exported to the output valve of controlled comparator simultaneously;

Fourth stage long number digital to analog converter is sampled to the output of third level long number digital to analog converter, completes the coding of the corresponding levels being exported to the output valve of controlled comparator simultaneously;

Level V quick flashing analog to digital converter is sampled to the output of fourth stage long number digital to analog converter, completes the coding of the corresponding levels being exported to the output valve of controlled comparator simultaneously;

Third level long number digital to analog converter is identical with the sequential of first order long number digital to analog converter with described level V quick flashing analog to digital converter;

Fourth stage long number digital to analog converter is identical with the sequential of second level long number digital to analog converter.

Wherein, described preposition sampling hold circuit comprises: the first operational amplifier (Ash1), the first, second, third and the 4th bootstrapped switch, transmission gate and electric capacity;

The positive-negative input end of described the first operational amplifier is shorted together by a nmos pass transistor (M7), and an input voltage (Vin_com) is joined to the positive-negative input end of described the first operational amplifier by a nmos pass transistor (M5) and a nmos pass transistor (M6);

The positive-negative output end of described the first operational amplifier is shorted together by a nmos pass transistor (M8), for the output of described the first operational amplifier is resetted;

The first bootstrapped switch (S1), the second bootstrapped switch (S2) are exported corresponding control signal the nmos pass transistor (M1) and the nmos pass transistor (M2) that play on-off action are opened, the 19 electric capacity (C19), the 17 electric capacity (C17) are connected with positive input signal, and the 20 electric capacity (C20) is connected with negative input signal with the 18 electric capacity (C18);

Described transmission gate is transferred to output according to the low and high level of control signal by the signal of input or disconnects with output;

Described the first bootstrapped switch and the second bootstrapped switch reset, and output signal is low level, and the source electrode of a nmos pass transistor (M1) and a nmos pass transistor (M2) and drain electrode are disconnected;

Described the 3rd bootstrapped switch (S3) and the 4th bootstrapped switch (S4) are exported effective control signal, made a nmos pass transistor (M3) and another nmos pass transistor (M4) conducting of on-off action, the bottom crown of described the 17 electric capacity (C17), described the 19 electric capacity (C19) and described the 18 electric capacity (C18), described the 20 electric capacity (C20) has been connected with the negative positive output end that described fortune first is calculated amplifier respectively;

When described the first operational amplifier is normally worked, the signal of sampling is kept and is outputed to the input of streamline first order long number digital to analog converter.

Wherein, described streamline first order long number digital to analog converter comprises: the second operational amplifier (A1), 10 transmission gates, 64 switch arrays, electric capacity and 32 controlled comparators of output;

Wherein, described the second operational amplifier (A1) positive-negative input end is shorted together by a nmos pass transistor (M62), and at the input of described the second operational amplifier A 1, has added input common-mode reference level Vcom1 by a nmos pass transistor (M60) and a nmos pass transistor (M61); The output of described the second operational amplifier (A1) is shorted together by a nmos pass transistor (M77), and the output of described the second operational amplifier (A1) is played a part to reset;

Described 32 controlled comparators of output are realized the sampling to input signal;

Described transmission gate, under the control of control signal, makes one end ground connection of the electric capacity that is connected with transmission gate or connects input common-mode reference level;

The output of described switch arrays is determined by the output of exporting controlled comparator.

Wherein, described streamline first order long number digital to analog converter also comprises:

Coding circuit, for encoding the output of the controlled comparator of output.

Wherein, described streamline second level long number digital to analog converter comprises: the 3rd operational amplifier (A2), 8 transmission gates, 32 switch arrays, electric capacity and 16 controlled comparators of output;

The positive-negative input end of described the 3rd operational amplifier (A2) is shorted together by a nmos pass transistor (M86), and adding input common mode reference voltage (Vcom2) by a nmos pass transistor (M84) and a nmos pass transistor (M85), positive-negative output end is also shorted together by a nmos pass transistor (M106);

Described 16 controlled comparators of output are realized the sampling to input signal;

Described 8 transmission gates, under the control of control signal, make one end ground connection of the electric capacity that is connected with transmission gate or connect input common-mode reference level;

Wherein, described streamline second level long number digital to analog converter also comprises:

16 positive calibration error memory circuits, for storing first order long number digital to analog converter with the caused error of capacitance mismatch that 16 controlled comparators of output are associated;

16 negative calibration error memory circuits, for storing first order long number digital to analog converter with the caused error of capacitance mismatch that other 16 controlled comparators of output are associated.

Wherein, described streamline third level long number digital to analog converter comprises: the 3rd operational amplifier (A3), 18 switch arrays, electric capacity and 17 controlled comparators of output;

The positive-negative input end of described the 3rd operational amplifier (A3) is shorted together by a nmos pass transistor (M124), and adding input common mode reference voltage Vcom3 by a nmos pass transistor (M122) and a nmos pass transistor (M123), positive-negative output end is shorted together by a nmos pass transistor (M128);

Described 17 controlled comparators of output are realized the sampling to input signal;

Wherein, described streamline third level long number digital to analog converter also comprises:

9 positive calibration error memory circuits, for storing second level long number digital to analog converter with the caused error of capacitance mismatch that 9 controlled comparators of output are associated;

8 negative calibration error memory circuits, for storing second level long number digital to analog converter with the caused error of capacitance mismatch that other 8 controlled comparators of output are associated.

Wherein, described streamline third level long number digital to analog converter also comprises: a coding circuit (E3), and for the output of the controlled comparator of output is encoded.

Wherein, described streamline fourth stage long number digital to analog converter comprises: four-operational amplifier (A4), 20 switch arrays, electric capacity and 16 controlled comparators of output;

Wherein, the positive-negative input end of described four-operational amplifier (A4) is shorted together by a nmos pass transistor (M144), and adding input common mode reference voltage Vcom4 by a nmos pass transistor (M142) and a nmos pass transistor (M143), positive-negative output end is shorted together by a nmos pass transistor (M152);

Wherein, described streamline fourth stage long number digital to analog converter also comprises: coding circuit 4, and for the output of the controlled comparator of output is encoded.

Wherein, described level V quick flashing analog to digital converter comprises:

7 comparators, for sampling to input signal.

Wherein, described level V quick flashing analog to digital converter also comprises: coding circuit E5, and for the output of comparator is encoded.

Wherein, described positive calibration error memory circuit comprises:

2 cmos transmission gates, 4 reversers, a NAND gate, together or door, current regulating circuit, 2 resistance, 2 nmos pass transistors; Wherein,

Described 2 cmos transmission gates are linked in sequence, and the first reverser (I1) in 4 reversers is connected with the first transmission gate of described 2 cmos transmission gates, and the second reverser (I2) is connected with the second transmission gate, and the first reverser is connected with the second reverser; Described the first reverser is also connected with described NAND gate, described NAND gate with described with or door be connected, described same or Men Yu tri-reversers connections, described the 3rd reverser is connected with the 4th reverser, described the 3rd reverser is connected with current regulating circuit by the first metal-oxide-semiconductor, described current regulating circuit is by a grounding through resistance, and described the 4th reverser is by a metal-oxide-semiconductor and grounding through resistance, and the metal-oxide-semiconductor being connected with the 4th reverser interconnects with the metal-oxide-semiconductor being connected with the 3rd reverser.

The beneficial effect of technique scheme of the present invention is as follows:

In such scheme, adopt analogue technique to calibrate, not only can improve the precision of analog-to-digital conversion device, effectively shorten the time of calibration.Adopt 4 times of the inter-stage gain compression of streamline first order MDAC simultaneously, streamline second level MDAC, streamline third level MDAC, the quantizing range of the quick flashing ADC of streamline fourth stage MDAC, streamline level V expands twice mode to be proofreaied and correct, and is used for eliminating the impact that the threshold value imbalance of the comparator in every grade of MDAC of streamline produces.

Accompanying drawing explanation

Fig. 1 is the functional block diagram of 16 125MSPS CMOS pipeline-type modulus converters in embodiments of the invention;

Fig. 2 is the schematic diagram of preposition sampling hold circuit in Fig. 1;

Fig. 3 is the schematic diagram of the streamline first order MDAC in Fig. 1;

Fig. 4 is the schematic diagram of the streamline second level MDAC in Fig. 1;

Fig. 5 is the schematic diagram of the streamline third level MDAC in Fig. 1;

Fig. 6 is the schematic diagram of the streamline fourth stage MDAC in Fig. 1;

Fig. 7 is the schematic diagram of the streamline level V quick flashing ADC in Fig. 1;

Fig. 8 is the schematic diagram of the digital correction circuit in Fig. 1;

Fig. 9 is the schematic diagram of the positive calibration error memory circuit in Fig. 4.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

First, technical term involved in the present invention is described:

PMOS:P-channel metal oxide semiconductor FET, P-channel metal-oxide-semiconductor field-effect transistor;

NMOS:N-channel metal oxide semiconductor FET, n channel metal oxide semiconductor field effect transistor;

CMOS:complementary metal oxide semiconductor FET, complementary metal oxide semiconductor field effect transistor;

ADC:analog-digital converter, analog-to-digital conversion device;

DAC:digital-analog converter, digital-to-analogue converter;

MDAC:Multi-bits digital-analog converter, long number digital-to-analogue device, refers in particular to every grade of circuit of pipeline-type modulus converter in the present invention.

Referring to Fig. 1, functional block diagram for 16 125MSPS CMOS pipeline-type modulus converters in embodiments of the invention, known in figure, this pipeline-type modulus converter comprises front-end sampling holding circuit, streamline first order long number digital to analog converter (MDAC), streamline second level long number digital to analog converter (MDAC), streamline third level long number digital to analog converter (MDAC), streamline fourth stage long number digital to analog converter (MDAC), streamline level V quick flashing ADC and the digital correction circuit being linked in sequence.Wherein:

Below in conjunction with concrete accompanying drawing, the various piece in foregoing circuit is elaborated:

Preposition sampling hold circuit, adopt the convertible circuit structure of fully differential electric charge, fully differential structure is conducive to suppress the impact of electric source disturbance on circuit performance, the convertible feedback factor of electric charge approaches 1, to the bandwidth requirement of the operational amplifier in sampling hold circuit, will reduce like this, the positive feedback realizing by capacitor C 17 and capacitor C 18 regulates the precision of setting up of sampling hold circuit, and the random signal of utilizing pseudorandom number generator to produce joins the output of sampling hold circuit, to make, at input signal, compared with a hour whole analog to digital converter, there is the good linearity, the random signal adding will deduct in digital correction circuit.

Referring to Fig. 2, known in figure, when clock signal is low level, at this moment clock signal clk_n1 and clk_n2 are high level.The positive-negative input end of operational amplifier A sh1 in sampling hold circuit is shorted together by nmos pass transistor M7, and voltage Vin_com is joined to the positive-negative input end of the operational amplifier A sh1 in sampling hold circuit by nmos pass transistor M5 and nmos pass transistor M6, nmos pass transistor M8 is shorted together the positive-negative output end of the operational amplifier A sh1 in sampling hold circuit, plays a part the operational amplifier A sh1 output in sampling hold circuit to reset.While bootstrapped switch S1 and bootstrapped switch S2 export corresponding control signal the nmos pass transistor M1 and the nmos pass transistor M2 that play on-off action are opened, make capacitor C 19, capacitor C 17, capacitor C 20 is connected with negative input signal with positive input signal respectively with capacitor C 18, namely completes the sampling to input signal.Fixed voltage Vref and fixed voltage Vin_com will be accessed respectively by nmos pass transistor M5, nmos pass transistor M6, nmos pass transistor M9 and transistor M10 in the two ends of capacitor C 15 and capacitor C 16.At this moment control signal dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, dith6_p signal is all low level, control signal dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n signal is all high level, so cmos transmission gate T1, cmos transmission gate T3, cmos transmission gate T5, cmos transmission gate T7, cmos transmission gate T9, cmos transmission gate T11, cmos transmission gate T14, cmos transmission gate T16, cmos transmission gate T18, cmos transmission gate T20 and cmos transmission gate T22 normally work, cmos transmission gate T2, cmos transmission gate T4, cmos transmission gate T6, cmos transmission gate T8, cmos transmission gate T10, cmos transmission gate T12, cmos transmission gate T13, cmos transmission gate T15, cmos transmission gate T17, the input of cmos transmission gate T19 and cmos transmission gate T21 and output disconnect, and at this moment capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, one end access fixed level Vref of capacitor C 6 and capacitor C 7, the other end also accesses fixed level Vref, one end access fixed level Vref_dith of capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12 and capacitor C 13, other end access level Vref, one end ground connection of capacitor C 1 and capacitor C 14, other end access fixed level Vref.When clock level is high level, at this moment clock signal clk_n1 and clk_n2 are low level.At this moment bootstrapped switch S1 and bootstrapped switch S2 reset, output signal is low level, source electrode and the drain electrode of nmos pass transistor M1 and nmos pass transistor M2 are disconnected, bootstrapped switch S3 and bootstrapped switch S4 export effective control signal, made nmos pass transistor M3 and the nmos pass transistor M4 conducting of on-off action, the bottom crown of capacitor C 17, C19 and capacitor C 18, C20 has been connected with the negative positive output end of operational amplifier A sh1 in sampling hold circuit respectively.At this moment the operational amplifier A sh1 in sampling hold circuit normally works, and the signal of sampling is kept and outputs to the input of streamline first order MDAC.According to input signal size, when need to not be when input port adds random signal, at this moment control signal dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, dith6_p are still low level, and control signal dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n are still high level.When needs are when input port adds random signal, because control signal dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n are respectively the anti-of control signal dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, dith6_p.At this moment the change at random of control signal dith1_p, dith2_p, dith3_p, dith4_p, dith5_p, dith6_p low and high level, so also random variation of the low and high level of corresponding control signal dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n, the cmos transmission gate of being controlled by control signal is like this also by corresponding conducting or shutoff, realization is the charging to capacitor C 12 to capacitor C 2, thereby in the output signal of sampling hold circuit, has added the signal of change at random.In digital correction circuit, according to the low and high level of control signal dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, dith6_n, judge the random signal size adding in sampling hold circuit and it is deducted in the Output rusults of conversion.

Referring to Fig. 3, streamline first order MDAC, adopt the convertible circuit structure of fully differential electric charge, under normal operation, the output of sampling hold circuit is carried out to the quantification of five, output six digit numeric code, and the residue difference after quantizing is carried out to the amplification of 8 times, with respect to theory, should carry out the amplification of 32 times, actual multiplication factor is compressed 1/4.Here select compression 1/4, the mainly consideration based on following, first, because can making the residue difference producing at the corresponding levels, the imbalance of the threshold value of comparator surpassed the quantizing ranges of subordinate after amplifying 32 times, this can introduce nonlinearity erron, so the multiple amplifying is compressed accordingly, to eliminate this impact; Its two, consider the restriction of the output voltage swing scope of operational amplifier in MDAC, so select compression 1/4, rather than 1/2; They are three years old, consider the required precision of comparator, the multiple of compression is larger, it is larger that the quantizing range of the MDAC of subordinate just reduces, the precision for the comparator that quantizes of subordinate is also just higher like this, thus select compression 1/4 here, rather than 1/8, in the situation that the quantification of three of subordinates, subordinate to the required precision of comparator with at the corresponding levels identical be all to reach five precision; Corresponding transfer function expression formula at the corresponding levels:

Voutp 1 - Voutn 1 = \{\begin{matrix} 8 (Vinp 1 - Vinn 1 + \frac{31 Vref}{64}) & Vinp 1 - Vinn 1 \leq \frac{- 15}{32} Vref \\ 8 (Vinp 1 - Vinn 1 - \frac{(2 i_{1} - 1) Vref}{64}) & \frac{(i_{1} - 1)}{32} Vref < Vinp 1 - Vinn 1 \leq \frac{i_{1}}{32} Vref \\ 8 (Vinp 1 - Vinn 1 - \frac{33 Vref}{64}) & Vinp 1 - Vinn 1 < \frac{16}{32} Vref \end{matrix}

Wherein Voutp1 is positive output value at the corresponding levels, and Voutn1 is negative output value at the corresponding levels, and Vinp1 is positive input value at the corresponding levels, and Vinn1 is negative input value at the corresponding levels, and Vref is reference voltage level, is also the quantizing range of ADC simultaneously, i ₁for corresponding integer, its span is-14≤i ₁≤ 16.

At this moment all comparator output is still 0, judges the size of inter-stage gain by comparing this twice output code.When inter-stage gain at the corresponding levels is less than 8 times, by adjustment, can increase inter-stage and gain, when inter-stage gain at the corresponding levels is greater than 8 times, by adjustment, can reduces inter-stage at the corresponding levels and gain.Here it should be noted that, calibration at the corresponding levels is to carry out after the calibration of rear class completes.That antithetical phrase DAC calibrates afterwards, by calibration control signal, the output of controlled comparator is controlled, in fixing input value referring to Fig. 3, known in figure, when normal work, when clock is while being high, clock signal clk1_p, clk1_p1, clk1_p2 are high level, at this moment 1 positive-negative input end of the operational amplifier A in MDAC is shorted together by nmos pass transistor M62, and at the input of operational amplifier A 1, has added input common-mode reference level Vcom1 by nmos pass transistor M60 and nmos pass transistor M61.The output of the operational amplifier A 1 in MDAC is shorted together by nmos pass transistor M77, and the output of the operational amplifier A 1 in MDAC is played a part to reset.At this moment the controlled comparator C oc1 of output at the corresponding levels to positive output and the negative output of exporting controlled comparator C oc32 be all 1, anti-and the negative output of positive output be all instead 0, so the switch arrays Sr1 in the corresponding levels to the PMOS transistor being connected with reference voltage Vref in switch arrays Sr64 and the nmos pass transistor that is connected to the ground all in off state, only has the nmos pass transistor conducting being connected with negative input signal with positive input signal, at this moment nmos pass transistor M50 in addition, nmos pass transistor M51, nmos pass transistor M54, nmos pass transistor M58 and nmos pass transistor M59 conducting, thereby realize capacitor C 25 to the sampling of 93 pairs of input signals of capacitor C.Export controlled comparator C oc1 simultaneously and also realize the sampling to input signal to exporting controlled comparator C oc32.Nmos pass transistor M74 and nmos pass transistor M75 conducting in addition, one end access input common-mode reference level Vcom1 by cmos transmission gate T35 to cmos transmission gate T44, at this moment control signal VCmdac1_gain1_p and VCmdac1_gain1_n will control conducting or the shutoff of cmos transmission gate T35, cmos transmission gate T44, nmos pass transistor M74 and nmos pass transistor M65, thereby determine one end ground connection when clock is high level of capacitor C 94 and capacitor C 103 or meet input common-mode reference level Vcom1; Control signal VCmdac1_gain2_p and VCmdac1_gain2_n will control conducting or the shutoff of cmos transmission gate T36, cmos transmission gate T43, nmos pass transistor M73 and nmos pass transistor M66, thereby determine one end ground connection when clock is high level of capacitor C 95 and capacitor C 102 or meet input common-mode reference level Vcom1; Control signal VCmdac1_gain3_p and VCmdac1_gain3_n will control conducting or the shutoff of cmos transmission gate T37, cmos transmission gate T42, nmos pass transistor M72 and nmos pass transistor M67, thereby determine one end ground connection when clock is high level of capacitor C 96 and capacitor C 101 or meet input common-mode reference level Vcom1; Control signal VCmdac1_gain4_p and VCmdac1_gain4_n will control conducting or the shutoff of cmos transmission gate T38, cmos transmission gate T41, nmos pass transistor M71 and nmos pass transistor M68, thereby determine one end ground connection when clock is high level of capacitor C 97 and capacitor C 100 or meet input common-mode reference level Vcom1; Control signal VCmdac1_gain5_p and VCmdac1_gain5_n will control conducting or the shutoff of cmos transmission gate T39, cmos transmission gate T40, nmos pass transistor M70 and nmos pass transistor M69, thereby determine one end ground connection when clock is high level of capacitor C 98 and capacitor C 99 or meet input common-mode reference level Vcom1.Coding circuit circuit E1 is in reset mode, and output code is 0 entirely.When clock level is low level, clock signal clk1_p, clk1_p1, clk1_p2 are low level, at this moment the operational amplifier A in MDAC 1 is normally worked, bootstrapped switch S5 and bootstrapped switch S6 export effective control signal, nmos pass transistor M63 and nmos pass transistor M64 conducting, be connected the bottom crown of capacitor C 93 and capacitor C 25 respectively with the negative positive output end of operational amplifier A 1 in MDAC.Sampling control signal Vsamp1 and Vsamn1 namely the bootstrapped switch S3 in sampling hold circuit and the output of bootstrapped switch S4 are low level, so all sampling switchs all disconnect.At this moment switch arrays Sr1 determines to the output of exporting controlled comparator C oc32 by exporting controlled comparator C oc1 to the output of switch arrays Sr64.Export controlled comparator C oc1 to output relatively the judging according to input signal and threshold size of exporting controlled comparator C oc32.The comparator threshold of streamline first order MDAC is respectively 16/32Vref, 15/32Vref, 14/32Vref, 13/32Vref, 12/32Vref, 11/32Vref, 10/32Vref, 9/32Vref, 8/32Vref, 7/32Vref, 6/32Vref, 5/32Vref, 4/32Vref, 3/32Vref, 2/32Vref, 1/32Vref, 0/32Vref,-1/32Vref,-2/32Vref,-3/32Vref,-4/32Vref,-5/32Vref,-6/32Vref,-7/32Vref,-8/32Vref,-9/32Vref,-10/32Vref,-11/32Vref,-12/32Vref,-13/32Vref,-14/32Vref,-15/32Vref.At this moment PMOS transistor M55, PMOS transistor M56 and PMOS transistor M57 conducting in addition.When normal work, control signal Vcorrect1 is always high level, and PMOS transistor M52 turn-offs, and control signal Vnormal1 and clk1_p1 are anti-phase, nmos pass transistor M53 conducting.Thereby realize the charging again to capacitor C 92 to capacitor C 26.Capacitor C 25 is identical to the total capacitance size of capacitor C 93 these 34 electric capacity with C60 to the total capacitance size of capacitor C 59 these 35 electric capacity, be all 64 specific capacitance C0_1, wherein the size of capacitor C 25 and capacitor C 93 is all 8 specific capacitance C0_1, the size of capacitor C 59 is 23 specific capacitance C0_1, the size of capacitor C 60 is 24 specific capacitance C0_1, and remaining capacitance size is all specific capacitance C0_1.According to charge conservation theorem, streamline first order MDAC realizes input signal is carried out to the quantification of five, and will remain 8 times of difference amplifications.Coding circuit 1 is encoded the output of the controlled comparator of output.Due to output controlled comparator output be thermometer-code, so the binary code that needs coding circuit 1 to convert it into.First utilize XOR that thermometer-code is converted into single 1 yard, single 1 yard of recycling or goalkeeper are converted into binary code.The coding result of first order streamline MDAC:

Vinp1-Vinn1=Vin1	D16	D15	D14	D13	D12	D11
							Vin1>16/32Vref	1	0	0	0	0	0
16/32Vref>Vin1>15/32Vref	0	1	1	1	1	1
							15/32Vref>Vin1>14/32Vref	0	1	1	1	1	0
14/32Vref>Vin1>13/32Vref	0	1	1	1	0	1
							13/32Vref>Vin1>12/32Vref	0	1	1	1	0	0

12/32Vref>Vin1>11/32Vref	0	1	1	0	1	1
							11/32Vref>Vin1>10/32Vref	0	1	1	0	1	0
10/32Vref>Vin1>9/32Vref	0	1	1	0	0	1
							9/32Vref>Vin1>8/32Vref	0	1	1	0	0	0
8/32Vref>Vin1>7/32Vref	0	1	0	1	1	1
							7/32Vref>Vin1>6/32Vref	0	1	0	1	1	0
6/32Vref>Vin1>5/32Vref	0	1	0	1	0	1
							5/32Vref>Vin1>4/32Vref	0	1	0	1	0	0
4/32Vref>Vin1>3/32Vref	0	1	0	0	1	1
							3/32Vref>Vin1>2/32Vref	0	1	0	0	1	0
2/32Vref>Vin1>1/32Vref	0	1	0	0	0	1
							1/32Vref>Vin1>0/32Vref	0	1	0	0	0	0
0/32Vref>Vin1>-1/32Vref	0	0	1	1	1	1
							-1/32Vref>Vin1>-2/32Vref	0	0	1	1	1	0
-2/32Vref>Vin1>-3/32Vref	0	0	1	1	0	1
							-3/32Vref>Vin1>-4/32Vref	0	0	1	1	0	0
-4/32Vref>Vin1>-5/32Vref	0	0	1	0	1	1
							-5/32Vref>Vin1>-6/32Vref	0	0	1	0	1	0
-6/32Vref>Vin1>-7/32Vref	0	0	1	0	0	1
							-7/32Vref>Vin1>-8/32Vref	0	0	1	0	0	0
-8/32Vref>Vin1>-9/32Vref	0	0	0	1	1	1
							-9/32Vref>Vin1>-10/32Vref	0	0	0	1	1	0
-10/32Vref>Vin1>-11/32Vref	0	0	0	1	0	1
							-11/32Vref>Vin1>-12/32Vref	0	0	0	1	0	0
-12/32Vref>Vin1>-13/32Vref	0	0	0	0	1	1
							-13/32Vref>Vin1>-14/32Vref	0	0	0	0	1	0
-14/32Vref>Vin1>-15/32Vref	0	0	0	0	0	1
							-15/32Vref>Vin1	0	0	0	0	0	0

Under calibration mode of operation, due to the mismatch of electric capacity, make the overall performance that can introduce corresponding error effect ADC at the corresponding levels, so need to calibrate accordingly, when calibration, at the corresponding levels and sampling hold circuit disconnects, and sampling hold circuit is not worked, and input at the corresponding levels is introduced fixing value, and at this moment control signal Vnormal1 is always low, nmos pass transistor M53 turn-offs, control signal Vcorrect1 and clock signal clk1_p homophase, PMOS transistor M52 conducting.During the gain of calibration inter-stage, first input is connected on to reference level Vinp1-Vinn1=-33/64Vref, at this moment export controlled comparator C oc1 to the output of exporting controlled comparator C oc32 be all 0, obtain a corresponding output encoder, just input is connected on reference level Vinp1-Vinn1=-31/64Vref again, obtain another corresponding output encoder, if when inter-stage at the corresponding levels gain is 8 times, the difference of the output code of front and back should be-1/4Vref.When the difference of front and back code has departed from this value, can regulate and control inter-stage gain increase and decrease control signal VCmdac1_gain1_n and to the value of inter-stage gain increase and decrease control signal VCmdac1_gain5_n, realize the increase and decrease adjustment of inter-stage gain, inter-stage gain increase and decrease control signal VCmdac1_gain1_p is increase and decrease control signal VCmdac1_gain1_n anti-of inter-stage gain.The increase and decrease control signal VCmdac1_gain_n of inter-stage gain is high level, and cmos transmission gate T46 and cmos transmission gate T47 conducting increase negative feedback electric capacity, realize reducing of inter-stage gain; The increase and decrease control signal VCmdac1_gain_n of inter-stage gain is low level, and cmos transmission gate T45 and cmos transmission gate T48 conducting, increase corresponding positive feedback, realizes the increase of inter-stage gain.Can regulate and control gain big or small control signal VCmdac1_gain1_n, VCmdac1_gain2_n, VCmdac1_gain3_n, VCmdac1_gain4_n, VCmdac1_gain5_n of inter-stage and realize the change amount of inter-stage gain.The little control signal VCmdac1_gain1_p of inter-stage gain, VCmdac1_gain2_p, VCmdac1_gain3_p, VCmdac1_gain4_p, VCmdac1_gain5_p is respectively the inter-stage big or small control signal VCmdac1_gain1_n that gains, VCmdac1_gain2_n, VCmdac1_gain3_n, VCmdac1_gain4_n, VCmdac1_gain5_n's is anti-, inter-stage gains big or small control signal VCmdac1_gain1_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac1_gain1_n that gains is low level, the size of corresponding inter-stage gain becomes (C60+C61+ ... + C93)/(C93 ± C94).Inter-stage gains big or small control signal VCmdac1_gain2_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac1_gain2_n that gains is low level, and corresponding inter-stage gain size becomes (C60+C61+ ... + C93)/(C93 ± C95).Inter-stage gains big or small control signal VCmdac1_gain3_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac1_gain3_n that gains is low level, and the size of corresponding inter-stage gain becomes (C60+C61+ ... + C93)/(C93 ± C96).Inter-stage gains big or small control signal VCmdac1_gain4_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac1_gain4_n that gains is low level, and corresponding inter-stage gain size becomes (C60+C61+ ... + C93)/(C93 ± C97).Inter-stage gains big or small control signal VCmdac1_gain5_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac1_gain5_n that gains is low level, and corresponding inter-stage gain size becomes (C60+C61+ ... + C93)/(C93 ± C98).By regulation and control inter-stage gain increase and decrease control signal VCmdac1_gain_n, and gain big or small control signal Cmdac1_gain1_n, VCmdac1_gain2_n, VCmdac1_gain3_n, VCmdac1_gain4_n, VCmdac1_gain5_n of inter-stage realizes the calibration of inter-stage gain.When circuit is normally worked, control signal directly adds in circuit according to the value after calibration.When the sub-DAC of calibration, input termination reference level Vinp1-Vinn1=-31/64Vref, the control signal VC1_1 to VC1_31 that controls the controlled comparator of output wherein has one for high, make the output of exporting controlled comparator accordingly be set to 1, other the controlled comparator output of output actual value, the output that can obtain other the controlled comparator of output according to the value of input is all 0.Whether the difference that is set to the output code of 1 front and back by relatively exporting controlled comparator is that 1/4Vref judges the caused mistake of the capacitance mismatch extent that the switch controlled with the controlled comparator of the output that is set to 1 is connected, and eliminates this error by corresponding calibration error memory circuit in regulation and control streamline second level MDAC.Finally, by such method, the output of sub-DAC is calibrated accordingly.When normal work, if controlled comparator is output as 1, in the MDAC of the streamline second level, its corresponding calibration error memory circuit will be added to the error producing when calibrating in the output signal of streamline second level MDAC so.If controlled comparator is output as 0, in the MDAC of the streamline second level, its corresponding calibration error memory circuit will can not be added to the error producing when calibrating in the output signal of streamline second level MDAC so.

Referring to Fig. 4, streamline second level MDAC, adopts the convertible circuit structure of fully differential electric charge, under normal operation, the output of streamline first order MDAC is carried out to the quantification of three, output five-digit number character code, and the residue difference of quantification is amplified 8 times.In the corresponding levels, the quantizing range of comparator has been expanded one times, and the output area of higher level MDAC is from-1/8Vref to 1/8Vref, so the quantizing range of comparator is from-1/8Vref to 1/8Vref, now this scope is expanded to from-1/4Vref to 1/4Vref.This is mainly for eliminating higher level because the residue difference that the threshold value imbalance of comparator produces has surpassed theoretical scope at the corresponding levels, comparison range by expansion comparator just can quantize the value exceeding accordingly like this, and the threshold value of eliminating due to higher level's comparator by suitable coding and figure adjustment departs from produced error.So do the threshold value imbalance of have ± 1/64Vref of the comparator that can make circuit can tolerate higher level.The corresponding levels have also designed corresponding calibration error memory circuit, be mainly used to produce the caused error of capacitance mismatch being connected with the output of each comparator of higher level, and this error is calibrated by the corresponding levels.Higher level has 32 comparators, the comparator that wherein threshold value is 32/64Vref does not carry out corresponding calibration process, in the corresponding levels, need 31 calibration error memory circuits like this, in order to realize the symmetry of circuit, 32 calibration error memory circuits have been designed, respectively 32 calibration error memory circuits are on average accessed to the positive and negative two ends of input, in order to realize same function, the calibration error memory circuit structure that accesses positive and negative two ends is different, what be associated with the positive input terminal of operational amplifier 2 in MDAC is positive calibration error memory circuit, contrary is negative calibration error memory circuit.Transfer function at the corresponding levels can simply be expressed as

Voutp 2 - Voutn 2 = \{\begin{matrix} 8 (Voutp 1 - Voutn 1 + \frac{17 Vref}{64}) - Verr & Voutp 1 - Voutn 1 \leq \frac{- 8}{32} Vref \\ 8 (Voutp 1 - Voutn 1 - \frac{(2 i_{2} - 1) Vref}{64}) - Verr & \frac{(i_{2} - 1)}{32} Vref < Voutp 1 - Voutn 1 \leq \frac{i_{2}}{32} Vref \\ 8 (Voutp 1 - Voutn 1 + \frac{17 Vref}{64}) - Verr & \frac{8}{32} Vref < Voutp 1 - Voutn 1 \end{matrix}

Wherein Voutp2 is anode output at the corresponding levels, Voutn2 is negative terminal output at the corresponding levels, Voutp1 is anode input at the corresponding levels, namely higher level's anode output simultaneously, Voutn1 is negative terminal input at the corresponding levels, namely higher level's negative terminal output simultaneously, the capacitance mismatch caused error amount of Verr for being associated with the controlled comparator of the output that is output as 1 in higher level, this value can just can be born.I ₂for corresponding integer, its scope is-8≤i ₂≤ 8.

Under calibration mode of operation, the corresponding levels and higher level MDAC are disconnected, at this moment higher level MDAC does not work, input access fixed value at the corresponding levels.First still carry out the calibration of inter-stage gain, due to the mismatch of feedback capacity, can make inter-stage gain produce and depart from.Input first accesses fixed value for-19/64Vref is at this moment because the output of comparator is all 0, and at this moment desirable corresponding levels residue difference is-1/8Vref; Input first being accessed to fixed value is-17/64Vref again, and at this moment desirable corresponding levels residue difference is 1/8Vref, so the difference of twice output code in front and back is-1/4Vref.The value connecing due to other electric capacity of twice of front and back does not all have to change, so if the departed from-1/4Vref of difference of the twice residue difference in front and back is mainly to depart from caused by inter-stage gain at the corresponding levels.According to the difference of twice output encoder in front and back, judge that inter-stage gain is greater than 8 times and is still less than 8 times, utilizing inter-stage gain adjust signal to adjust inter-stage yield value, make it to equal 8 times.Carry out again afterwards the calibration of sub-DAC, the output that utilizes adjustment signal that the corresponding levels are exported to a controlled comparator of output in controlled comparator is set to 1, at this moment desirable residue difference at the corresponding levels is-1/8Vref, the output encoder of putting 1 front and back residue difference by relatively exporting controlled comparator judges the caused error of mismatch of electric capacity associated with it, in Bing subordinate, regulate and control corresponding with it calibration error memory circuit, the difference that makes comparator put 1 front and back residue difference is 1/4Vref.This is just stored in subordinate by the caused error of mismatch of putting the electric capacity that 1 comparator is associated.During normal work, when this is exported controlled comparator and is output as 0, the caused error of mismatch of the electric capacity being associated with the controlled comparator of output can not be incorporated in subordinate.On the contrary, when this is exported controlled comparator and is output as 1, the caused error of mismatch of the electric capacity being associated with comparator will be incorporated into the output of subordinate, thereby eliminates this error amount.

Referring to Fig. 4, known in figure, under normal operation, when clock is low level, clock signal clk2_n, clock signal clk2_n1, clock signal clk2_n2 is output as high level, clock clk2_p is low level, at this moment the positive-negative input end of the operational amplifier A in MDAC 2 is shorted together by nmos pass transistor M86, and add input common mode reference voltage Vcom2 by nmos pass transistor M84 and nmos pass transistor M85, positive-negative output end is also shorted together by nmos pass transistor M106, output to the operational amplifier A 2 in MDAC plays a part reset.At this moment the controlled comparator C oc33 of output at the corresponding levels to positive output and the negative output of exporting controlled comparator C oc49 be all 1, anti-and the negative output of positive output be all instead 0, so the switch arrays Sr65 in the corresponding levels to the PMOS transistor being connected with reference voltage Vref in switch arrays Sr98 and the nmos pass transistor that is connected to the ground all in off state, only has the nmos pass transistor conducting being connected with negative input signal with positive input signal, at this moment nmos pass transistor M78 in addition, nmos pass transistor M80, nmos pass transistor M81, nmos pass transistor M87, nmos pass transistor M89, nmos pass transistor M92 and nmos pass transistor M93 conducting, thereby realize capacitor C 159 to the sampling of 196 pairs of input signals of capacitor C.Export controlled comparator C oc33 simultaneously and also realize the sampling to input signal to exporting controlled comparator C oc49.At this moment positive calibration error memory circuit Ep1 stores the controlled comparator C oc1 of the output in first order MDAC to the negative output of exporting controlled comparator C oc16 to positive calibration error memory circuit Ep16, negative calibration error memory circuit En1 stores the controlled comparator C oc17 of the output in first order MDAC to the negative output of exporting controlled comparator C oc31 to negative calibration error memory circuit En15 simultaneously, the output of negative calibration error memory circuit En16 is always fixed value, the output of the extremely positive calibration error memory circuit Ep16 of positive calibration error memory circuit Ep1 and the extremely negative calibration error memory circuit En15 of negative calibration error memory circuit En1 is placed in to corresponding definite value simultaneously, from capacitor C 108 to capacitor C 139 is charged.Capacitor C 140 to capacitor C 155 will be connected with capacitor C 108 to capacitor C 139 respectively, thereby the output of regulating error calibration circuit joins the value of the output of MDAC at the corresponding levels.Nmos pass transistor M104 and nmos pass transistor M105 conducting in addition, one end access input common-mode reference level Vcom2 by cmos transmission gate T55 to cmos transmission gate T62, at this moment control signal VCmdac2_gain1_p and VCmdac2_gain1_n will control conducting or the shutoff of cmos transmission gate T55, cmos transmission gate T62, nmos pass transistor M96 and nmos pass transistor M103, thereby determine one end ground connection when clock is high level of capacitor C 197 and capacitor C 204 or meet input common-mode reference level Vcom2; Control signal VCmdac2_gain2_p and VCmdac2_gain2_n will control conducting or the shutoff of cmos transmission gate T56, cmos transmission gate T62, nmos pass transistor M97 and nmos pass transistor M102, thereby determine one end ground connection when clock is high level of capacitor C 198 and capacitor C 203 or meet input common-mode reference level Vcom2; Control signal VCmdac2_gain3_p and VCmdac2_gain3_n will control conducting or the shutoff of cmos transmission gate T57, cmos transmission gate T60, nmos pass transistor M98 and nmos pass transistor M101, thereby determine one end ground connection when clock is high level of capacitor C 199 and capacitor C 202 or meet input common-mode reference level Vcom2; Control signal VCmdac2_gain4_p and VCmdac2_gain4_n will control conducting or the shutoff of cmos transmission gate T58, cmos transmission gate T59, nmos pass transistor M99 and nmos pass transistor M100, thereby determine one end ground connection when clock is high level of capacitor C 200 and capacitor C 201 or meet input common-mode reference level Vcom2; When clock is high level, clock signal clk2_n, clock signal clk2_n1, clock signal clk2_n2 are output as low level, clk2_p is high level, at this moment the operational amplifier A in MDAC 2 is normally worked, bootstrapped switch S7 and bootstrapped switch S8 export effective control signal, make the bottom crown of capacitor C 156 and capacitor C 196 access respectively the positive-negative output end of the operational amplifier A 2 in MDAC.Switch arrays Sr65 will be decided to the output of exporting controlled comparator C oc49 by the controlled comparator C oc33 of output to the output of switch arrays Sr98.Export controlled comparator and exported accordingly according to the size of comparator input signal and threshold value, the threshold value of the comparator in the MDAC of the streamline second level is respectively: 8/32Vref, 7/32Vref, 6/32Vref, 5/32Vref, 4/32Vref, 3/32Vref, 2/32Vref, 1/32Vref, 0/32Vref ,-1/32Vref ,-2/32Vref ,-3/32Vref ,-4/32Vref ,-5/32Vref ,-6/32Vref ,-7/32Vref ,-8/32Vref.At this moment PMOS transistor M79, nmos pass transistor M82, PMOS transistor M83 and PMOS transistor M88 conducting in addition, at this moment control signal Vcorrect2 is always low level, and nmos pass transistor M91 is turn-offed; Control signal VSamp2 and clock signal clk2_n homophase, PMOS transistor M90 conducting.Thereby realize the charging again to capacitor C 195 to capacitor C 157.The extremely negative calibration error memory circuit En15 of the extremely positive calibration error memory circuit Ep16 of simultaneously positive calibration error memory circuit Ep1 and negative calibration error memory circuit En1 exports the fixed value that controlled comparator C oc1 determines to the negative output of exporting controlled comparator C oc31 by output in streamline first order MDAC, realization is the charging again to capacitor C 139 to capacitor C 108, thereby the error of streamline first order MDAC neutron DAC can be joined in output signal at the corresponding levels.Capacitor C 156 is identical to the total capacitance size of capacitor C 196 these 21 electric capacity with C176 to the total capacitance size of capacitor C 175 these 20 electric capacity, be all 64 specific capacitance C0_2, wherein the size of capacitor C 156 and capacitor C 196 is all 8 specific capacitance C0_2, the size of capacitor C 175 and capacitor C 176 is all 20 specific capacitance C0_2, the size of capacitor C 177 is 16 specific capacitance C0_2, the size of capacitor C 174 is 17 specific capacitance C0_2, and remaining capacitance size is all specific capacitance C0_2.Capacitor C 108 is large equally to capacitor C 155 these 48 electric capacity, is all C0_2.According to charge conservation theorem, streamline second level MDAC realizes input signal is carried out to the quantification of three, and will remain 8 times of difference amplifications.Coding circuit 2 is encoded the output of the controlled comparator of output.Due to output controlled comparator output be thermometer-code, so the binary code that needs coding circuit 2 to convert it into.First utilize XOR that thermometer-code is converted into single 1 yard, single 1 yard of recycling or goalkeeper are converted into binary code.The coding result of second level streamline MDAC:

Vinp2-Vinn2=Vin2	D25	D24	D23	D22	D21
						Vin2>8/32Vref	0	1	1	0	0
8/32Vref>Vin2>7/32Vref	0	1	0	1	1
						7/32Vref>Vin2>6/32Vref	0	1	0	1	0
6/32Vref>Vin2>5/32Vref	0	1	0	0	1
						5/32Vref>Vin2>4/32Vref	0	1	0	0	0
4/32Vref>Vin2>3/32Vref	0	0	1	1	1
						3/32Vref>Vin2>2/32Vref	0	0	1	1	0
2/32Vref>Vin2>1/32Vref	0	0	1	0	1
						1/32Vref>Vin2>0/32Vref	0	0	1	0	0
0/32Vref>Vin2>-1/32Vref	0	0	0	1	1
						-1/32Vref>Vin2>-2/32Vref	0	0	0	1	0
-2/32Vref>Vin2>-3/32Vref	0	0	0	0	1
						-3/32Vref>Vin2>-4/32Vref	0	0	0	0	0
-4/32Vref>Vin2>-5/32Vref	1	1	1	1	1
						-5/32Vref>Vin2>-6/32Vref	1	1	1	1	0
-6/32Vref>Vin2>-7/32Vref	1	1	1	0	1
						-7/32Vref>Vin2>-8/32Vref	1	1	1	0	0
-8/32Vref>Vin2	1	1	0	1	1

Under calibration mode of operation, the corresponding levels and higher level MDAC are disconnected, at this moment higher level MDAC does not work, input access fixed value at the corresponding levels.At this moment control signal Vcorrect2 and clock signal clk2_p homophase, make nmos pass transistor M91 conducting when signal is high level all the time; Control signal Vnormal2 is always high level, and PMOS transistor M90 is turn-offed all the time.First carry out the calibration of inter-stage gain, first input is connected on to reference level Vinp2-Vinn2=-19/64Vref, at this moment the output Coc33 of controlled comparator to the output of the output Coc49 of controlled comparator be all 0, obtain a corresponding output encoder, just input is connected on reference level Vinp1-Vinn1=-17/64Vref again, obtains another corresponding output encoder.When inter-stage at the corresponding levels gain is 8 times, the difference of the output code of front and back should be-1/4Vref.When the difference of front and back code has departed from this value, can regulate and control inter-stage gain increase and decrease control signal VCmdac2_gain1_n and to the value of inter-stage gain increase and decrease control signal VCmdac2_gain4_n, realize the increase and decrease adjustment of inter-stage gain, inter-stage gain increase and decrease control signal VCmdac2_gain1_p is the anti-of inter-stage gain increase and decrease control signal VCmdac2_gain1_n.Inter-stage gain increase and decrease control signal VCmdac2_gain_n is high level, makes cmos transmission gate T64 and cmos transmission gate T65 conducting, and negative feedback electric capacity is increased, and realizes reducing of inter-stage gain; Inter-stage gain increase and decrease control signal VCmdac2_gain_n is low level, makes cmos transmission gate T63 and cmos transmission gate T66 conducting, and positive feedback electric capacity is increased, and realizes the increase of inter-stage gain.Can regulate and control gain big or small control signal VCmdac2_gain1_n, VCmdac2_gain2_n, VCmdac2_gain3_n, VCmdac2_gain4_n of inter-stage and realize the change amount of inter-stage gain.Gain big or small control signal VCmdac2_gain1_p, VCmdac2_gain2_p, VCmdac2_gain3_p, VCmdac2_gain4_p of inter-stage is respectively inter-stage the anti-of big or small control signal VCmdac2_gain1_n, VCmdac2_gain2_n, VCmdac2_gain3_n, VCmdac2_gain4_n of gaining.Inter-stage gains big or small control signal VCmdac2_gain1_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac2_gain1_n that gains is low level, and the size of corresponding inter-stage gain becomes (C176+C177+ ... + C196)/(C196 ± C197).Inter-stage gains big or small control signal VCmdac2_gain2_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac2_gain2_n that gains is low level, and the size of corresponding inter-stage gain becomes (C176+C177+ ... + C196)/(C196 ± C198).Inter-stage gains big or small control signal VCmdac2_gain3_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac2_gain3_n that gains is low level, and the size of corresponding inter-stage gain becomes (C176+C177+ ... + C196)/(C196 ± C199).Inter-stage gains big or small control signal VCmdac2_gain4_n while being high level, do not affect the size of inter-stage gain, the inter-stage big or small control signal VCmdac2_gain4_n that gains is low level, and the size of corresponding inter-stage gain becomes (C176+C177+ ... + C196)/(C196 ± C200).By regulation and control inter-stage gain increase and decrease control signal VCmdac2_gain_n, and gain big or small control signal Cmdac2_gain1_n, VCmdac2_gain2_n, VCmdac2_gain3_n, VCmdac2_gain4_n of inter-stage realizes the calibration of inter-stage gain.When circuit is normally worked, control signal directly adds in circuit according to the value after calibration.When the sub-DAC of calibration, input termination reference level Vinp1-Vinn1=-31/64Vref, to VC2_17, one of them is high level to the control signal VC2_1 of the controlled comparator of control output, make the output of exporting controlled comparator accordingly be set to 1, other the controlled comparator output of output actual value, the output that can obtain other the controlled comparator of output according to the value of input is all 0.Whether the difference that is set to the output code of 1 front and back by relatively exporting controlled comparator is that 1/4Vref judges the caused mistake of the capacitance mismatch extent that the switch controlled with the controlled comparator of the output that is set to 1 is connected, and eliminates this error by corresponding calibration error memory circuit in regulation and control streamline third level MDAC.Finally, by such method, the output of sub-DAC is calibrated accordingly.When normal work, if controlled comparator is output as 1, in streamline third level MDAC, its corresponding calibration error memory circuit will be added to the error producing when calibrating in the output signal of streamline third level MDAC so.If controlled comparator is output as 0, in streamline third level MDAC, its corresponding calibration error memory circuit will can not be added to the error producing when calibrating in the output signal of streamline third level MDAC so.

Referring to Fig. 5, streamline third level MDAC, adopts the convertible circuit structure of fully differential electric charge, under normal operation, the output of streamline second level MDAC is carried out to the quantification of three, output five-digit number character code, then the residue difference of quantification is carried out to the amplification of 8 times.Equally by one times of the quantizing range expansion of comparator in the corresponding levels.From original-1/8Vref to 1/8Vref, expand to present-1/4Vref to 1/4Vref.This is mainly the imbalance due to the threshold value of higher level's comparator for elimination, causes higher level's Output rusults to surpass the caused error of quantized interval at the corresponding levels.After quantizing range at the corresponding levels having been carried out to expansion here, make higher level's output obtain suitable coding, finally in digital correction circuit, obtain correct result.So so do the threshold value imbalance of have ± 1/64Vref of the comparator that can make circuit can tolerate higher level.In the corresponding levels, add in addition corresponding calibration error memory circuit to eliminate the error of higher level's neutron DAC.Transfer function expression formula at the corresponding levels:

Voutp 3 - Voutn 3 = \{\begin{matrix} 8 (Voutp 2 - Voutn 2 + \frac{17 Vref}{64}) - Verr 1 & Voutp 2 - Voutn 2 \leq \frac{- 8}{32} Vref \\ 8 (Voutp 2 - Voutn 2 - \frac{(2 i_{3} - 1) Vref}{64}) - Verr 1 & \frac{(i_{3} - 1)}{32} Vref < Voutp 2 - Voutn 2 \leq \frac{i_{3}}{32} Vref \\ 8 (Voutp 2 - Voutn 2 + \frac{17 Vref}{64}) - Verr 1 & \frac{8}{32} Vref < Voutp 2 - Voutn 2 \end{matrix}

Wherein, Voutp3 is anode output at the corresponding levels, Voutn3 is negative terminal output at the corresponding levels, Voutp2 is anode input at the corresponding levels, namely higher level's anode output simultaneously, Voutn2 is negative terminal input at the corresponding levels, simultaneously namely higher level's negative terminal output, the capacitance mismatch caused error amount of Verr1 for being associated with the controlled comparator of the output that is output as 1 in higher level, this value can just can be born.I3 is corresponding integer, and its scope is-8≤i ₃≤ 8.

Because the output of residue difference at the corresponding levels only need to reach the required precision of 7, the mismatch of electric capacity can meet this precision, so at the corresponding levels with regard to the requirement of not calibrating.

Referring to Fig. 5, in figure during known circuit working, when clock is high level, clock signal clk3_p, clock signal clk3_p1, clock signal clk3_p2 and clock signal clk3_p3 are high level, and clock signal clk3_n and clock signal clk3_n3 are low level.At this moment the positive-negative input end of the operational amplifier A in MDAC 3 is shorted together by nmos pass transistor M124, and add input common mode reference voltage Vcom3 by nmos pass transistor M122 and nmos pass transistor M123, positive-negative output end is shorted together by nmos pass transistor M128, and the output of the operational amplifier A 3 in MDAC is played a part to reset.At this moment comparator C om1 at the corresponding levels to positive output and the negative output of exporting controlled comparator C om17 be all 1, anti-and the negative output of positive output be all instead 0, so the switch arrays Sr99 in the corresponding levels to the PMOS transistor being connected with reference voltage Vref in switch arrays Sr118 and the nmos pass transistor that is connected to the ground all in off state, only has the nmos pass transistor conducting being connected with negative input signal with positive input signal, at this moment nmos pass transistor M113 in addition, nmos pass transistor M114, nmos pass transistor M116, nmos pass transistor M118, nmos pass transistor M199, nmos pass transistor M125 conducting, thereby realize capacitor C 239 to the sampling of 264 pairs of input signals of capacitor C.Simultaneously comparator C om1 also realizes the sampling to input signal to comparator C om17.At this moment positive calibration error memory circuit Ep17 stores the controlled comparator C oc33 of the output in the MDAC of the second level to the negative output of exporting controlled comparator C oc41 to positive calibration error memory circuit Ep25, negative calibration error memory circuit En17 stores the controlled comparator C oc42 of the output in the MDAC of the second level to the negative output of exporting controlled comparator C oc49 to negative calibration error memory circuit En24 simultaneously, in order to mate the positive-negative input end of third level MDAC, need to add PMOS transistor M107, nmos pass transistor M108, PMOS transistor M109, nmos pass transistor M110, PMOS transistor M111 and nmos pass transistor M112.The output of the extremely positive calibration error memory circuit Ep25 of positive calibration error memory circuit Ep17 and the extremely negative calibration error memory circuit En24 of negative calibration error memory circuit En17 is placed in to corresponding definite value simultaneously, PMOS transistor 107, PMOS transistor M109 and PMOS transistor M111 conducting, from charging to capacitor C 209 to capacitor C 228.Capacitor C 229 to capacitor C 238 will be connected with capacitor C 209 to capacitor C 228 respectively, thereby the output of regulating error calibration circuit joins the value of the output of MDAC at the corresponding levels.At this moment the output of coding circuit E3 is 0 entirely.When clock is low level, clock signal clk3_p, clk3_p1, clk3_p2 and clk3_p3 are low level, clock signal clk3_n and clk3_n3 are high level, at this moment the operational amplifier A in MDAC 3 is normally worked, bootstrapped switch S9 and bootstrapped switch S10 export effective control signal, make the bottom crown of capacitor C 239 and capacitor C 264 access respectively the positive-negative output end of the operational amplifier A 3 in MDAC.Switch arrays Sr99 will be decided to the output of comparator C om17 by comparator C om1 to the output of switch arrays Sr118.Comparator is exported accordingly according to the size of comparator input signal and threshold value, and the threshold value of the comparator in streamline third level MDAC is respectively: 8/32Vref, 7/32Vref, 6/32Vref, 5/32Vref, 4/32Vref, 3/32Vref, 2/32Vref, 1/32Vref, 0/32Vref ,-1/32Vref ,-2/32Vref ,-3/32Vref ,-4/32Vref ,-5/32Vref ,-6/32Vref ,-7/32Vref ,-8/32Vref.At this moment PMOS transistor M115, nmos pass transistor M117, PMOS transistor M120 and PMOS transistor M121 conducting in addition.Thereby realize the charging again to capacitor C 263 to capacitor C 240.The extremely negative calibration error memory circuit En24 of the extremely positive calibration error memory circuit Ep25 of simultaneously positive calibration error memory circuit Ep17 and negative calibration error memory circuit En17 exports the fixed value that controlled comparator C oc33 determines to the negative output of exporting controlled comparator C oc49 by output in the MDAC of the streamline second level, realization is the charging again to capacitor C 127 to capacitor C 112, thereby the error of streamline second level MDAC neutron DAC can be joined in output signal at the corresponding levels.Capacitor C 239 is identical to the total capacitance size of capacitor C 264 these 13 electric capacity with C252 to the total capacitance size of capacitor C 251 these 13 electric capacity, be all 32 specific capacitance C0_3, wherein the size of capacitor C 239 and capacitor C 264 is all 4 specific capacitance C0_3, the size of capacitor C 250 and capacitor C 253 is all 6 specific capacitance C0_3, the size of capacitor C 251 and capacitor C 252 is 12 specific capacitance C0_3, and remaining capacitance size is all specific capacitance C0_3.Capacitor C 209 is large equally to capacitor C 238 these 30 electric capacity, is all C0_3.According to charge conservation theorem, streamline third level MDAC realizes input signal is carried out to the quantification of three, and will remain 8 times of difference amplifications.Coding circuit 3 is encoded the output of comparator.Due to the output of comparator be thermometer-code, so the binary code that needs coding circuit 3 to convert it into.First utilize XOR that thermometer-code is converted into single 1 yard, single 1 yard of recycling or goalkeeper are converted into binary code.The coding result of third level streamline MDAC:

Vinp3-Vinn3=Vin3	D35	D34	D33	D32	D31
						Vin3>8/32Vref	0	1	1	0	0
8/32Vref>Vin3>7/32Vref	0	1	0	1	1
						7/32Vref>Vin3>6/32Vref	0	1	0	1	0
6/32Vref>Vin3>5/32Vref	0	1	0	0	1
						5/32Vref>Vin3>4/32Vref	0	1	0	0	0
4/32Vref>Vin3>3/32Vref	0	0	1	1	1
						3/32Vref>Vin3>2/32Vref	0	0	1	1	0
2/32Vref>Vin3>1/32Vref	0	0	1	0	1
						1/32Vref>Vin3>0/32Vref	0	0	1	0	0
0/32Vref>Vin3>-1/32Vref	0	0	0	1	1
						-1/32Vref>Vin3>-2/32Vref	0	0	0	1	0
-2/32Vref>Vin3>-3/32Vref	0	0	0	0	1
						-3/32Vref>Vin3>-4/32Vref	0	0	0	0	0
-4/32Vref>Vin3>-5/32Vref	1	1	1	1	1
						-5/32Vref>Vin3>-6/32Vref	1	1	1	1	0
-6/32Vref>Vin3>-7/32Vref	1	1	1	0	1
						-7/32Vref>Vin3>-8/32Vref	1	1	1	0	0
-8/32Vref>Vin3	1	1	0	1	1

Referring to Fig. 6, streamline fourth stage MDAC, adopts the convertible circuit structure of fully differential electric charge, and the corresponding levels are carried out the quantification of three to the output of higher level MDAC, output five-digit number character code, and the difference of quantification is carried out to 8 times of amplifications.Equally by one times of the quantizing range expansion of comparator at the corresponding levels.From original-1/8Vref to 1/8Vref, expand to present-1/4Vref to 1/4Vref.This is mainly the imbalance due to the threshold value of higher level's comparator for elimination, causes higher level's Output rusults to surpass the caused error of quantized interval at the corresponding levels.After quantizing range at the corresponding levels having been carried out to expansion here, make higher level's output obtain suitable coding, finally in digital correction circuit, obtain correct result.So so do the threshold value imbalance of have ± 1/64Vref of the comparator that can make circuit can tolerate higher level.The expression formula of transfer function at the corresponding levels:

Voutp 4 - Voutn 4 = \{\begin{matrix} 8 (Voutp 3 - Voutn 3 + \frac{17 Vref}{64}) & Voutp 3 - Voutn 3 \leq \frac{- 8}{32} Vref \\ 8 (Voutp 3 - Voutn 3 - \frac{(2 i_{4} - 1) Vref}{64}) & \frac{(i_{4} - 1)}{32} Vref < Voutp 3 - Voutn 3 \leq \frac{i_{4}}{32} Vref \\ 8 (Voutp 3 - Voutn 3 + \frac{17 Vref}{64}) & \frac{8}{32} Vref < Voutp 3 - Voutn 3 \end{matrix}

Wherein, Voutp4 is anode output at the corresponding levels, and Voutn4 is negative terminal output at the corresponding levels, Voutp3 is anode input at the corresponding levels, namely higher level's anode output simultaneously, and Voutn3 is negative terminal input at the corresponding levels, namely higher level's negative terminal output simultaneously, i4 is corresponding integer, its scope is-8≤i ₄≤ 8.

Referring to Fig. 6, known in figure, during circuit working, when clock is low level, clock signal clk4_n, clock signal clk4_n1, clock signal clk4_n2 and clock signal clk4_n3 are high level, and clock signal clk4_p and clock signal clk4_p3 are low level.At this moment the positive-negative input end of the operational amplifier A in MDAC 4 is shorted together by nmos pass transistor M144, and add input common mode reference voltage Vcom4 by nmos pass transistor M142 and nmos pass transistor M143, positive-negative output end is shorted together by nmos pass transistor M152, and the output of the operational amplifier A 4 in MDAC is played a part to reset.At this moment comparator C om18 at the corresponding levels to positive output and the negative output of exporting controlled comparator C om34 be all 1, anti-and the negative output of positive output be all instead 0, so the switch arrays Sr119 in the corresponding levels to the PMOS transistor being connected with reference voltage Vref in switch arrays Sr138 and the nmos pass transistor that is connected to the ground all in off state, only has the nmos pass transistor conducting being connected with negative input signal with positive input signal, at this moment nmos pass transistor M135 in addition, nmos pass transistor M136, nmos pass transistor M138, nmos pass transistor M140, nmos pass transistor M145, nmos pass transistor M147 conducting, thereby realize capacitor C 273 to the sampling of 298 pairs of input signals of capacitor C.At this moment the output of coding circuit E4 is 0 entirely.When clock is high level, clock signal clk4_n, clock signal clk4_n1, clock signal clk4_n2 and clock signal clk4_n3 are low level, clock signal clk4_p and clock signal clk4_p3 are high level, at this moment the operational amplifier A in MDAC 4 is normally worked, nmos pass transistor M148, nmos pass transistor M50 and PMOS transistor M149, PMOS transistor M151 conducting, make the bottom crown of capacitor C 273 and capacitor C 298 access respectively the positive-negative output end of the operational amplifier A 4 in MDAC.Switch arrays Sr119 will be decided to the output of comparator C mo34 by comparator C om18 to the output of switch arrays Sr138.Comparator is exported accordingly according to the size of comparator input signal and threshold value, and the threshold value of the comparator in streamline fourth stage MDAC is respectively: 8/32Vref, 7/32Vref, 6/32Vref, 5/32Vref, 4/32Vref, 3/32Vref, 2/32Vref, 1/32Vref, 0/32Vref ,-1/32Vref ,-2/32Vref ,-3/32Vref ,-4/32Vref ,-5/32Vref ,-6/32Vref ,-7/32Vref ,-8/32Vref.At this moment PMOS transistor M137, nmos pass transistor M139, PMOS transistor M141 and PMOS transistor M146 conducting in addition.Thereby realize the charging again to capacitor C 294 to capacitor C 274.Capacitor C 273 is identical to the total capacitance size of capacitor C 298 these 13 electric capacity with C286 to the total capacitance size of capacitor C 285 these 13 electric capacity, be all 32 specific capacitance C0_4, wherein the size of capacitor C 273 and capacitor C 285 is all 4 specific capacitance C0_4, the size of capacitor C 284 and capacitor C 287 is all 6 specific capacitance C0_4, the size of capacitor C 285 and capacitor C 286 is 12 specific capacitance C0_4, and remaining capacitance size is all specific capacitance C0_4.According to charge conservation theorem, streamline fourth stage MDAC realizes input signal is carried out to the quantification of three, and will remain 8 times of difference amplifications.Coding circuit 4 is encoded the output of comparator.Due to the output of comparator be thermometer-code, so the binary code that needs coding circuit 4 to convert it into.First utilize XOR that thermometer-code is converted into single 1 yard, single 1 yard of recycling or goalkeeper are converted into binary code.The coding result of fourth stage streamline MDAC:

Vinp4-Vinn4=Vin4	D45	D44	D43	D42	D41
						Vin4>8/32Vref	0	1	1	0	0
8/32Vref>Vin4>7/32Vref	0	1	0	1	1
						7/32Vref>Vin4>6/32Vref	0	1	0	1	0
6/32Vref>Vin4>5/32Vref	0	1	0	0	1
						5/32Vref>Vin4>4/32Vref	0	1	0	0	0
4/32Vref>Vin4>3/32Vref	0	0	1	1	1
						3/32Vref>Vin4>2/32Vref	0	0	1	1	0
2/32Vref>Vin4>1/32Vref	0	0	1	0	1
						1/32Vref>Vin4>0/32Vref	0	0	1	0	0
0/32Vref>Vin4>-1/32Vref	0	0	0	1	1
						-1/32Vref>Vin4>-2/32Vref	0	0	0	1	0
-2/32Vref>Vin4>-3/32Vref	0	0	0	0	1
						-3/32Vref>Vin4>-4/32Vref	0	0	0	0	0
-4/32Vref>Vin4>-5/32Vref	1	1	1	1	1
						-5/32Vref>Vin4>-6/32Vref	1	1	1	1	0
-6/32Vref>Vin4>-7/32Vref	1	1	1	0	1
						-7/32Vref>Vin4>-8/32Vref	1	1	1	0	0
-8/32Vref>Vin4	1	1	0	1	1

Referring to Fig. 7, streamline level V quick flashing ADC, carries out the quantification of two by the output of streamline fourth stage MDAC, output four-digit number code, same by expand to from original-1/8Vref to 1/8Vref-6/32Vref of the quantizing range of comparator to 6/32Vref.This is mainly the imbalance due to the threshold value of higher level's comparator for elimination, causes higher level's Output rusults to surpass the caused error of quantized interval at the corresponding levels.After quantizing range at the corresponding levels having been carried out to expansion here, make higher level's output obtain suitable coding, finally in digital correction circuit, obtain correct result.So so do the threshold value imbalance of have ± 1/64Vref of the comparator that can make circuit can tolerate higher level.

Referring to Fig. 7, known in figure, during circuit working, when clock is high level, comparator C om35 samples to input signal to comparator C om41, and at this moment comparator C om35 is 1 to positive output and the negative output of comparator C om41, the anti-and negative output of positive output be all instead 0.The output of coding circuit E5 is 0 entirely.When clock is low level, comparator is exported accordingly according to the size of comparator input signal and threshold value.The threshold value of comparator at the corresponding levels is respectively: 3/16Vref, 2/16Vref, 1/16Vref, 0/16Vref ,-1/16Vref ,-2/16Vref ,-3/16Vref.Coding circuit 5 is encoded the output of comparator.Because comparator is output as thermometer-code, so the binary code that needs coding circuit E5 to convert it into.First utilize XOR that thermometer-code is converted into single 1 yard, single 1 yard of recycling or goalkeeper are converted into binary code.The coding result of level V streamline quick flashing ADC:

Vinp5–Vinn5=Vin5	D54	D53	D52	D51
					Vin5>3/16Vref	0	1	0	1
3/16Vref>Vin5>2/16Vref	0	1	0	0
					2/16Vref>Vin5>1/16Vref	0	0	1	1
1/16Vref>Vin5>0/16Vref	0	0	1	0
					0/16Vref>Vin5>-1/16Vref	0	0	0	1
-1/16Vref>Vin5>-2/16Vref	0	0	0	0
					-2/16Vref>Vin5>-3/16Vref	1	1	1	1
-3/16Vref>Vin5	1	1	1	0

Referring to Fig. 8, digital correction circuit, because the multiplication factor of the residue difference of streamline first order MDAC has been compressed 4 times, the input quantized interval of streamline second level MDAC, streamline the 3rd utmost point MDAC, the 4th grade of MDAC of streamline and streamline level V quick flashing ADC is all expanded accordingly.Process is like this in order to make in the threshold value imbalance of comparator within the scope of ± 1/64Vref, not affect the performance of ADC.So the coding of every grade will produce according to the input value of every grade corresponding output code.The random value adding in sampling hold circuit in addition also need to deduct in Output rusults.So the random value adding in the output code of every grade and sampling hold circuit need to be carried out to corresponding logic plus and minus calculation, obtain final 16 the correct output binary codes of ADC.

Referring to Fig. 8, known in figure, digital correction circuit, output code D52 and the D51 of streamline level V quick flashing ADC are directly exported, the output code D53 of streamline level V quick flashing ADC is added the output code D41 with streamline fourth stage MDAC, and the output code D42 of the streamline fourth stage will subtract each other with the output code D54 of streamline level V quick flashing ADC.The principle of makeing is like this in streamline fourth stage MDAC, to have the threshold value deviation theory value of a comparator, other is all in normal situation, if threshold value is bigger than normal, when input value be and Threshold and actual threshold between time, the output signal of streamline fourth stage MDAC will be higher than 1/8Vref, its output encoder is little by 1 during than Threshold, the output code D52 of streamline level V quick flashing ADC is the same with Threshold with D51, and the output code D53 of streamline level V quick flashing ADC is 1, need to add in the output code D41 of streamline fourth stage MDAC, make final threshold value coding result bigger than normal the same with the result of Threshold coding.If threshold value is less than normal, when input value be and Threshold and actual threshold between time, the output signal of streamline fourth stage MDAC will be lower than-1/8Vref, its output encoder is during than Threshold large 1, the output code D52 of streamline level V quick flashing ADC is the same with Threshold with D51, and the output code D53 of streamline level V quick flashing ADC is 1, need to join in the output code D41 of streamline fourth stage MDAC, the output code D54 of streamline level V quick flashing ADC is 1, need to from the output code D42 of streamline fourth stage MDAC, deduct, it is actual is that the output code D41 of streamline fourth stage MDAC is subtracted to 1, make final threshold value coding result less than normal the same with the result of Threshold coding.In like manner, the output code D31 of streamline third level MDAC need to add the output code D44 of streamline fourth stage MDAC, and the output code D32 of streamline third level MDAC need to deduct the output code D45 of streamline fourth stage MDAC; The output code D21 of streamline second level MDAC need to add the output code D34 of streamline third level MDAC, the output code D22 of streamline second level MDAC need to deduct the output code D35 of streamline third level MDAC, the output code D11 of streamline first order MDAC need to add the output code D24 of streamline second level MDAC, and the output code D12 of streamline first order MDAC need to deduct the output code D25 of streamline second level MDAC.Need in addition to deduct the random signal control signal dith1_n, dith2_n, dith3_n, dith4_n, dith5_n, the dith6_n that add sampling hold circuit output signal, finally obtain 16 binary codings of actual input value.When input is during higher than maximum positive input value, it is 1 that input signal overflows quantizing range index signal OF, and other 16 outputs are 1 entirely, when input is during lower than minimum negative input value, input signal overflows quantizing range index signal OF and is similarly 1, other 16 for output be 0 entirely.When input signal is positioned at normal quantizing range, it is 0 that input signal overflows quantizing range index signal OF.

From said structure, when normal work, when clock signal is low level, sampling hold circuit is sampled to input signal; When clock is high level, streamline first order MDAC samples to the output of sampling hold circuit, and this value of also simultaneously sampling of the comparator in streamline first order MDAC.When clock is low level again, the output valve that the controlled comparator of output of streamline first order MDAC produces will be controlled the output of sub-DAC, and will quantize 8 times of outputs of residue difference amplification, streamline second level MDAC this output valve of sampling realizes the coding of the corresponding levels being exported to the output valve of controlled comparator simultaneously.Equally, streamline second level MDAC is when clock is high level, export the output valve of controlled comparator generation and will control the output of sub-DAC, and will quantize 8 times of outputs of residue difference amplification, streamline third level MDAC this output valve of sampling completes the coding of the corresponding levels being exported to the output valve of controlled comparator simultaneously.Streamline third level MDAC is identical with the sequential of the streamline first order with streamline level V quick flashing ADC.Streamline fourth stage MDAC is identical with the sequential of streamline second level MDAC.

Referring to Fig. 9, known in figure, this positive calibration error memory circuit comprises: cmos transmission gate T70, cmos transmission gate T71, reverser I1, reverser I2, reverser I3, reverser I4, NAND gate Nand1, with or door Sor1, current regulating circuit Ic1, resistance R 1, resistance R 2, nmos pass transistor M155, nmos pass transistor M156.When calibration, first, clock signal clk6_p is low level, clk6_n is high level, the output of NAND gate Nand1 is always 1, when the positive and negative control signal Vcdac_updown_1 of calibration error is while being high, with or door be output as 1, at this moment nmos pass transistor M156 conducting, the output of calibration error memory circuit is the voltage of transistor M156 drain electrode.Clock signal clk6_p is high level afterwards, clock signal clk6_n is low level, when input signal Vin_cn is low, namely the negative output of corresponding comparator is 0, at this moment NAND gate Nand1 is output as 0, a same or door Sor1 is output as 0, at this moment nmos pass transistor M155 conducting, and the output of calibration error memory circuit is the voltage of transistor M155 drain electrode.If this calibration error memory circuit is relevant to the positive input terminal of operational amplifier in corresponding MDAC, positive calibration error memory circuit namely will will deduct an error amount so in the output signal of MDAC accordingly.The large young pathbreaker of this error signal is adjusted signal Vcdac_c1_4 and is decided by 1 times of reference current adjustment signal Vcdac_c1_1,2 times of reference current adjustment signal Vcdac_c1_2,4 times of reference current adjustment signal Vcdac_c1_3,8 times of reference currents.When the positive and negative control signal Vcdac_updown_1 of calibration error is while being low, will in the output signal of corresponding MDAC, will increase an error amount so.When if input signal Vin_cn is high, the output of calibration error memory circuit is not changed by low level at clock signal clk6_p in high level changes, so calibration error memory circuit does not exert an influence to the output signal of corresponding MDAC.Always indicate when making the positive and negative control signal Vcdac_updown_1 of calibration error be high in the output signal of corresponding MDAC and will deduct an error amount.When calibration error memory circuit is relevant to the negative input end of operational amplifier in corresponding MDAC, namely bear calibration error memory circuit, the nmos pass transistor M155 in calibration error memory circuit and the gate signal of nmos pass transistor M156 will exchange down.

When normal work, adjustment signal in calibration error memory circuit, the positive and negative control signal Vcdac_updown_1 of calibration error, 1 times of reference current are adjusted signal Vcdac_c1_1,2 times of reference currents and are adjusted that signal Vcdac_c1_2,4 times of reference currents adjust signal Vcdac_c1_3,8 times of reference currents are adjusted signal Vcdac_c1_4, and the value when according to calibration is written in circuit.Thereby realize the calibration because of the caused error of mismatch of electric capacity.

The above is the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, do not departing under the prerequisite of principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims

1. 16 flow-line modulus converters, is characterized in that, comprising:

2. analog to digital converter according to claim 1, is characterized in that, described preposition sampling hold circuit comprises: the first operational amplifier (Ash1), the first, second, third and the 4th bootstrapped switch, transmission gate and electric capacity;

3. analog to digital converter according to claim 1, is characterized in that, described streamline first order long number digital to analog converter comprises: the second operational amplifier (A1), 10 transmission gates, 64 switch arrays, electric capacity and 32 controlled comparators of output;

4. analog to digital converter according to claim 3, is characterized in that, described streamline first order long number digital to analog converter also comprises:

Coding circuit, for encoding the output of the controlled comparator of output.

5. analog to digital converter according to claim 1, is characterized in that, described streamline second level long number digital to analog converter comprises: the 3rd operational amplifier (A2), 8 transmission gates, 32 switch arrays, electric capacity and 16 controlled comparators of output;

6. analog to digital converter according to claim 5, is characterized in that, described streamline second level long number digital to analog converter also comprises:

7. analog to digital converter according to claim 1, is characterized in that, described streamline third level long number digital to analog converter comprises: the 3rd operational amplifier (A3), 18 switch arrays, electric capacity and 17 controlled comparators of output;

8. analog to digital converter according to claim 7, is characterized in that, described streamline third level long number digital to analog converter also comprises:

9. analog to digital converter according to claim 8, is characterized in that, described streamline third level long number digital to analog converter also comprises: a coding circuit (E3), and for the output of the controlled comparator of output is encoded.

10. analog to digital converter according to claim 1, is characterized in that, described streamline fourth stage long number digital to analog converter comprises: four-operational amplifier (A4), 20 switch arrays, electric capacity and 16 controlled comparators of output;

11. analog to digital converters according to claim 10, is characterized in that, described streamline fourth stage long number digital to analog converter also comprises: coding circuit 4, and for the output of the controlled comparator of output is encoded.

12. analog to digital converters according to claim 1, is characterized in that, described level V quick flashing analog to digital converter comprises:

7 comparators, for sampling to input signal.

13. analog to digital converters according to claim 12, is characterized in that, described level V quick flashing analog to digital converter also comprises: coding circuit E5, and for the output of comparator is encoded.

14. according to the analog to digital converter described in claim 6 or 8, it is characterized in that, described positive calibration error memory circuit comprises: