WO2017091928A1

WO2017091928A1 - High-speed pipelined successive approximation adc based on dynamic ringing-based operational amplifier

Info

Publication number: WO2017091928A1
Application number: PCT/CN2015/095926
Authority: WO
Inventors: 任俊彦; 陈勇臻; 王晶晶; 朱凯; 叶凡
Original assignee: 复旦大学
Priority date: 2015-11-30
Filing date: 2015-11-30
Publication date: 2017-06-08

Abstract

A high-speed pipelined successive approximation ADC based on a dynamic ringing-based operational amplifier comprises: a pipelined quantization front end (301), configured to realize quantization of higher-order bits in the ADC, wherein the pipelined quantization front end (301) is provided with a dynamic ringing-based residue amplifier (307) configured to perform residue amplification; a remainder quantization rear end (302), composed of two successive approximation ADC sub-channels (308, 309) and configured to realize comparison and quantization of lower-order bits in the ADC, wherein input ends of the two successive approximation ADC sub-channels (308, 309) are respectively connected to output ends of the dynamic ringing-based residue amplifier (307); and a digital selection and redundant bit correction module (303) connected to output ends of the two successive approximation ADC sub-channels (308, 309) and configured to realize digital output selection, digital output time alignment, and redundant bit correction for the dual-channel time-interleaved successive approximation ADC. The above technical solution has advantages of a high speed and low power consumption when compared with a conventional pipelined successive approximation ADC, thereby reducing the static power consumption of an inter-stage residue amplifier.

Description

High Speed Pipeline-Successive Approximation ADC Based on Dynamic Ringing Operational Amplifier

Technical field

The present invention relates to the field of integrated circuit technology, and more particularly to a high speed pipeline-successive approximation analog-to-digital converter (ADC) based on a dynamic ringing operational amplifier.

Background technique

The pipeline-successive approximation ADC is a new structure that has emerged in the field of data converter design in recent years. It was first published in 2010 by Sym C. Lee and Micheal P. Flynn on Symposium on VLSI circuits. Based on the most simplified two-step structure in the pipeline structure, the sub-ADCs of the front and rear stages are implemented by successive approximation ADCs. This architecture takes advantage of the high data processing rate of pipelined ADCs, combined with the advantages of low power consumption and high linearity of successive approximation ADCs in advanced processes. The combination of the two is beneficial to achieve high speed and high precision of the ADC while ensuring low power consumption of the ADC.

The most expensive part of the pipeline-successive approximation ADC is the inter-stage residual amplifier. In a single-channel ADC, the speed of the residual amplifier is determined by the sampling rate of the ADC, and the accuracy is determined by the accuracy of the successive-stage approximation ADC. So low-power pipelines - the low-power implementation of op amps in successive approximation ADCs contribute to the energy-efficient implementation of the overall ADC.

The ringing operational amplifier was published by the Benjamin Hershberg, UKMoon et al. at the International Solid State Circuits Conference (ISSCC) in 2012. The initial design was based on a ring oscillator, which controlled the output stage to be in a sub-threshold state during steady operation. Achieve small signal amplification. The initial implementation is a pseudo-differential op amp mode, and the output stage is controlled by an external bias signal, as shown in Figure 1. The operational amplifier adopts the form of pseudo differential. In FIG. 1, a circuit structure of a differential path is given, which is formed by cascading the first stage inverter 101, the second stage inverter 102, and the third stage inverter 103, wherein The second stage inverter is split into two groups. When the amplifier is in the reset state, that is, the

switches

105, 106, 107 are closed, different bias voltages are stored on the

capacitors

108 and 109, respectively, so that the amplifier is at During normal operation, the voltages of

capacitors

108 and 109 make NMOS transistor 111 and PMOS transistor 110 of third-pole inverter 103 more susceptible to weak inversion, even sub-threshold regions, thus The output impedance of the op amp is increased, making the loop stable. The capacitor 104 in FIG. 1 is a self-calibrating capacitor, and the voltage difference between the common mode voltage of the input terminal and the common mode voltage of the input signal when the circuit is in the reset state when the circuit is in the reset state.

It was subsequently improved by Yong Lim and Michael P.Flynn, and published in the ISSCC in 2014 and 2015 respectively. The improved ringing operational amplifier is shown in Figure 2. The improvement of Yong Lim et al. is mainly as follows: (1) The pseudo-differential circuit is modified into an input-stage fully differential circuit. The current flows through the NMOS tail

current tubes

204 and 205 in the differential two-way inverter in the first stage 201, and the quiescent current magnitude It is regulated by tail

current tubes

204, 205, bias tube 208, first stage common mode

feedback control tubes

206 and 207, and the like. The feedback signal of the common mode feedback transistor 205 is controlled by the common mode level of the output. (2) The second stage 102 split into two paths in FIG. 1 is improved to 202 in FIG. 2, and the separation of the steady state bias points of the

MOS transistors

212 and 213 in the third stage 203 is realized by the resistor 209, thereby achieving stable operation. Op amp static operating point. (3) Changing the MOS transistors in the second stage 102 and the third stage 103 in FIG. 1 to the high

gate voltage tubes

210, 211, 212, 213, etc., is more advantageous for achieving stable operation of the operational amplifier.

In the improvement of Yong Lim et al., the use of the fully differential first stage 201 reduces the output swing of the first stage inverter and reduces the output rate, which is disadvantageous for implementation in high speed circuits; The use of the same will also reduce the transmission speed of the inverter judgment results. Therefore, the present invention proposes a dynamic ringing operational amplifier capable of effectively increasing the steady speed of the ringing operational amplifier and applying the high speed operational amplifier to a pipeline-successive approximation ADC.

Summary of the invention

The object of the present invention is to propose a novel low power pipeline-successive approximation ADC structure, which is characterized by using a dynamic ringing operational amplifier as a first stage high precision pipeline stage front end and a second level successive approximation ADC. The quantized amplifier between the quantized stages achieves the high-speed quantization feature of the pipelined ADC while still maintaining the low-power characteristics of the successive approximation ADC, while low power consumption through dynamic operational amplifiers and other modular circuits. Designed to further improve energy efficiency.

Specifically, the present invention provides a high speed pipeline-successive approximation ADC based on a dynamic ringing operational amplifier, comprising:

A pipelined quantization front end that implements high-order quantization in the ADC, where the pipelined quantization front end A dynamic ringing residual amplifier for performing residual amplification is provided therein;

The quantized backend is composed of two successive approximation ADC subchannels for realizing comparison quantization of low bits in the ADC, wherein the input terminals of the two successive approximation ADC subchannels are respectively connected to the dynamic ringing residual The output of the amplifier;

Digital selection and redundancy bit calibration module, connected to the outputs of the two successive approximation ADC subchannels and used to implement dual channel time interleaving, digital output selection of the successive approximation ADC, time alignment of digital outputs, and redundancy Remaining calibration.

Preferably, in the above high-speed pipeline-successive approximation ADC, the pipelined quantization front end is an M-bit quantization front end with redundant bits, wherein M is a positive integer, and the M-bit quantization front end with redundant bits includes a gate Pressurized bootstrap sampling switch, M-bit flash type ADC, M-bit thermometer coded capacitor type DAC, the dynamic ringing residual amplifier,

The input signal of the pipelined quantization front end is divided into two paths, and signal sampling is implemented on the M-bit flash type ADC and the M-bit thermometer coded capacitance type DAC, respectively.

Preferably, in the above high speed pipeline-successive approximation ADC, the deviation of the sampling level values of the two input signals is eliminated by the redundant bits of the M-bit quantization front end.

Preferably, in the above high speed pipeline-successive approximation ADC, the dynamic ringing residual amplifier adopts a pseudo differential form, which is inverted by the first stage inverter, the second stage inverter and the third stage. The first stage inverter is provided with two first resistors and a second resistor having a positive feedback effect, one end of the first resistor is connected to one end of the second resistor, and the other end of the first resistor is connected a drain end of the PMOS transistor in the first stage inverter and a gate end of the NMOS transistor in the second stage inverter, and the other end of the second resistor is connected to the drain end of the NMOS transistor in the first stage inverter and The gate terminal of the PMOS transistor in the second stage inverter.

Preferably, in the high-speed pipeline-successive approximation ADC described above, the method further includes: a clock generation module that respectively generates a control clock signal of the pipeline-type quantization front end and a control clock signal of the margin quantization back end according to an externally input frequency.

Preferably, in the above high speed pipeline-successive approximation ADC, the two successive approximation ADC subchannels are N-bit successive approximation ADCs, wherein N is a positive integer, and the N-bit successive approximation ADC is binary coded DAC, dynamic comparator, asynchronous control logic circuit,

Wherein, the margin quantization control clock signal of the back end is connected to the asynchronous control logic circuit to generate a basis The asynchronous control timing obtained by the logic judgment results to realize the control of the binary coded DAC and the dynamic comparator.

Preferably, in the high-speed pipeline-successive approximation ADC described above, the two successive approximation ADC subchannels are implemented by a top plate sampling method.

Preferably, in the high speed pipeline-successive approximation ADC described above, the digital selection and redundancy bit calibration module is implemented by a digital circuit.

In summary, the present invention proposes a high speed pipeline-successive approximation ADC architecture based on a ringing operational amplifier that combines high speed and low power consumption. In the present invention, for the low-power design of the pipeline stage, the structure without the sample-and-hold circuit is adopted; for the high-speed low-power design of the successive stage of the successive approximation ADC, the structure of the sampling of the top plate is adopted.

The foregoing description of the preferred embodiments of the present invention

DRAWINGS

The accompanying drawings are included to provide a further understanding of the embodiments of the invention In the figure:

Figure 1 is a schematic diagram showing the structure of a ringing operational amplifier that was first published in 2012.

Figure 2 is a schematic diagram showing the structure of a ringing operational amplifier published in the ISSCC in 2015.

FIG. 3 is a schematic structural diagram of an embodiment of a high speed pipeline-successive approximation ADC based on a ringing operational amplifier according to the present invention.

FIG. 4 is a schematic structural diagram of a sub-channel successive approximation ADC according to the present invention.

FIG. 5 is an embodiment of a dynamic ringing operational amplifier proposed by the present invention.

Figure 6 is a timing diagram of the main modules of the present invention.

Figure 7 is an explanatory diagram of the setting of the pipeline level redundancy bits in the present invention.

Description of the reference signs:

101, 102, and 103 are the three-stage inverters in the bell-type operational amplifier structure that was first published in 2012. Circuit, 104 is a self-calibration zero capacitor, 105, 106, 107 are operational amplifier reset switches, 108, 109 are bias storage capacitors, and 110, 111 are third-stage output tubes;

201, 202, and 203 are three-stage inverter circuits in the ringing operational amplifier structure published in the ISSCC in 2015, 204 and 205 are first-stage tail current tubes, and 206 and 207 are first-stage output common-mode feedback control tubes. 208 is a bias current control tube, 209 is a static working point separation resistor of the third stage MOS tube, and 210 to 213 are MOS tubes in the second stage and third stage inverter circuits;

301 is the pipeline-level front end, 302 is the successive approximation ADC rear stage, 303 is the digital selection and redundant bit calibration module, 304, 311 is the gate voltage bootstrap switch, 305 is the M-bit flash type ADC, and 306 is the M-bit DAC. 307 is a ringing operational amplifier, 308, 309 are sub-channel successive approximation ADCs, 310 is a clock generation module, and 311 and 312 are two signal sampling paths;

401 is a DAC capacitor array distributed in binary size, 402 is a dynamic comparator, and 403 is an asynchronous control logic;

501, 502, 503 are three-stage inverter circuits in the high-speed ringing operational amplifier structure proposed by the present invention, 504 and 505 are two positive feedback resistors, and 506 to 509 are in one or two two-stage inverter circuits. Inverter MOS tube, 510, 511 is the latter two-stage circuit control tube, and 512 is a common mode feedback circuit;

601 to 606 correspond to

Timing relationship

701 and 702 are residual transmission curve offsets when the comparator is out of adjustment, the comparators of the front and rear stages are mismatched, and the sampling time is deviated.

detailed description

Embodiments of the present invention will now be described in detail with reference to the drawings.

As an example, the present invention can provide a pipeline-successive approximation ADC based on a dynamic ringing operational amplifier, which is implemented as a 200 MS/s sampling rate, 12-bit precision ADC.

FIG. 3 is a schematic structural diagram of an embodiment of a high speed pipeline-successive approximation ADC based on a ringing operational amplifier according to the present invention. In the embodiment shown in FIG. 3, the high speed pipeline-successive approximation ADC based on the dynamic ringing operational amplifier mainly includes: a pipeline type quantization front end 301, a margin quantization back end 302, a digital selection and redundancy bit calibration module 303. And a clock generation module 310. .

The pipelined quantization front end 301 implements quantization of high bits (eg, the first M bits) in the ADC, where A dynamic ringing residual amplifier 307 for performing residual amplification is provided in the pipeline-type quantization front end 301.

Preferably, the pipelined quantization front end 301 is an M-bit quantization front end with redundant bits (where M is a positive integer), and the M-bit quantization front end 301 with redundant bits includes a gate voltage bootstrap sampling switch 304 and M bits. The flash ADC 305, the M-bit thermometer coded capacitor DAC 306, and the dynamic ringing residual amplifier 307 realize quantization of the high M bits and amplification of the residuals in the ADC. The input signal of the pipeline type quantization front end 301 is divided into two

paths

311 and 312, and signal sampling is performed on the capacitors in the M-bit flash type ADC 305 and the capacitance in the M-bit thermometer coded capacitance type DAC 306, respectively. The deviation of the sampling level values of the two input signals is eliminated by the redundant bits of the M-bit quantization front end. That is, the deviation of the sampling level value introduced by the sampling timing deviation on the two sampling signal paths is eliminated in the present invention by setting redundant bits to the pipeline stage.

According to the above configuration, the pipeline-type quantization front end 301 of the present invention adopts a configuration without a sample-and-hold circuit, and reduces the overhead of the operational amplifier in the sample-and-hold circuit.

As an example, the redundancy bits of the pipeline stage sampling quantization front end 301 of the present invention can be designed with a 0.5 bit redundancy design, and the residual transmission curve of the signal after passing through the pipeline stage with redundant bits is as shown in FIG. 7, FIG. The schematic diagram of the residual signal transmission curve of the 2.5-bit pipeline stage is given. In the case of the comparator type offset in the flash type ADC 305, the sampling level error introduced at the sampling time, and the comparator mismatch in the front and rear stages 301 and 302, In the case of the 701 and 702 appearing in the transmission curve, the design of the redundant bits can effectively avoid the residual signal in the range of the input signal of the post-amplifier ADC 302, thereby causing a loss of code.

More specifically, Figure 5 illustrates one embodiment of a dynamic ringing operational amplifier as set forth in the present invention. In view of the application of the present invention in a high speed environment, each stage of the inverter should have a higher speed. Therefore, the dynamic ringing residual amplifier 307 preferably takes the form of a pseudo differential which is constituted by the first stage inverter 501, the second stage inverter 502, and the third stage inverter 503. Give the first stage inverter 501 a larger output swing space and a larger drain-source voltage.

Preferably, the first stage inverter 501 is provided with two first resistors 504 and a second resistor 505 having a positive feedback effect. One end of the first resistor 504 is connected to one end of the second resistor 505, and the other end of the first resistor 504 is connected to the drain end of the PMOS transistor 506 in the first-stage inverter 501 and the NMOS in the second-stage inverter 502. a gate end of the transistor 509, and the other end of the second resistor 505 is connected to the first stage inverter 501 The drain terminal of the NMOS transistor 507 and the gate terminal of the PMOS transistor 510 in the second-stage inverter 502. With such a connection method, in the case where the large signal of the ringing operational amplifier is established, the two MOS transistors of 506 and 509 are more likely to enter the conduction state, thereby realizing the fast transmission of the signal, and the large signal is quickly established; the signal is basically stable and the operation is established. The amplifier enters the small signal setup phase, the output impedance of the third stage 503 gradually exhibits a high impedance state, the current in the first stage 501 decreases, and the voltage drop across 504 and 505 compresses the drain-source voltages of the

MOS transistors

506 and 507. The reasonable values of the 504 and 505 resistor values can maximize the transconductance of the

MOS transistors

506 and 507, thereby effectively increasing the response speed of the small signal in the operational amplifier. The

positive feedback resistors

504 and 505 introduced in the first stage inverter of the present invention have the advantages of improving the large signal and small signal establishing speed of the operational amplifier, and contribute to the application of the ringing operational amplifier in the high speed circuit.

For example, according to the structure shown in Figure 5,

In the case of a high level, the latter two

stages

502 and 503 do not operate, and the input of the first stage inverter 501 is connected to the output terminal for realizing the calibration of the charge storage amount in the sub-zero capacitance. in

In the case of a low level, the op amp operates.

In order to further reduce the power consumption of the ringing operational amplifier, the clocked signal may be further added to the second stage 502 and the third stage 503 of the operational amplifier in the present invention.

Controlled tailpipes

510 and 511. When the operational amplifier is in the reset state, the

tail tubes

510 and 511 are turned off, and the two stages of the operational amplifier are not operated, realizing the effect of the dynamic operational amplifier. In addition, common mode feedback circuit 512 is used to implement common mode stabilization of the pseudo differential operational amplifier.

The margin quantization backend 302 is composed of two successive approximation ADC subchannels 308 and 309 for achieving comparative quantization of the lower bits in the ADC. The inputs of the two successive approximation ADC sub-channels 308 and 309 are respectively connected to the output ends of the dynamic ringing residual amplifier 307.

The two successive approximation ADC sub-channels 308 and 309 described above are preferably N-bit successive approximation ADCs (where N is a positive integer), as shown in FIG. The N-bit successive approximation ADC is preferably composed of a binary coded DAC 401, a dynamic comparator 402, and an asynchronous control logic circuit 403, as shown in FIG. 4, for implementing comparative quantization of the N bits after the ADC.

The ADC structure is preferably an asynchronous successive approximation ADC sampled by a top plate. In the present invention, the successive approximation ADC selects an asynchronous structure, and the timing of the logic of the asynchronous control logic circuit 403 controls the timing, which facilitates the reasonable allocation of the comparison time of each bit and achieves a quick comparison. In the present invention Compared with the traditional bottom plate sampling, the top plate sampling 401 can directly perform signal comparison after sampling, omitting the time of one signal comparison and charge redistribution. This reduces the capacitance by half, reduces the area overhead, and increases the slew rate. In the present invention, the successive approximation ADC is used as the latter stage of the overall ADC, and the accuracy requirement is relatively low, and the top plate sampling can be supported.

The size of the capacitor in the DAC 401 is designed in binary code. Channel control clock

When it is high, the subchannel is in sampling mode; in the channel control clock

When low, the subchannel is in quantization mode. Channel control clock

The asynchronous control logic circuit 403 is used to generate the asynchronous control timing obtained according to the logical judgment result, and the control of the comparator 402 and the DAC 401 is implemented.

The control clock signal of the margin quantization back end is connected to the asynchronous control logic circuit 403 to generate an asynchronous control timing obtained according to the logic judgment result, thereby implementing the control of the binary coded DAC 401 and the dynamic comparator 402.

The digital selection and redundancy bit calibration module 303 is coupled to the outputs of the two successive approximation ADC subchannels 308 and 309 and is used to implement dual channel time interleaving of the digital output selection of the successive approximation ADC, the timing of the digital output Quasi and redundant bit calibration. For example, the digital selection and redundancy bit calibration module 303 is preferably implemented by a digital circuit.

The clock generation module 310 generates a control clock signal of the pipeline type quantization front end 301 and a control clock signal of the margin quantization back end 302, respectively, according to the frequency of the external input. For example, the clock generation module 310 generates a control clock signal of the ADC front-end pipeline stage through a clock drive circuit, a non-overlapping clock generation circuit, a frequency dividing circuit, etc. according to a sinusoidal signal whose external input frequency is a sampling frequency.

Etc., and the control signal clock of the two-channel time-interleaved successive approximation ADC subchannel

with

Finally, an embodiment of the timing diagram of the present invention is shown in FIG. 6, and the working process of the present invention is exemplified below in conjunction with the timing diagram:

(1)

When it is high, the pipeline stage front end works in the sampling mode. Since the sampling capacitor in the DAC306 uses the bottom plate sampling mode, the capacitor top plate is connected to the common mode signal, and the clock signal is used.

The gate voltage bootstrap switch 311 is controlled to implement signal sampling. In sample mode, the ringing op amp is in reset mode and does not work.

(2)

When the falling edge triggers, the signal stops sampling, and the flash ADC 305 starts to compare and quantize according to the input signal obtained by sampling.

The quantized result is passed to the reference level strobe of DAC 306 before the rising edge.

(3)

When high, the DAC 306 generates a residual signal that is amplified by a ringing op amp. The signal is received by the subsequent sub-channel successive approximation ADC and the subsequent quantization is performed.

(4) Sub-time interleaved sub-channel ADC sub-channel 308 is clock signal

Control, subchannel 309 by clock signal

control. Clock signal

with

Clock signal

The frequency is divided and generated by the corresponding logic circuit. Clock signal

with

Control subchannel 308 and subchannel 309 operate alternately to achieve high speed signal quantization and transmission.

In summary, the present invention reduces the overhead of the inter-stage residual amplifier static power consumption compared to the conventional high-speed and low-power consumption of the pipeline-successive ADC; compared with the existing ringing operational amplifier As a result, the amplifier speed is increased, enabling application in high speed ADCs.

It is apparent to those skilled in the art that various modifications and variations can be made in the above-described embodiments of the present invention without departing from the spirit and scope of the invention. Therefore, it is intended that the present invention cover the modifications and modifications of the invention

Claims

A high speed pipeline-successive approximation ADC based on a dynamic ringing operational amplifier, comprising:

a pipeline-type quantization front end, which implements quantization of a high bit in the ADC, wherein a dynamic ringing residual amplifier for performing residual amplification is disposed in the pipeline-type quantization front end;

The quantized backend is composed of two successive approximation ADC subchannels for realizing comparison quantization of lower bits in the ADC, wherein the input terminals of the two successive approximation ADC subchannels are respectively connected to the dynamic ringing type The output of the residual amplifier;

Digital selection and redundancy bit calibration module, digital output selection of the successive approximation ADC connected to the output of the two successive approximation ADC subchannels and used to achieve dual channel time interleaving, time alignment of the digital output And redundant bit calibration.
The high speed pipeline-successive approximation ADC of claim 1 wherein said pipelined quantization front end is an M-bit quantization front end with redundant bits, wherein M is a positive integer, said M with redundant bits The bit quantization front end includes a gate voltage bootstrap sampling switch, an M-bit flash type ADC, an M-bit thermometer coded capacitance type DAC, and the dynamic ringing residual amplifier.

The input signal of the pipelined quantization front end is divided into two paths, and signal sampling is implemented on the M-bit flash type ADC and the M-bit thermometer coded capacitive type DAC, respectively.
The high speed pipeline-successive approximation ADC of claim 2, wherein the deviation of the sampling level values of the two input signals is eliminated by redundant bits of the M-bit quantization front end.
The high speed pipeline-successive approximation ADC of claim 1 wherein said dynamic ringing residual amplifier is in the form of a pseudo differential comprising a first stage inverter, a second stage inverter and said a three-stage inverter, wherein the first-stage inverter is provided with two first resistors and a second resistor having a positive feedback effect, and one end of the first resistor is connected to one end of the second resistor, The other end of the first resistor is connected to the drain end of the PMOS transistor in the first stage inverter and the gate end of the NMOS transistor in the second stage inverter, and the other end of the second resistor is connected to the first stage inverter The drain end of the NMOS transistor and the PMOS transistor in the second stage inverter The gate end.
The high-speed pipeline-successive approximation ADC according to claim 1, further comprising: a clock generation module that respectively generates a control clock signal of the pipeline-type quantization front end according to an externally input frequency and quantizes the remaining amount The control signal of the terminal.
A high-speed pipeline-successive approximation ADC according to claim 5, wherein said two successive approximation ADC subchannels are N-bit successive approximation ADCs, wherein N is a positive integer, said N-bit successive approximation The ADC consists of a binary coded DAC, a dynamic comparator, and an asynchronous control logic.

The control clock signal of the margin quantization back end is connected to the asynchronous control logic circuit to generate an asynchronous control timing obtained according to the logic judgment result, thereby implementing control of the binary coded DAC and the dynamic comparator.
The high-speed pipeline-successive approximation ADC of claim 6, wherein the two successive approximation ADC subchannels are implemented by a top plate sampling method.
The high speed pipeline-successive approximation ADC of claim 1 wherein said digital selection and redundancy bit calibration module is implemented by a digital circuit.