TWI747422B - Successive approximation register analog-to-digital converter - Google Patents

Abstract

A successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) coupled to receive a first input voltage to generate a first output voltage; a second DAC coupled to receive a second input voltage to generate a second output voltage; a comparator having a positive input node coupled to receive the first output voltage of the first DAC, and a negative input node coupled to receive the second output voltage of the second DAC; a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; a first calibration circuit coupled between the positive input node of the comparator and a ground voltage; and a second calibration circuit coupled between the negative input node of the comparator and the ground voltage.

Description

Step-by-step analog to digital converter

The present invention relates to a continuous asymptotic (SAR) analog-to-digital converter (ADC), in particular to a continuous asymptotic analog-to-digital converter capable of correcting top-plate residue voltage.

A successive approximation register analog-to-digital converter (SAR ADC) is a type of analog-to-digital converter (ADC) for equivalently converting analog signals into digital signals. The progressive analog-to-digital converter performs conversion by comparing and searching all possible quantization levels to obtain a digital output. Compared with the general analog-to-digital converter, the progressive analog-to-digital converter uses less circuit area and power consumption.

The time-interleaved progressive analog-to-digital converter uses multiple sub-analog-to-digital converters (sub-ADC) to speed up the conversion. However, the gain error or offset error between these sub-analog-to-digital converters will reduce the overall linearity of the progressive analog-to-digital converter.

Therefore, there is an urgent need to propose a novel correction mechanism to reduce the gain error between multiple analog-to-digital converters in the cyclical analog-to-digital converter.

In view of the foregoing, one of the objectives of the embodiments of the present invention is to provide a SAR analog-to-digital converter (ADC), which can correct the residual voltage on the board, thereby enhancing the gain and input range of the analog-to-digital converter.

According to an embodiment of the present invention, the cyclically asymptotic analog-to-digital converter includes a first digital-to-analog converter, a second digital-to-analog converter, a comparator, a cyclic asymptotic controller, a first correction circuit, and a second correction Circuit. The first digital-to-analog converter receives a first input voltage at its input node and generates a first output voltage at its output node. The second digital-to-analog converter receives a second input voltage at its input node and generates a second output voltage at its output node. The positive input node of the comparator receives the first output voltage of the first digital-to-analog converter, and its negative input node receives the second output voltage of the second digital-to-analog converter. The cyclical controller controls the switching of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison output of the comparator to generate an output code. The first correction circuit is connected between the positive input node of the comparator and the ground voltage. The second correction circuit is connected between the negative input node of the comparator and the ground voltage.

100: Step-by-step analog to digital converter

11A: The first digital to analog converter

11B: Second digital to analog converter

12: Comparator

13: Continuous and progressive controller

14A: The first correction circuit

14B: Second correction circuit

21: The first inverter

22: second inverter

SWp: First start switch

SWn: second start switch

SWcal_1: The first calibration switch

SWcal_2: The second calibration switch

SWrst: reset switch

SWr_goal: target switch

Ccal_1: the first correction capacitor

Ccal_2: The second correction capacitor

Vip: the first input voltage

Vin: second input voltage

Vrefp: Positive reference voltage

Vrefn: negative reference voltage

Vop: first output voltage

Von: second output voltage

Vr_goal: target voltage

Vdd: power supply voltage

M1: The first transistor

M2: second transistor

M3: third transistor

M4: The fourth transistor

M5: Fifth transistor

M6: The sixth transistor

M7: seventh transistor

M8: Eighth Transistor

M9: Ninth Transistor

C: Capacitor

CLK: clock signal

R: reset node

The first figure shows a block diagram of a cyclic analog-to-digital converter capable of correcting the residual voltage of the upper board according to an embodiment of the present invention.

The second figure shows the circuit diagram of the reset switch of the analog-to-digital converter in the first figure.

The first figure shows a block diagram of a SAR analog-to-digital converter (ADC) 100 capable of correcting top-plate residue voltage according to an embodiment of the present invention.

In this embodiment, the progressive analog to digital converter (hereinafter referred to as the analog to digital converter) 100 may include a first digital to analog converter (DAC) 11A, by means of the first bootstrapped switch SWp, It receives the first (or positive) input voltage Vip at its input node, so the input The output node generates the first output voltage Vop. The first digital-to-analog converter 11A may include a complex capacitor (not shown), the upper plate of which is connected to the input node of the first digital-to-analog converter 11A, and the lower plate of which can be switched to the positive reference voltage Vrefp and the negative reference voltage Vrefn.

In a similar situation, the analog-to-digital converter 100 may include a second digital-to-analog converter 11B. The second start switch SWn receives the second (or negative) input voltage Vin at its input node, thereby generating a second (or negative) input voltage Vin at its output node. The second output voltage Von. The second digital-to-analog converter 11B may include a complex capacitor (not shown), the upper plate of which is connected to the input node of the second digital-to-analog converter 11B, and the lower plate of which can be switched to the positive reference voltage Vrefp and the negative reference voltage Vrefn.

The analog-to-digital converter 100 of this embodiment may include a comparator 12, the positive input node of which receives the first output voltage Vop of the first digital-to-analog converter 11A, and the negative input node of which receives the second digital-to-analog converter 11B. The second output voltage Von.

The analog-to-digital converter 100 of this embodiment may include a SAR controller 13, which controls the first digital-to-analog converter 11A and the second digital-to-analog converter 11B according to the comparison output of the comparator 12 Switching is used to generate an output code (code) from the most significant bit (MSB) to the least significant bit (LSB) in sequence.

According to one of the features of this embodiment, the analog-to-digital converter 100 may include a first correction circuit 14A connected between the positive input node of the comparator 12 and the ground voltage. The first correction circuit 14A may include a plurality of first correction capacitors Ccal_1 connected in parallel, the upper plate of which is connected to the positive input node of the comparator 12, and the lower plate of which can be respectively connected to the ground voltage through the first correction switch SWcal_1.

In a similar situation, the analog-to-digital converter 100 may include a second correction circuit 14B connected between the negative input node of the comparator 12 and the ground voltage. The second calibration circuit 14B may include a plurality of second calibration capacitors Ccal_2 connected in parallel, the upper board of which is connected to the negative input node of the comparator 12, and the lower board of which can be respectively connected to the ground voltage through the second calibration switch SWcal_2.

The analog-to-digital converter 100 of this embodiment may include a reset switch SWrst connected between the positive input node and the negative input node of the comparator 12 for resetting the comparator 12. Of this embodiment The analog-to-digital converter 100 may include a goal switch SWr_goal connected between the positive input node of the comparator 12 and the target voltage Vr_goal.

After the sampling period and conversion period of each (or more) cycles, a correction period can be performed. During the calibration period, the reset switch SWrst is turned on (that is, turned on) to generate a reset voltage. After turning off (ie turning off) the reset switch SWrst, turn on (ie turning on) the target switch SWr_goal. Thereby, the comparator 12 compares the target voltage Vr_goal (for the positive input node) with the reset voltage (for the negative input node). Then, the progressive controller 13 controls the switching between the first correction capacitor Ccal_1 (of the first correction circuit 14A) and the second correction capacitor Ccal_2 (of the second correction circuit 14B) according to the comparison result of the comparator 12.

The second figure shows the circuit diagram of the reset switch SWrst of the analog-to-digital converter 100 in the first figure. In this embodiment, the reset switch SWrst may include transistors M1-M9 and capacitor C, and the connection is shown in the figure.

The reset switch may include a first inverter 21 composed of a (P-type) first transistor M1 and a (N-type) second transistor M2, and includes a (P-type) third transistor M3 and (N-type) Type) A second inverter 22 composed of a fourth transistor M4. The first inverter 21 receives the clock signal CLK, and the second inverter 22 receives the output of the first inverter 21.

The first plate of the capacitor C receives the output of the second inverter 22. The drain and source of the (P-type) fifth transistor M5 are connected between the power supply voltage Vdd and the second plate of the capacitor C, and the gate of the fifth transistor M5 is connected to the reset node R. The (P-type) sixth transistor M6 acts as a pass gate, its source and drain are respectively connected to the second plate (of the capacitor C) and the reset node R, and its gate is controlled by the first reverse器21 output.

The (N-type) seventh transistor M7 and the (N-type) eighth transistor M8 are connected in series between the reset node R and the ground. The gate of the seventh transistor M7 is controlled by the output of the first inverter 21, and the gate of the eighth transistor M8 is connected to the power supply voltage Vdd.

The (N-type) ninth transistor M9 serves as a channel gate, and its drain and source are respectively connected to the positive input node and the negative input node of the comparator 12. The gate of the ninth transistor M9 is connected to the reset node R.

When the reset switch is operated, when the clock signal CLK is at a low level, the capacitor C is charged, the transistors M5 and M7 are turned on, and the transistors M6 and M9 are turned off. Therefore, the voltage of the negative output node of the comparator 12 is maintained at the source of the ninth transistor M9.

When the clock signal CLK is at a high level, the capacitor C is discharged, the transistors M5 and M7 are turned off, and the transistors M6 and M9 are turned on. Therefore, the voltage of the drain (that is, the positive input node) of the ninth transistor M9 can be transmitted to the source of the ninth transistor M9.

The above are only the preferred embodiments of the present invention, and are not intended to limit the scope of the patent application of the present invention; all other equivalent changes or modifications made without departing from the spirit of the invention should be included in the following Within the scope of the patent application.

100: Step-by-step analog to digital converter

11A: The first digital to analog converter

11B: Second digital to analog converter

12: Comparator

13: Continuous and progressive controller

14A: The first correction circuit

14B: Second correction circuit

SWp: First start switch

SWn: second start switch

SWcal_1: The first calibration switch

SWcal_2: The second calibration switch

SWrst: reset switch

SWr_goal: target switch

Ccal_1: the first correction capacitor

Ccal_2: The second correction capacitor

Vip: the first input voltage

Vin: second input voltage

Vrefp: Positive reference voltage

Vrefn: negative reference voltage

Vop: first output voltage

Von: second output voltage

Vr_goal: target voltage

Vdd: power supply voltage

Claims (9)

A cyclical analog-to-digital converter, comprising: a first digital-to-analog converter, receiving a first input voltage at its input node, and generating a first output voltage at its output node; a second digital-to-analog converter , Receiving a second input voltage at its input node, and generating a second output voltage at its output node; a comparator whose positive input node receives the first output voltage of the first digital-to-analog converter, and its negative input node receives the A second output voltage of the second digital-to-analog converter; a cyclical controller that controls the switching of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison output of the comparator, To generate an output code; a first correction circuit connected between the positive input node of the comparator and the ground voltage; and a second correction circuit connected between the negative input node of the comparator and the ground voltage; wherein the The first correction circuit includes a plurality of first correction capacitors connected in parallel, the upper plate of which is connected to the positive input node of the comparator, and the lower plate of which can be respectively connected to the ground voltage through the first correction switch. For example, the cyclic asymptotic analog-to-digital converter of claim 1, wherein the first digital-to-analog converter includes a plurality of capacitors, the upper board of which is connected to the input node of the first digital-to-analog converter, and the lower board is switchable To positive reference voltage and negative reference voltage. For example, the cyclic asymptotic analog-to-digital converter of claim 1, wherein the second digital-to-analog converter includes a plurality of capacitors, the upper board of which is connected to the input node of the second digital-to-analog converter, and the lower board is switchable To positive reference voltage and negative reference voltage. For example, the cyclic asymptotic analog-to-digital converter of claim 1, wherein the second correction circuit includes a plurality of first correction capacitors connected in parallel, and the upper plate is connected to the negative input node of the comparator, and the lower plate is corrected by the second The switches can be connected to ground voltage respectively. For example, the cyclic asymptotic analog-to-digital converter of claim 1 further includes: a reset switch connected between the positive input node and the negative input node of the comparator for resetting the comparator; and a target The switch is connected between the positive input node of the comparator and the target voltage. For example, the cyclical analog-to-digital converter of claim 5, wherein during the calibration period, the reset switch and the target switch are turned on, and the cyclical controller controls the first calibration according to the comparison result of the comparator Switching between the circuit and the second correction circuit. For example, the cyclic asymptotic analog-to-digital converter of claim 5, wherein the reset switch includes: a first transistor and a second transistor, forming a first inverter, which receives a clock signal; Three transistors and a fourth transistor form a second inverter, which receives the output of the first inverter; a capacitor, the first plate of which receives the output of the second inverter; a fifth inverter A crystal whose drain and source are connected between the power supply voltage and the second plate of the capacitor, and whose gate is connected to the reset node; a sixth transistor whose source and drain are respectively connected to the first plate of the capacitor The gate of the second board and the reset node is controlled by the output of the first inverter; a seventh transistor and an eighth transistor are connected in series between the reset node and ground, and the seventh transistor The gate of the crystal is controlled by the output of the first inverter, and the gate of the eighth transistor is connected to the power supply voltage; and a ninth transistor whose drain and source are respectively connected to the comparator The gates of the positive input node and the negative input node are connected to the reset node. For example, the cyclic asymptotic analog-to-digital converter of claim 7, wherein when the clock signal is low, the capacitor is charged, the fifth transistor and the seventh transistor are turned on, and the sixth transistor and the The ninth transistor is turned off, so the voltage of the negative output node of the comparator is maintained at the source of the ninth transistor. For example, the cyclic asymptotic analog-to-digital converter of claim 7, wherein when the clock signal is high, the capacitor is discharged, the fifth transistor and the seventh transistor are turned off, and the sixth transistor and the The ninth transistor is turned on, so the voltage of the positive input node is transferred to the source of the ninth transistor.

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