CN114079465A - Progressive analog-to-digital converter - Google Patents
Progressive analog-to-digital converter Download PDFInfo
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- CN114079465A CN114079465A CN202010805206.7A CN202010805206A CN114079465A CN 114079465 A CN114079465 A CN 114079465A CN 202010805206 A CN202010805206 A CN 202010805206A CN 114079465 A CN114079465 A CN 114079465A
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- 230000000750 progressive effect Effects 0.000 title claims abstract description 27
- 239000003990 capacitor Substances 0.000 claims description 33
- 238000010586 diagram Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000004075 alteration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
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Abstract
A progressive analog-to-digital converter comprises a first digital-to-analog converter, a second digital-to-analog converter and a second voltage divider, wherein the first digital-to-analog converter receives a first input voltage to generate a first output voltage; a second digital-to-analog converter receiving a second input voltage to generate a second output voltage; a comparator having a positive input node receiving a first output voltage of the first digital-to-analog converter and a negative input node receiving a second output voltage of the second digital-to-analog converter; the progressive controller controls the switching of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison output of the comparator so as to generate an output code; a first correction circuit connected between a positive input node of the comparator and a ground voltage; and a second correction circuit connected between the negative input node of the comparator and a ground voltage.
Description
Technical Field
The present invention relates to a progressive analog-to-digital converter (ADC), and more particularly, to a progressive ADC capable of correcting a top-plate residual voltage (top-plate residual voltage).
Background
A progressive analog-to-digital converter (SAR ADC) is one type of analog-to-digital converter (ADC) for equivalently converting an analog signal into a digital signal. The progressive adc performs the conversion by comparing and searching all possible quantization levels to obtain a digital output. Compared with a general analog-to-digital converter, the progressive analog-to-digital converter uses less circuit area and power consumption.
Time-interleaved analog-to-digital converters use sub-analog-to-digital converters (sub-ADCs) to speed up the conversion. However, the gain error or offset error between these sub-adcs may reduce the overall linearity of the progressive adc.
Therefore, it is desirable to provide a novel calibration mechanism for reducing the gain error between a plurality of sub-adcs in a progressive adc.
Disclosure of Invention
In view of the foregoing, an objective of the present invention is to provide a progressive-SAR analog-to-digital converter (ADC) capable of correcting the residual voltage of the upper plate, thereby enhancing the gain and input range of the ADC.
According to an embodiment of the present invention, the sequential analog-to-digital converter includes a first digital-to-analog converter, a second digital-to-analog converter, a comparator, a sequential controller, a first correction circuit and a second correction circuit. The first digital-to-analog converter receives a first input voltage at an input node thereof and generates a first output voltage at an output node thereof. The second digital-to-analog converter receives a second input voltage at its input node and generates a second output voltage at its output node. The positive input node of the comparator receives the first output voltage of the first digital-to-analog converter, and the negative input node thereof receives the second output voltage of the second digital-to-analog converter. The progressive controller controls the first digital-to-analog converter and the second digital-to-analog converter to switch according to the comparison output of the comparator so as to generate an output code. The first correction circuit is connected between the positive input node of the comparator and the ground voltage. The second correction circuit is connected between the negative input node of the comparator and a ground voltage.
Preferably, the first digital-to-analog converter includes a plurality of capacitors, upper plates thereof are connected to the input nodes of the first digital-to-analog converter, and lower plates thereof are switchable to a positive reference voltage and a negative reference voltage.
Preferably, the second digital-to-analog converter includes a plurality of capacitors, upper plates thereof are connected to the input nodes of the second digital-to-analog converter, and lower plates thereof are switchable to a positive reference voltage and a negative reference voltage.
Preferably, the first correction circuit comprises a plurality of first correction capacitors connected in parallel, upper plates thereof being connected to the positive input node of the comparator, and lower plates thereof being respectively connected to a ground voltage via first correction switches.
Preferably, the second correction circuit comprises a plurality of first correction capacitors connected in parallel, upper plates thereof being connected to the negative input node of the comparator, and lower plates thereof being respectively connected to a ground voltage by second correction switches.
Preferably, the method further comprises: a reset switch connected between the positive input node and the negative input node of the comparator for resetting the comparator; and the target switch is connected between the positive input node of the comparator and a target voltage.
Preferably, during the calibration period, the reset switch and the target switch are turned on, and the progressive controller controls the switching between the first calibration circuit and the second calibration circuit according to the comparison result of the comparator.
Preferably, the reset switch comprises: a first transistor and a second transistor forming a first inverter for receiving a clock signal; a third transistor and a fourth transistor forming a second inverter which receives an output of the first inverter; a capacitor having a first plate receiving an output of the second inverter; a fifth transistor having a drain and a source connected between a power supply voltage and the second plate of the capacitor, and a gate connected to the reset node; a sixth transistor having a source and a drain connected to the second plate of the capacitor and the reset node, respectively, and a gate controlled by the output of the first inverter; a seventh transistor and an eighth transistor connected in series between the reset node and ground, the gate of the seventh transistor being controlled by the output of the first inverter, and the gate of the eighth transistor being connected to a power supply voltage; and a ninth transistor having a drain and a source connected to the positive input node and the negative input node of the comparator, respectively, and a gate connected to the reset node.
Preferably, when the clock signal is at a low level, the capacitor is charged, the fifth transistor and the seventh transistor are turned on, and the sixth transistor and the ninth transistor are turned off, so that the voltage of the negative output node of the comparator is maintained at the source of the ninth transistor.
Preferably, when the clock signal is at a high level, the capacitor is discharged, the fifth transistor and the seventh transistor are turned off, and the sixth transistor and the ninth transistor are turned on, so that the voltage at the positive input node is transmitted to the source of the ninth transistor.
By means of the technical scheme, the invention at least has the following advantages and effects: the gradual analog-to-digital converter can correct the residual voltage of the upper plate and can enhance the gain and the input range of the analog-to-digital converter.
Drawings
FIG. 1 is a block diagram of a progressive ADC capable of correcting upper plate residual voltage according to an embodiment of the present invention.
Fig. 2 shows a circuit diagram of a reset switch of the analog-to-digital converter of fig. 1.
[ description of main element symbols ]
100 progressive analog-to-digital converter 11A first digital-to-analog converter
11B second digital-to-analog converter 12 comparator
13 progressive controller 14A first correction circuit
14B second correction circuit 21 first inverter
22 second inverter SWp first start switch
SWn second starting switch SWcal _1 first correcting switch
SWcal _2 second correction switch SWrst reset switch
SWr _ goal target switch Ccal _1 first correction capacitor
Ccal 2 second calibration capacitor Vip first input voltage
Vin, second input voltage Vrefp, and Positive reference Voltage
Vrefn negative reference Voltage Vop first output Voltage
Von, second output voltage Vr _ goal, target voltage
Vdd, power supply voltage M1, first transistor
M2 a second transistor M3 a third transistor
M4 a fourth transistor M5 a fifth transistor
M6 sixth transistor M7 seventh transistor
M8 the eighth transistor M9 the ninth transistor
C capacitor CLK clock signal
R is reset node
Detailed Description
Fig. 1 shows a block diagram of a progressive (SAR) analog-to-digital converter (ADC)100 capable of correcting a top-plate residual voltage according to an embodiment of the present invention.
In the present embodiment, the progressive analog-to-digital converter (adc)100 may include a first digital-to-analog converter (DAC)11A receiving a first (or positive) input voltage Vip at an input node thereof via a first start-up (bootstrapped) switch SWp, thereby generating a first output voltage Vop at an output node thereof. The first digital-to-analog converter 11A may include a plurality of capacitors (not shown), an upper plate of which is connected to an input node of the first digital-to-analog converter 11A, and a lower plate of which is switchable to a positive reference voltage Vrefp and a negative reference voltage Vrefn.
Similarly, the adc 100 may comprise a second dac 11B receiving a second (or negative) input voltage Vin at its input node via a second start switch SWn, thereby generating a second output voltage Von at its output node. The second digital-to-analog converter 11B may include a plurality of capacitors (not shown), an upper plate of which is connected to an input node of the second digital-to-analog converter 11B, and a lower plate of which is switchable to a positive reference voltage Vrefp and a negative reference voltage Vrefn.
The adc 100 of the present embodiment may include a comparator 12 having a positive input node receiving the first output voltage Vop of the first digital-to-analog converter 11A and a negative input node receiving the second output voltage Von of the second digital-to-analog converter 11B.
The analog-to-digital converter 100 of the present embodiment may include a progressive (SAR) controller 13 for controlling the switching of the first digital-to-analog converter 11A and the second digital-to-analog converter 11B according to the comparison output of the comparator 12 to sequentially generate the output codes (codes) from the Most Significant Bit (MSB) to the Least Significant Bit (LSB).
According to one feature of the present embodiment, the adc 100 may include a first calibration circuit 14A connected between the positive input node of the comparator 12 and the ground voltage. The first calibration circuit 14A may include a plurality of first calibration capacitors Ccal _1 connected in parallel, the upper plates of which are connected to the positive input node of the comparator 12, and the lower plates of which are respectively connected to the ground voltage via first calibration switches SWcal _ 1.
Similarly, the analog-to-digital converter 100 may include a second correction circuit 14B connected between the negative input node of the comparator 12 and the ground voltage. The second correction circuit 14B may include a plurality of second correction capacitors Ccal _2 connected in parallel, the upper plates of which are connected to the negative input node of the comparator 12, and the lower plates of which are respectively connectable to the ground voltage via second correction switches SWcal _ 2.
The analog-to-digital converter 100 of the present embodiment may include a reset (reset) switch SWrst connected between the positive input node and the negative input node of the comparator 12 for resetting the comparator 12. The analog-to-digital converter 100 of the present embodiment may include a target (goal) switch SWr _ goal connected between the positive input node of the comparator 12 and the target voltage Vr _ goal.
After the sampling period and the conversion period of each cycle (or cycles), a calibration period may be performed. During the calibration period, the reset switch SWrst is turned on (i.e., turned on) to generate a reset voltage. After the reset switch SWrst is turned off (i.e., turned off), the target switch SWr _ goal is turned on (i.e., turned on). Thereby, the comparator 12 compares the target voltage Vr _ goal (of the positive input node) with the reset voltage (of the negative input node). Then, the progressive controller 13 controls switching of the first correction capacitor Ccal _1 (of the first correction circuit 14A) and the second correction capacitor Ccal _2 (of the second correction circuit 14B) according to the comparison result of the comparator 12.
Fig. 2 shows a circuit diagram of the reset switch SWrst of the analog-to-digital converter 100 of fig. 1. In the present embodiment, the reset switch SWrst includes transistors M1-M9 and a capacitor C, connected as shown.
The reset switch may include a first inverter 21 composed of a (P-type) first transistor M1 and a (N-type) second transistor M2, and includes a second inverter 22 composed of a (P-type) third transistor M3 and a (N-type) fourth transistor M4. The first inverter 21 receives a clock signal CLK, and the second inverter 22 receives an output of the first inverter 21.
The first plate of the capacitor C receives the output of the second inverter 22. The drain and source of the (P-type) fifth transistor M5 are connected between the power voltage Vdd and the second plate of the capacitor C, and the gate of the fifth transistor M5 is connected to the reset node R. The (P-type) sixth transistor M6 serves as a pass gate, and has its source and drain connected to the second plate (of the capacitor C) and the reset node R, respectively, and its gate controlled by the output of the first inverter 21.
An (N-type) seventh transistor M7 and an (N-type) eighth transistor M8 are connected in series between the reset node R and ground. The gate of the seventh transistor M7 is controlled by the output of the first inverter 21, and the gate of the eighth transistor M8 is connected to the power voltage Vdd.
The ninth transistor M9 is a pass gate, and has a drain and a source connected to the positive input node and the negative input node of the comparator 12, respectively. The gate of the ninth transistor M9 is connected to the reset node R.
When the reset switch is operated, when the clock signal CLK is low, the capacitor C is charged, the transistors M5 and M7 are turned on, and the transistors M6 and M9 are turned off. Therefore, the voltage at the negative output node of the comparator 12 is held at the source of the ninth transistor M9.
When the clock signal CLK is high, the capacitor C is discharged, the transistors M5 and M7 are turned off, and the transistors M6 and M9 are turned on. Therefore, the voltage at the drain (i.e., the positive input node) of the ninth transistor M9 is transmitted to the source of the ninth transistor M9.
Although the present invention has been described with reference to a preferred embodiment, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A progressive analog-to-digital converter, comprising:
a first digital-to-analog converter receiving a first input voltage at an input node thereof and generating a first output voltage at an output node thereof;
a second digital-to-analog converter receiving a second input voltage at its input node and generating a second output voltage at its output node;
a comparator having a positive input node receiving a first output voltage of the first digital-to-analog converter and a negative input node receiving a second output voltage of the second digital-to-analog converter;
a progressive controller for controlling the switching of the first DAC and the second DAC according to the comparison output of the comparator to generate an output code;
a first correction circuit connected between a positive input node of the comparator and a ground voltage; and
and a second correction circuit connected between the negative input node of the comparator and a ground voltage.
2. The progressive analog-to-digital converter of claim 1, wherein the first digital-to-analog converter comprises a plurality of capacitors, upper plates of which are connected to the input nodes of the first digital-to-analog converter, and lower plates of which are switchable to a positive reference voltage and a negative reference voltage.
3. The progressive analog-to-digital converter of claim 1, wherein the second digital-to-analog converter comprises a plurality of capacitors, upper plates of which are connected to the input nodes of the second digital-to-analog converter, and lower plates of which are switchable to a positive reference voltage and a negative reference voltage.
4. The sequential-progression analog-to-digital converter of claim 1, wherein the first correction circuit comprises a plurality of first correction capacitors connected in parallel, upper plates of which are connected to positive input nodes of the comparators, and lower plates of which are respectively connected to a ground voltage by first correction switches.
5. The sequential progressive analog-to-digital converter of claim 1, wherein the second calibration circuit comprises a plurality of parallel first calibration capacitors, upper plates of which are connected to the negative input nodes of the comparators, and lower plates of which are respectively connected to a ground voltage by second calibration switches.
6. The progressive analog-to-digital converter of claim 1, further comprising:
a reset switch connected between the positive input node and the negative input node of the comparator for resetting the comparator; and
and the target switch is connected between the positive input node of the comparator and a target voltage.
7. The sequential-progression ADC of claim 6, wherein during a calibration period, the reset switch and the target switch are turned on, the sequential-progression controller controls the switching between the first calibration circuit and the second calibration circuit according to the comparison result of the comparator.
8. The progressive analog-to-digital converter of claim 1, wherein the reset switch comprises:
a first transistor and a second transistor forming a first inverter for receiving a clock signal;
a third transistor and a fourth transistor forming a second inverter which receives an output of the first inverter;
a capacitor having a first plate receiving an output of the second inverter;
a fifth transistor having a drain and a source connected between a power supply voltage and the second plate of the capacitor, and a gate connected to the reset node;
a sixth transistor having a source and a drain connected to the second plate of the capacitor and the reset node, respectively, and a gate controlled by the output of the first inverter;
a seventh transistor and an eighth transistor connected in series between the reset node and ground, the gate of the seventh transistor being controlled by the output of the first inverter, and the gate of the eighth transistor being connected to a power supply voltage; and
a ninth transistor having a drain and a source connected to the positive input node and the negative input node of the comparator, respectively, and a gate connected to the reset node.
9. The sequential analog-to-digital converter of claim 8, wherein when the clock signal is low, the capacitor is charged, the fifth and seventh transistors are turned on, and the sixth and ninth transistors are turned off, so that the voltage at the negative output node of the comparator is maintained at the source of the ninth transistor.
10. The sequential analog-to-digital converter of claim 8, wherein when the clock signal is high, the capacitor is discharged, the fifth and seventh transistors are turned off, and the sixth and ninth transistors are turned on, so that the voltage at the positive input node is transmitted to the source of the ninth transistor.
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| CN202010805206.7A CN114079465B (en) | 2020-08-12 | 2020-08-12 | Step-by-step analog-to-digital converter |
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Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448911B1 (en) * | 2001-07-30 | 2002-09-10 | Cirrus Logic, Inc. | Circuits and methods for linearizing capacitor calibration and systems using the same |
| US20080316080A1 (en) * | 2007-06-22 | 2008-12-25 | Nec Electronics Corporation | Successive approximation type A/D converter |
| US20100207791A1 (en) * | 2009-01-23 | 2010-08-19 | Frank Ohnhaeuser | Sar adc and method with inl compensation |
| US20120262316A1 (en) * | 2011-04-13 | 2012-10-18 | Maxim Integrated Products, Inc. | Method to reduce voltage swing at comparator input of successive-approximations-register analog-to-digital converters |
| CN102859882A (en) * | 2010-04-22 | 2013-01-02 | 德州仪器公司 | Successive approximation register analog-to-digital converter with integral non-linearity correction |
| CN103095299A (en) * | 2011-11-04 | 2013-05-08 | 财团法人工业技术研究院 | Weight estimation method and device and analog-digital converter applying same |
| KR101746063B1 (en) * | 2016-06-02 | 2017-06-12 | 금오공과대학교 산학협력단 | Offset error correction apparatus of sar adc |
| US20170179974A1 (en) * | 2015-12-17 | 2017-06-22 | Imec Vzw | Circuit for Stabilizing a Digital-to-Analog Converter Reference Voltage |
| US20170302288A1 (en) * | 2016-04-15 | 2017-10-19 | Realtek Semiconductor Corporation | Calibration Circuit and Calibration Method for DAC |
| CN109802675A (en) * | 2019-01-21 | 2019-05-24 | 电子科技大学 | A kind of SAR ADC high-accuracy capacitor array correcting method |
| US20190229747A1 (en) * | 2018-01-19 | 2019-07-25 | Socionext Inc. | Analogue-to-digital converter circuitry |
| US20200195269A1 (en) * | 2018-12-12 | 2020-06-18 | Realtek Semiconductor Corporation | Successive approximation register analog-to-digital converter and operation method thereof |
-
2020
- 2020-08-12 CN CN202010805206.7A patent/CN114079465B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448911B1 (en) * | 2001-07-30 | 2002-09-10 | Cirrus Logic, Inc. | Circuits and methods for linearizing capacitor calibration and systems using the same |
| US20080316080A1 (en) * | 2007-06-22 | 2008-12-25 | Nec Electronics Corporation | Successive approximation type A/D converter |
| US20100207791A1 (en) * | 2009-01-23 | 2010-08-19 | Frank Ohnhaeuser | Sar adc and method with inl compensation |
| CN102859882A (en) * | 2010-04-22 | 2013-01-02 | 德州仪器公司 | Successive approximation register analog-to-digital converter with integral non-linearity correction |
| US20120262316A1 (en) * | 2011-04-13 | 2012-10-18 | Maxim Integrated Products, Inc. | Method to reduce voltage swing at comparator input of successive-approximations-register analog-to-digital converters |
| CN103095299A (en) * | 2011-11-04 | 2013-05-08 | 财团法人工业技术研究院 | Weight estimation method and device and analog-digital converter applying same |
| US20170179974A1 (en) * | 2015-12-17 | 2017-06-22 | Imec Vzw | Circuit for Stabilizing a Digital-to-Analog Converter Reference Voltage |
| US20170302288A1 (en) * | 2016-04-15 | 2017-10-19 | Realtek Semiconductor Corporation | Calibration Circuit and Calibration Method for DAC |
| KR101746063B1 (en) * | 2016-06-02 | 2017-06-12 | 금오공과대학교 산학협력단 | Offset error correction apparatus of sar adc |
| US20190229747A1 (en) * | 2018-01-19 | 2019-07-25 | Socionext Inc. | Analogue-to-digital converter circuitry |
| US20200195269A1 (en) * | 2018-12-12 | 2020-06-18 | Realtek Semiconductor Corporation | Successive approximation register analog-to-digital converter and operation method thereof |
| CN109802675A (en) * | 2019-01-21 | 2019-05-24 | 电子科技大学 | A kind of SAR ADC high-accuracy capacitor array correcting method |
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