CN111277271A - Low-power-consumption successive approximation type analog-to-digital conversion circuit and time sequence arrangement method - Google Patents
Low-power-consumption successive approximation type analog-to-digital conversion circuit and time sequence arrangement method Download PDFInfo
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- CN111277271A CN111277271A CN202010204599.6A CN202010204599A CN111277271A CN 111277271 A CN111277271 A CN 111277271A CN 202010204599 A CN202010204599 A CN 202010204599A CN 111277271 A CN111277271 A CN 111277271A
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- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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Abstract
The invention discloses a low-power-consumption successive approximation type analog-to-digital conversion circuit and a time sequence arrangement method, wherein the circuit successive approximation type analog-to-digital conversion circuit comprises a comparator, a digital-to-analog converter and a successive approximation logic circuit; the comparator comprises a preamplifier, a dynamic latch and a latch ready signal generating circuit; the latch ready signal generating circuit comprises a first inverter, a second inverter and a NOR gate circuit; the input end of the first inverter is used as the first input end of the latch ready signal generating circuit; the output end of the first inverter is connected with the first input end of the NOR gate circuit; the input end of the second inverter is used as the second input end of the latch ready signal generating circuit; the output end of the second inverter is connected with the second input end of the NOR gate circuit; the output end of the NOR gate circuit outputs a latch tie signal. The invention can reduce the bias current of the preamplifier in the comparator, thereby reducing the power consumption of the successive approximation type analog-to-digital conversion circuit.
Description
Technical Field
The invention relates to the technical field of analog-to-digital conversion, in particular to a low-power-consumption successive approximation type analog-to-digital conversion circuit and a time sequence arrangement method.
Background
Analog-to-digital conversion is a technique for converting an analog signal into a digital signal. Signals occurring in the real world, such as light intensity signals, electrocardiogram signals, etc., are all in the form of analog signals, and if digital processing is required, these signals are converted into digital signals. A circuit for implementing such a technique is called an analog-to-digital conversion circuit, and nowadays, the analog-to-digital conversion circuit is often implemented in the form of a semiconductor integrated circuit. The mainstream semiconductor analog-digital conversion circuit has a structure of a flash type, a successive approximation type, a pipeline type, a Sigma-Delta type and the like, wherein the successive approximation type analog-digital conversion circuit is suitable for low-power consumption occasions such as wearable equipment and implantable medical equipment.
The traditional successive approximation type analog-digital circuit comprises a comparator, a digital-analog converter and a successive approximation logic circuit, wherein the comparator consists of a preamplifier and a dynamic latch, and the comparator compares the output of the digital-analog converter with a common-mode voltage. The comparator and the successive approximation logic circuit in the conventional successive approximation type analog-to-digital conversion circuit are both driven by a clock signal only, so all steps in the conventional successive approximation type analog-to-digital conversion circuit, such as comparator reset, digital-to-analog converter update output, comparator comparison and the like, can only occur from a rising edge or a falling edge of the clock signal, wherein the two steps of digital-to-analog converter update output and comparator comparison occur simultaneously, which can cause the following adverse conditions: since the output of the digital-to-analog converter is not yet stable when the comparator starts to compare, fluctuations in the output of the digital-to-analog converter will cause fluctuations in the output of the preamplifier in the comparator. In the worst case, when the output of the digital-to-analog converter crosses from a voltage far from the common mode voltage and is very close to the common mode voltage when the output is updated, the output of the preamplifier in the comparator does not reach the final state at the end of the clock period due to the speed limitation, so that an error comparison result is generated. The speed of the preamplifier in the comparator is determined by two parameters, namely the slew rate and the gain bandwidth product, and the bias current of the preamplifier needs to be greatly increased to increase the speed of the preamplifier in the comparator, which leads to the increase of the power consumption of the whole successive approximation analog-digital circuit.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provide a low-power consumption successive approximation type analog-to-digital conversion circuit and a time sequence arrangement method.
A low-power consumption successive approximation type analog-to-digital conversion circuit comprises a comparator, a digital-to-analog converter and a successive approximation logic circuit;
the positive phase input end of the comparator is connected with the common mode voltage, the negative phase input end of the comparator is connected with the output of the digital-to-analog converter, the clock input end of the comparator is connected with a clock signal, the reset input end of the comparator is connected with the latch ready signal output end of the comparator, and the comparator outputs a comparison result and a latch ready signal.
The sampling input end of the digital-to-analog converter is connected with the analog signal input, the sampling control input end is connected with the sampling control signal output by the successive approximation logic circuit, and the digital code input end is connected with the digital code output by the successive approximation logic circuit.
The clock input end of the successive approximation logic circuit is connected with a clock signal, the comparison result input end of the successive approximation logic circuit is connected with the comparison result output of the comparator, the latch ready signal input end is connected with the latch ready signal output of the comparator, and the successive approximation logic circuit outputs a sampling control signal and a digital code.
Preferably, the comparator comprises a preamplifier, a dynamic latch and a latch ready signal generating circuit; wherein the positive phase input end of the preamplifier is used as the positive phase input end of the comparator; the inverting input end of the preamplifier is used as the inverting input end of the comparator; the reset end of the preamplifier is used as the reset input end of the comparator; the positive phase output end of the preamplifier is connected with the positive phase input end of the dynamic latch; the inverting output end of the preamplifier is connected with the inverting input end of the dynamic latch; the reset end of the dynamic latch is used as the clock input end of the comparator; the positive phase output end of the dynamic latch outputs the comparison result of the comparator and is connected with the first input end of the latch ready signal generating circuit; the inverted output end of the dynamic latch is connected with the second input end of the latch ready signal generating circuit; the output end of the latch ready signal generating circuit outputs a latch ready signal.
Preferably, the latch ready signal generating circuit comprises a first inverter, a second inverter and a nor gate circuit; wherein the input end of the first inverter is used as the first input end of the latch ready signal generating circuit; the output end of the first inverter is connected with the first input end of the NOR gate circuit; the input end of the second inverter is used as the second input end of the latch ready signal generating circuit; the output end of the second inverter is connected with the second input end of the NOR gate circuit; the output terminal of the NOR gate circuit is used as the output terminal of the latch tie signal generating circuit.
The time sequence arrangement method of the low-power-consumption successive approximation type analog-to-digital conversion circuit comprises the following steps of:
s1, when a conversion starts, the successive approximation logic circuit outputs a high-level sampling control signal on the rising edge of the clock signal, and the digital-to-analog converter samples an analog signal; the comparator outputs a latch ready signal of low level;
s2, at the rising edge of the next clock signal, the successive approximation logic circuit outputs a low-level sampling control signal, and the digital-to-analog converter stops sampling the analog signal; the comparator compares the common-mode voltage with the output of the digital-to-analog converter;
s3, at the falling edge of the clock signal of the step S2, the comparator outputs the comparison result; after the comparator outputs a comparison result for an establishment time, the comparator outputs a high-level latch ready signal;
s4, at the rising edge of the latch ready signal, the successive approximation logic circuit updates and outputs the digital code according to the comparison result; the digital-to-analog converter updates output according to the digital code; resetting the comparator;
and S5, repeating the steps S2 to S4 until the current conversion is completed, and outputting the digital code of the conversion result by the successive approximation logic circuit.
Compared with the prior art, the invention has the following advantages and effects:
the comparator in the circuit can output a latch ready signal after outputting a comparison result for a set-up time, control the successive approximation logic circuit to update the digital coding output immediately after the comparison result is generated, enable the digital-to-analog converter to update the output after the comparison result is generated, simultaneously control the comparator to reset, enable the step of updating the output of the digital-to-analog converter to occur before the comparison step of the comparator in advance, enable the digital-to-analog converter to output stable when the comparator compares the output of the digital-to-analog converter with the common-mode voltage, avoid the problem that the speed of a preamplifier in the comparator needs to be increased due to the fluctuation of the output of the digital-to-analog converter, reduce the speed requirement of the preamplifier in the comparator, reduce the bias current of the preamplifier, thereby reducing the power consumption of the comparator and achieving the purpose of reducing the power consumption of the successive approximation analog-.
Drawings
Fig. 1 is a block diagram of a successive approximation type analog-to-digital conversion circuit according to the present embodiment;
FIG. 2 is a block diagram of a comparator in a successive approximation type analog-to-digital conversion circuit according to the present embodiment;
FIG. 3 is a block diagram illustrating a latch ready signal generating circuit in a comparator of a successive approximation type analog-to-digital conversion circuit according to the present embodiment;
fig. 4 is a schematic diagram of the analog-to-digital conversion timing implemented by the successive approximation type analog-to-digital conversion circuit of the present embodiment.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.
As shown in fig. 1, a low power consumption successive approximation type analog-to-digital conversion circuit of the present embodiment includes a comparator, a digital-to-analog converter, and a successive approximation logic circuit;
the positive phase input end of the comparator is connected with the common mode voltage, the negative phase input end of the comparator is connected with the output of the digital-to-analog converter, the clock input end of the comparator is connected with a clock signal, the reset input end of the comparator is connected with the output end of the latch ready signal, and the comparator outputs a comparison result and the latch ready signal;
the sampling input end of the digital-to-analog converter is connected with an analog signal input, the sampling control input end is connected with a sampling control signal, and the digital code input end is connected with a digital code output by the successive approximation logic circuit;
the clock input end of the successive approximation logic circuit is connected with a clock signal, the comparison result input end is connected with the comparison result output of the comparator, the latch ready signal input end is connected with the latch ready signal output of the comparator, and the successive approximation logic circuit outputs a sampling control signal and a digital code.
As shown in fig. 2, the comparator includes a preamplifier a1, a dynamic latch I1, and a latch ready signal generation circuit I2; wherein the positive phase input terminal of the preamplifier A1 is used as the positive phase input terminal of the comparator; the inverting input terminal of the preamplifier A1 is used as the inverting input terminal of the comparator; the reset end of the preamplifier A1 is used as the reset input end of the comparator; the non-inverting output terminal of the preamplifier A1 is connected with the non-inverting input terminal of the dynamic latch I1; the inverting output terminal of the preamplifier A1 is connected with the inverting input terminal of the dynamic latch I1; the reset end of the dynamic latch I1 is used as the clock input end of the comparator; the non-inverting output terminal of the dynamic latch I1 outputs the comparison result of the comparator, and is connected with the first input terminal of the latch ready signal generating circuit I2; the inverted output end of the dynamic latch I1 is connected with the second input end of the latch ready signal generating circuit I2; the output terminal of the latch ready signal generation circuit I2 outputs a latch ready signal.
As shown in fig. 3, the latch ready signal generation circuit I2 includes a first inverter I21, a second inverter I22 and a nor gate I23, wherein an input terminal of the first inverter I21 is used as a first input terminal of the latch ready signal generation circuit I2; the output end of the first inverter I21 is connected with the first input end of the NOR gate circuit I23; the input end of the second inverter I22 is used as the second input end of the latch ready signal generating circuit I2; the output end of the second inverter I22 is connected with the second input end of the NOR gate circuit I23; the output terminal of the NOR gate circuit I23 serves as the output terminal of the latch tie signal generating circuit I2.
In this embodiment, a timing arrangement method implemented by a low-power-consumption successive approximation type analog-to-digital conversion circuit is shown in fig. 4, and includes the following steps:
s1, when a conversion starts, the successive approximation logic circuit outputs a high-level sampling control signal on the rising edge of the clock signal, and the digital-to-analog converter samples an analog signal; the comparator outputs a latch ready signal of low level;
s2, at the rising edge of the next clock signal, the successive approximation logic circuit outputs a low-level sampling control signal, and the digital-to-analog converter stops sampling the analog signal; the comparator compares the common-mode voltage with the output of the digital-to-analog converter;
s3, at the falling edge of the clock signal of S2, the comparator outputs the comparison result; after the comparator outputs a comparison result for an establishment time, the comparator outputs a high-level latch ready signal;
s4, at the rising edge of the latch ready signal, the successive approximation logic circuit updates and outputs the digital code according to the comparison result; the digital-to-analog converter updates output according to the digital code; resetting the comparator;
and S5, repeating the steps S2 to S4 until the current conversion is completed, and outputting the digital code of the conversion result by the successive approximation logic circuit.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (4)
1. A low-power consumption successive approximation type analog-to-digital conversion circuit is characterized by comprising a comparator, a digital-to-analog converter and a successive approximation logic circuit;
the positive phase input end of the comparator is connected with the common mode voltage, the negative phase input end of the comparator is connected with the output of the digital-to-analog converter, the clock input end of the comparator is connected with a clock signal, the reset input end of the comparator is connected with the latch ready signal output end of the comparator, and the comparator outputs a comparison result and a latch ready signal;
the sampling input end of the digital-to-analog converter is connected with an analog signal input, the sampling control input end is connected with a sampling control signal output by the successive approximation logic circuit, and the digital code input end is connected with a digital code output by the successive approximation logic circuit;
the clock input end of the successive approximation logic circuit is connected with a clock signal, the comparison result input end of the successive approximation logic circuit is connected with the comparison result output of the comparator, the latch ready signal input end is connected with the latch ready signal output of the comparator, and the successive approximation logic circuit outputs a sampling control signal and a digital code.
2. A low power consumption successive approximation type analog-to-digital conversion circuit according to claim 1, wherein the comparator comprises a preamplifier (a 1), a dynamic latch (I1) and a latch ready signal generating circuit I2; wherein the non-inverting input terminal of the preamplifier (A1) is used as the non-inverting input terminal of the comparator; the inverting input terminal of the preamplifier (A1) is used as the inverting input terminal of the comparator; the reset end of the preamplifier (A1) is used as the reset input end of the comparator; the non-inverting output terminal of the preamplifier (A1) is connected with the non-inverting input terminal of the dynamic latch (I1); the inverting output end of the preamplifier (A1) is connected with the inverting input end of the dynamic latch (I1); the reset end of the dynamic latch (I1) is used as the clock input end of the comparator; the non-inverting output end of the dynamic latch (I1) outputs the comparison result of the comparator and is connected with the first input end of the latch ready signal generating circuit (I2); the inverting output end of the dynamic latch (I1) is connected with the second input end of the latch ready signal generating circuit (I2); the output terminal of the latch ready signal generation circuit (I2) outputs a latch ready signal.
3. The ADC circuit of claim 2, wherein the latch ready signal generation circuit (I2) comprises a first inverter (I21), a second inverter (I22) and a NOR gate circuit (I23); wherein an input terminal of the first inverter (I21) serves as a first input terminal of the latch ready signal generating circuit (I2); the output end of the first inverter (I21) is connected with the first input end of the NOR gate circuit (I23); an input terminal of the second inverter (I22) is used as a second input terminal of the latch ready signal generating circuit (I2); the output end of the second inverter (I22) is connected with the second input end of the NOR gate circuit (I23); the output terminal of the NOR gate circuit (I23) serves as the output terminal of the latch tie signal generating circuit (I2).
4. The method of claim 1 for scheduling a low power successive approximation analog to digital conversion circuit, comprising the steps of:
s1, when a conversion starts, the successive approximation logic circuit outputs a high-level sampling control signal on the rising edge of the clock signal, and the digital-to-analog converter samples an analog signal; the comparator outputs a latch ready signal of low level;
s2, at the rising edge of the next clock signal, the successive approximation logic circuit outputs a low-level sampling control signal, and the digital-to-analog converter stops sampling the analog signal; the comparator compares the common-mode voltage with the output of the digital-to-analog converter;
s3, at the falling edge of the clock signal of the step S2, the comparator outputs the comparison result; after the comparator outputs a comparison result for an establishment time, the comparator outputs a high-level latch ready signal;
s4, at the rising edge of the latch ready signal, the successive approximation logic circuit updates and outputs the digital code according to the comparison result; the digital-to-analog converter updates output according to the digital code; resetting the comparator;
and S5, repeating the steps S2 to S4 until the current conversion is completed, and outputting the digital code of the conversion result by the successive approximation logic circuit.
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Cited By (1)
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| CN113839676A (en) * | 2020-06-23 | 2021-12-24 | 円星科技股份有限公司 | Successive approximation type analog-to-digital conversion circuit and operation method thereof |
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