CN219181502U - Pipelined analog-to-digital converter - Google Patents
Pipelined analog-to-digital converter Download PDFInfo
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- CN219181502U CN219181502U CN202123088232.1U CN202123088232U CN219181502U CN 219181502 U CN219181502 U CN 219181502U CN 202123088232 U CN202123088232 U CN 202123088232U CN 219181502 U CN219181502 U CN 219181502U
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Abstract
The utility model discloses a pipelined analog-to-digital converter, which comprises a multi-stage pipeline unit and an output register; each stage of pipeline unit comprises a sampling hold circuit, a sub-ADC, a sub-DAC, a dynamic amplifier and a Yu Chasheng circuit, wherein the output end of the sampling hold circuit is respectively and electrically connected with the input end of the sub-ADC and the input end of the dynamic amplifier, the output end of the dynamic amplifier is electrically connected with the first input end of the residual generating circuit, the output end of the sub-ADC is electrically connected with the input end of the sub-DAC, and the output end of the sub-DAC is electrically connected with the second input end of the residual generating circuit; the output end of each sub DAC is respectively and electrically connected with the input end of the output register. According to the pipelined analog-to-digital converter, the quantization process and the amplification process of the pipeline units are decoupled, so that the two processes can be parallelized, the time required by each pipeline unit is saved, and the running speed of the whole system is improved.
Description
Technical Field
The present utility model relates to the field of analog-to-digital converters, and in particular, to a pipelined analog-to-digital converter.
Background
The direct radio frequency sampling (Direct RF sampling) technique provides many advantages for wideband and multiband communications, but places extremely high performance requirements on the required analog-to-digital converter (ADC), requiring that neither the input bandwidth nor the sampling rate be below gigahertz. As an important technology of the gigahertz radio frequency sampling analog-to-digital converter, the time interleaving (time-interleaving) technology can effectively improve the sampling rate of the system, but a large number of time interleaving channels can obviously improve the complexity of the system, introduce various mismatch errors and further reduce the performance and stability of the system. In a time interleaved ADC system, increasing the sampling rate of a single channel ADC can reduce the number of channels required, reduce the complexity of the system, reduce the difficulty of correcting mismatch errors, and even realize a gigahertz radio frequency sampling ADC with a single channel. Therefore, it is important to increase the sampling rate of the single channel ADC.
In general, pipelined architectures can better balance system complexity, slew rate, slew accuracy, and calibration overhead, and are the mainstream architecture for medium-high accuracy high-speed ADCs. Pipelined ADCs are composed of a cascade of multiple pipelined units having a similar internal architecture. Each stage of the pipelined ADC includes a sample-and-hold unit, a quantization and residual generation unit, and a residual amplification unit. The single pipeline cascading unit only needs to complete low-precision quantization and transfer the generated residual difference signal to the post stage of the pipeline, and the post quantization work is completed by the post stage. In a single stage pipeline unit of a conventional pipelined ADC, three main steps of sampling, quantization, and residual amplification need to be performed sequentially in one clock cycle. The current pipeline unit firstly samples the signal transmitted from the previous stage, the sampled signal is quantized by the quantization unit of the current stage after the sampling is finished, and then a residual signal is generated by a feedback DAC (analog-to-digital converter) according to the quantization result of the current pipeline unit. After the generation of the residual difference signal is finished, the residual difference signal is amplified by the residual differential state amplifier of the current stage and is transmitted to the next stage. The specific structure and the time sequence are shown in fig. 1 and 2. Since the generation of the residual depends on the feedback of the quantization result, the residual amplification must not be performed until the quantization is completed. Thus, the conversion rate of pipelined ADCs is limited by the time required for a single stage pipeline to sequentially complete sampling, quantization, and residual amplification.
Disclosure of Invention
The present utility model aims to solve at least one of the technical problems existing in the prior art. Therefore, the utility model provides a pipelined analog-to-digital converter which can improve the running speed of a system.
A pipelined analog-to-digital converter according to an embodiment of the present utility model includes: the multi-stage pipeline unit comprises a sampling hold circuit, a sub-ADC, a sub-DAC, a dynamic amplifier and a Yu Chasheng circuit, wherein the output end of the sampling hold circuit is electrically connected with the input end of the sub-ADC and the input end of the dynamic amplifier respectively, the output end of the dynamic amplifier is electrically connected with the first input end of the Yu Chasheng circuit, the output end of the sub-ADC is electrically connected with the input end of the sub-DAC, and the output end of the sub-DAC is electrically connected with the second input end of the Yu Chasheng circuit; and the output end of each sub DAC is electrically connected with the input end of the output register respectively.
The pipelined analog-to-digital converter according to the embodiment of the utility model has at least the following beneficial effects: decoupling the quantization process and the amplification process of the pipeline units, so that the two processes can be parallelized, thereby saving the time required by each pipeline unit and improving the running speed of the whole system; meanwhile, the pipelined analog-to-digital converter can improve the operation rate of the single-channel ADC to the gigahertz range, has expandability, and can further expand the conversion rate or increase the length of the pipeline by a time interleaving technology, thereby improving the single-stage quantization precision and other schemes to expand the quantization precision.
According to some embodiments of the utility model, the clock control unit is configured to provide a clock signal to each of the sample-and-hold circuits.
According to some embodiments of the utility model, the dynamic amplifier comprises: the grid electrode of the first MOS tube is connected with a main amplification clock signal; the source electrode of the second MOS tube is electrically connected with the source electrode of the first MOS tube; the grid electrode of the third MOS tube is connected with positive end input voltage, the drain electrode of the third MOS tube is electrically connected with the drain electrode of the first MOS tube, and a positive end voltage output port is arranged between the drain electrode of the third MOS tube and the drain electrode of the first MOS tube; the grid electrode of the fourth MOS tube is connected with negative end input voltage, the drain electrode of the fourth MOS tube is electrically connected with the drain electrode of the second MOS tube, and a negative end voltage output port is arranged between the drain electrode of the fourth MOS tube and the drain electrode of the second MOS tube; a fifth MOS tube, wherein the grid electrode of the fifth MOS tube is connected with the positive end input voltage, and the drain electrode of the fifth MOS tube is electrically connected with the source electrode of the third MOS tube; a sixth MOS tube, wherein the grid electrode of the sixth MOS tube is connected with the negative end input voltage, and the drain electrode of the sixth MOS tube is electrically connected with the source electrode of the fourth MOS tube; a seventh MOS tube, wherein the grid electrode of the seventh MOS tube is connected with the main amplification clock signal, the drain electrode of the seventh MOS tube is electrically connected with the source electrode of the fifth MOS tube, and the source electrode of the seventh MOS tube is grounded; the grid electrode of the eighth MOS tube is connected with the main amplification clock signal, the drain electrode of the eighth MOS tube is electrically connected with the source electrode of the sixth MOS tube, and the source electrode of the eighth MOS tube is grounded; and the grid electrode of the ninth MOS tube is connected with the main amplification clock signal, the drain electrode of the ninth MOS tube is respectively and electrically connected with the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube, and the source electrode of the ninth MOS tube is grounded.
According to some embodiments of the utility model, a first resistor is further disposed between the drain of the fifth MOS transistor and the drain of the ninth MOS transistor, and a second resistor is further disposed between the drain of the sixth MOS transistor and the drain of the ninth MOS transistor.
According to some embodiments of the utility model, the first MOS transistor and the second MOS transistor are PMOS transistors, and the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor, the eighth MOS transistor and the ninth MOS transistor are NMOS transistors.
Additional aspects and advantages of the utility model will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model.
Drawings
The foregoing and/or additional aspects and advantages of the utility model will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a prior art pipelined analog-to-digital converter;
FIG. 2 is a timing diagram of the pipelined analog-to-digital converter shown in FIG. 1;
FIG. 3 is a schematic diagram of a pipelined analog-to-digital converter according to an embodiment of the present utility model;
FIG. 4 is a timing diagram of the pipelined analog-to-digital converter shown in FIG. 3;
FIG. 5 is a schematic diagram of a prior art dynamic amplifier;
FIG. 6 is a schematic diagram of a dynamic amplifier according to an embodiment of the present utility model;
FIG. 7 is a schematic diagram of a dynamic amplifier according to an embodiment of the present utility model;
reference numerals:
the sample-and-hold circuit 100, the sub-ADC 200, the sub-DAC 300, the dynamic amplifiers 400, yu Chasheng are formed into a circuit 500, an output register 600, a clock control unit 700.
Detailed Description
Reference will now be made in detail to the present embodiments of the present utility model, examples of which are illustrated in the accompanying drawings, wherein the accompanying drawings are used to supplement the description of the written description so that one can intuitively and intuitively understand each technical feature and overall technical scheme of the present utility model, but not to limit the scope of the present utility model.
In the description of the present utility model, a number means one or more, a number means two or more, and greater than, less than, exceeding, etc. are understood to not include the present number, and above, below, within, etc. are understood to include the present number. The description of the first and second is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present utility model, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present utility model can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
Fig. 1 is a schematic diagram of a pipelined analog-to-digital converter in the prior art. As shown in FIG. 1, the pipelined analog-to-digital converter is composed of M stages of pipeline units, each stage of pipeline unit has N-bit quantization precision, and M is a positive integer. Therefore, the pipelined analog-to-digital converter shares m×n bit precision, and the basic workflow is as follows:
1. the sample-hold unit samples the analog input signal and transmits the analog input signal to the pipeline with the required time t SAMP ；
2. An N-bit sub ADC in a pipeline unit quantizes an analog input signal, and the required time is t AD ；
3. The N-bit sub DAC in the pipeline unit generates a quantized feedback signal according to the quantized result of the sub ADC of the stage, and the required time is t DA ；
4. The analog input signal is subtracted from the quantized feedback signal to generate a residual signal, the required time is t FB ；
5. The dynamic amplifier amplifies the residual signal and transmits the residual signal to the next stage of pipeline unit, and the required time is t AMP Meanwhile, the next stage pipeline samples the amplified residual difference signal;
6. after the amplification process is completed, the current pipeline stage can be released and the next sample can be received. And meanwhile, the next stage pipeline unit quantizes the acquired amplified previous stage residual difference signal, namely, the steps 2-5 are repeated until the last stage pipeline unit finishes the quantization of the sample.
Fig. 2 shows the timing relationship of the pipelined analog-to-digital converter described above when in operation. When the pipelined analog-to-digital converter works, the steps are required to be sequentially executed in turn; at the same time, the total time consumption of each stage of pipeline unit is required to be less than a single main clock period so as to ensure that the pipeline unit is already accessed when the next sampling sample is inputAnd (3) releasing correctly. That is, the main clock period T of the pipelined analog-to-digital converter is not less than T SAMP +t AD +t DA +t FB +t AMP I.e. the primary clock frequency is not higher than
It can be seen that conventional pipelined analog-to-digital converters are limited by the implementation steps and the sampling rate is not fast enough.
As shown in fig. 3, a pipelined analog-to-digital converter according to an embodiment of the present utility model includes a multi-stage pipeline unit and an output register 600; each stage of pipeline unit comprises a sample-hold circuit 100, a sub-ADC 200, a sub-DAC 300, a dynamic amplifier 400 and a residual generating circuit 500, wherein the output end of the sample-hold circuit 100 is electrically connected with the input end of the sub-ADC 200 and the input end of the dynamic amplifier 400 respectively, the output end of the dynamic amplifier 400 is electrically connected with the first input end of the residual generating circuit 500, the output end of the sub-ADC 200 is electrically connected with the input end of the sub-DAC 300, and the output end of the sub-DAC 300 is electrically connected with the second input end of the residual generating circuit 500; the output end of each sub DAC300 is electrically connected to the input end of the output register 600; the output terminal of the clock control unit 700 is electrically connected to the input terminal of each sample-and-hold circuit 100.
As shown in fig. 3 and 4, a pipeline analog-to-digital converter according to an embodiment of the present utility model has the following specific workflow:
1. the sample-and-hold circuit 100 of the first stage pipeline unit samples the analog input signal and takes time t to input the analog input signal into the pipeline SAMP ；
2. The sub ADC200 of N-bit precision in the pipeline unit quantizes the analog input signal and transmits the quantized result to the output register 600 for latching; meanwhile, the dynamic amplifier 400 amplifies the analog input signal and transmits to the residual generation circuit 500; the time required for this process is t AD/AMP . In practical applications, the subsequent pipeline units Yu Chasheng are circuits except the first stage pipeline unit500 are integrated with the sample-and-hold circuit 100, that is, the dynamic amplifier 400 amplifies an analog input signal, and the next sample-and-hold circuit 100 can sample and hold the amplified analog input signal.
3. The sub DAC300 with N-bit precision in the pipeline unit generates a quantization feedback signal according to the quantization result of the sub ADC200 of the pipeline unit of this stage, and sends the quantization feedback signal to the Yu Chasheng unit 500, where the required time is t DA The method comprises the steps of carrying out a first treatment on the surface of the In order to match the quantized feedback signal with the amplified analog input signal, the sub-DAC 300 needs to use a large swing reference voltage in order to raise the swing of the output signal of the sub-DAC 300; after the quantization process and the amplification process of the analog input signal are completed, the pipeline unit of the stage can be released to wait for the input of the next sampling sample;
4. yu Chasheng the circuit 500 subtracts the quantized feedback signal from the analog input signal to produce a residual signal, which takes a time t FB The method comprises the steps of carrying out a first treatment on the surface of the Meanwhile, the sample hold circuit 100 of the next stage pipeline unit can sample and hold the residual signal;
5. after the residual signal is generated, the sub-ADC 200 and the dynamic amplifier 400 of the next stage pipeline are started, and steps 2-4 are repeated until the final stage pipeline unit finishes the quantization of the sample.
As can be seen from fig. 2, 4 and the above-described workflow, the sampling rate of the pipelined analog-to-digital converter of the present utility model is improved compared to the conventional pipelined analog-to-digital converter. According to the pipelined analog-to-digital converter, the quantization process and the amplification process of the pipeline units are decoupled by adopting the improved residual generation strategy, so that the two processes can be parallelized for operation, the time required by each pipeline unit is saved, and the operation speed of the whole system is improved. The pipelined analog-to-digital converter can improve the operation rate of the single-channel ADC to the gigahertz range, has expandability, can further expand the conversion rate through a time interleaving technology, or can increase the length of the pipeline, and can improve the single-stage quantization precision and other schemes to expand the quantization precision.
The pipelined analog-to-digital converter according to an embodiment of the present utility model further comprises a clock control unit 700, the clock control unit 700 being configured to provide a clock signal to each sample-and-hold circuit 100 for controlling the operating state of the sample-and-hold circuit 100.
For pipelined analog-to-digital converters, the power consumption of the dynamic amplifier is the primary source of power consumption; therefore, in order to reduce the power consumption of the pipelined analog-to-digital converter, the structure of the dynamic amplifier needs to be improved to reduce the power consumption thereof. Fig. 5 is a schematic diagram of a conventional dynamic amplifier, which is composed of a class-a differential pair (class-A differential pair, i.e., MSO transistors M3 and M4), a pair of PMOS reset switches (i.e., MOS transistors M1 and M2), and a load capacitor (not shown). The differential currents generated by differential pairs of class A are, as known from the derivation in the literature "M.S.Akter, R.Sehgal, F.van der Goes, K.A.A. Makinwa and K.Bult," A66-dB SNDR Pipelined Split-ADC in 40-nm CMOS Using a Class-AB Residue Amplifier, "in IEEE Journal of Solid-State Circuits, vol.53, no.10, pp.2939-2950, oct.2018", appendix C:
the nonlinear characteristic is mainly derived from the compression characteristic of the differential current under the large swing. In order to improve the linearity of the dynamic amplifier, as shown in fig. 6, the dynamic amplifier 400 of the present utility model is improved on the conventional dynamic amplifier by adding a nonlinear current source to provide an additional discharge current having a high-order correlation with the input signal to the output differential pair, thereby compensating the high-order output correlation term (i.e., (V) I+ -V I- ) 2 ) Thereby improving the compression characteristics of the dynamic amplifier 400 at large swings and further improving the linearity thereof. Further, the method may also be combined with source degeneration techniques (source degeneration) to further improve linearity; in the implementation process, a negative feedback loop is formed by adding source resistors R1 and R2, so as to reduce the variation of the amplification gain of the dynamic amplifier 400And (5) melting.
Specifically, please refer to fig. 7 for the structure of the dynamic amplifier 400 of the present utility model. The dynamic amplifier 400 according to the present utility model includes: the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, the sixth MOS transistor M6, the seventh MOS transistor M7, the eighth MOS transistor M8 and the ninth MOS transistor M9; the gates of M1 and M2 are connected with a main amplification clock signal CK, the source electrode of M1 is electrically connected with the source electrode of M2, the drain electrode of M1 is electrically connected with the drain electrode of M3, and the drain electrode of M2 is electrically connected with the drain electrode of M4; the grid electrode of M3 is connected with the positive end input voltage V I+ A positive voltage output port V is arranged between the drain electrode of M3 and the drain electrode of M1 O+ The method comprises the steps of carrying out a first treatment on the surface of the M4 has its gate connected to negative voltage input port V I- A negative voltage output port V is arranged between the drain electrode of M4 and the drain electrode of M2 O- The method comprises the steps of carrying out a first treatment on the surface of the The grid electrode of M5 is connected with the positive end input voltage V I+ The drain electrode of M5 is electrically connected with the source electrode of M3; the grid of M6 is connected with negative input voltage V I- The drain electrode of M6 is electrically connected with the source electrode of M4; the grid electrodes of M7, M8 and M9 are connected with a main amplification clock signal CK, the drain electrode of M7 is electrically connected with the source electrode of M5, and the source electrode of M7 is grounded; the drain electrode of M8 is electrically connected with the source electrode of M6, and the source electrode of M8 is grounded; the drain electrode of M9 is electrically connected with the drain electrode of M5 and the drain electrode of M6 respectively, and the source electrode of M9 is grounded. M1 and M2 are PMOS tubes, and M3-M9 are NMOS tubes. Further, a first resistor R1 is further disposed between the drain electrode of M5 and the drain electrode of M9, and a second resistor R2 is further disposed between the drain electrode of M6 and the drain electrode of M9.
According to the dynamic amplifier 400 disclosed by the utility model, the low power consumption characteristic of the dynamic amplifier 400 can be fully utilized by improving the linearity, and a high-precision and low-power consumption solution is provided for the dynamic amplifier 400 in the pipelined analog-to-digital converter.
In the description of the present specification, a description referring to the terms "one embodiment," "further embodiment," "some specific embodiments," or "some examples," etc., means that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present utility model have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the utility model, the scope of which is defined by the claims and their equivalents.
Claims (5)
1. A pipelined analog-to-digital converter comprising:
the multi-stage pipeline unit comprises a sampling hold circuit, a sub-ADC, a sub-DAC, a dynamic amplifier and a Yu Chasheng circuit, wherein the output end of the sampling hold circuit is electrically connected with the input end of the sub-ADC and the input end of the dynamic amplifier respectively, the output end of the dynamic amplifier is electrically connected with the first input end of the Yu Chasheng circuit, the output end of the sub-ADC is electrically connected with the input end of the sub-DAC, and the output end of the sub-DAC is electrically connected with the second input end of the Yu Chasheng circuit;
and the output end of each sub DAC is electrically connected with the input end of the output register respectively.
2. The pipelined analog-to-digital converter of claim 1 further comprising a clock control unit for providing a clock signal to each of said sample-and-hold circuits.
3. The pipelined analog-to-digital converter of claim 1 wherein said dynamic amplifier comprises:
the grid electrode of the first MOS tube is connected with a main amplification clock signal;
the source electrode of the second MOS tube is electrically connected with the source electrode of the first MOS tube;
the grid electrode of the third MOS tube is connected with positive end input voltage, the drain electrode of the third MOS tube is electrically connected with the drain electrode of the first MOS tube, and a positive end voltage output port is arranged between the drain electrode of the third MOS tube and the drain electrode of the first MOS tube;
the grid electrode of the fourth MOS tube is connected with negative end input voltage, the drain electrode of the fourth MOS tube is electrically connected with the drain electrode of the second MOS tube, and a negative end voltage output port is arranged between the drain electrode of the fourth MOS tube and the drain electrode of the second MOS tube;
a fifth MOS tube, wherein the grid electrode of the fifth MOS tube is connected with the positive end input voltage, and the drain electrode of the fifth MOS tube is electrically connected with the source electrode of the third MOS tube;
a sixth MOS tube, wherein the grid electrode of the sixth MOS tube is connected with the negative end input voltage, and the drain electrode of the sixth MOS tube is electrically connected with the source electrode of the fourth MOS tube;
a seventh MOS tube, wherein the grid electrode of the seventh MOS tube is connected with the main amplification clock signal, the drain electrode of the seventh MOS tube is electrically connected with the source electrode of the fifth MOS tube, and the source electrode of the seventh MOS tube is grounded;
the grid electrode of the eighth MOS tube is connected with the main amplification clock signal, the drain electrode of the eighth MOS tube is electrically connected with the source electrode of the sixth MOS tube, and the source electrode of the eighth MOS tube is grounded;
and the grid electrode of the ninth MOS tube is connected with the main amplification clock signal, the drain electrode of the ninth MOS tube is respectively and electrically connected with the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube, and the source electrode of the ninth MOS tube is grounded.
4. The pipelined analog-to-digital converter of claim 3 wherein a first resistor is further disposed between a drain of said fifth MOS transistor and a drain of said ninth MOS transistor, and a second resistor is further disposed between a drain of said sixth MOS transistor and a drain of said ninth MOS transistor.
5. The pipelined analog-to-digital converter of claim 3 or 4 wherein the first and second MOS transistors are PMOS transistors, and the third, fourth, fifth, sixth, seventh, eighth and ninth MOS transistors are NMOS transistors.
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