CN104702282B - The digital calibrating method and circuit of multistage many bit sub-circuits in analog-digital converter - Google Patents
The digital calibrating method and circuit of multistage many bit sub-circuits in analog-digital converter Download PDFInfo
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Abstract
The present invention relates to a kind of digital calibrating method of multistage many bit sub-circuits in analog-digital converter, first, design peripheral control circuits, control ADC working condition, it is controlled its sub- pipelining-stage circuit calibrated to needs, and to there is being read out with error output for each sub- level in the register inside ADC, carry out error calculation, obtained error amount will be calculated, it is deposited into ADC internal registers, the error compensation for being calculated each sub- level by Data Synthesis module completes calibration into last output.Main advantages of the present invention are to propose a kind of Capacitor Mismatch Calibration of multistage many bit sub-circuits, and use digital circuit.Calibration control flow is realized outside the piece of analog-digital converter, reduces the complexity of whole Design of A/D Converter, and calibration method is easy to be reliable, and calibration effect is good.
Description
Technical field
It is multistage many in field, more particularly to a kind of production line analog-digital converter with manufacturing the invention belongs to IC design
The digital calibrating method and circuit of bit sub-circuit.
Background technology
With developing rapidly for microprocessor and signal processing technology, to analog-digital converter (Analog-to-Digital
Converter, ADC) performance requirement more and more higher.High-speed high-precision flow line ADC is fast with its conversion speed, high resolution,
Low in energy consumption the characteristics of, it is widely used in field of signal processing.On the other hand, with the high speed development of integrated circuit technology, device
Size it is less and less, the operating rate of device is further lifted, and power consumption is further reduced.But, caused by size reduction
Device mismatch is increasingly severe, when the precision of pipeline ADC brings up to more than 12bit, and electric capacity loses caused by the deviation of technique
Match somebody with somebody, the imperfection of amplifier, the generation of comparator imbalance equal error, can not have been set using the design method of conventional analog circuits
Count out high performance ADC.The data exported using the method for digital calibration to analog sampling circuit carry out error correction, can be effective
The error that the deviation of ground compensation technique is brought, improves the performance of pipeline ADC.In high-speed high-precision flow line ADC research,
The sub- level ADC of every grade of traditional single bits structures, which is realized, will significantly improve the overall power of chip, increase the area of chip.For
Reduction sampling capacitance, reduces power consumption, reduces noise, in chopped-off head and what preceding sub- ADC must use many bit architectures.Comparing more
In the sub- level ADC of special structure, the capacitance mismatch of comparator will produce nonlinearity erron, have impact on the dynamic property of converter,
Error caused by needing level ADC to many bits capacitance mismatch is calibrated.
As shown in figure 1, pipeline ADC is by clock generating circuit, pipeline conversion structure, delay alignment register array and
Digital calibration circuit is constituted, and wherein pipeline conversion structure is input sample holding circuit (SHA, Sample-Hold
Amplifier) constituted with n level conversions circuits cascading.The sub- level conversion circuit of each streamline includes 1 sub- ADC (SADC) and 1
Surplus gain digital analog converter (MDAC, Multiplying Digital to Analog Converter).Entering line number
When mould is changed, sampling hold circuit is sampled in sampling relative input signal, is then keeping opposite stage1 outputs, as
SHA circuits in 1st grade of input voltage Vi, stage1 are sampled and kept to Vi, are turned while SADC carries out A/D to Vi
Change, obtain k1bit transformation results and be output to as this level conversion result in delay alignment register array, and be used as SADC's
Numeral input is to realize the quantitative estimation to Vi, and analog subtraction circuit realiration Vi makees poor with k1bit estimates, and obtained difference exists
Amplification amplifies 2 by amplifierk1-1Exported after times as the simulation output Vo of this grade to stage2.Remaining grade of circuit and the 1st
Level work process is similar.
Fig. 2 is the transfer curve of 1.5bit grades of circuits, 3 kinds of digital codes of circuit output of 1.5bit structures, when this
It is 00 that level input, which is less than this grade of output code of Vr/4,.When the input of this level is between [- Vr/4, Vr/4], this grade of output code is
01.When the input of this level is more than Vr/4, this grade of output code is 10.Band is mismatched by electric capacity by being calculated in two turning points
The error come, then again by the error compensation, obtains the output of linear relationship, the curve of output after calibration as shown in Figure 3.
Because the electric capacity number that the sub- level ADC of many bits is used is more, the comparison point of comparator is numerous, is realized using analog circuit
Method will cause circuit extremely complex, and power consumption and area are significantly greatly increased.And existing 1.5bit grades of sub- ADC digital calibration skill
Although art possesses preferable calibration effect, but can not meet many sub- level structure streamlines of bit of high accuracy ADC designs will
Ask.Invent a kind of implementation method simple, realize that circuit is easy, high multistage, many bit-level sub-circuit calibration method of calibration efficiency
Seem and be highly desirable to.
The content of the invention
For problem above, the invention provides a kind of numeral for the multistage many sub- level ADC of bit for being easy to digital circuit
Calibration method and circuit.
The present invention provides a kind of calibration method of the sub- level comparator capacitance mismatch of 3.5bit, multistage calibration is carried out, to reality
Now error caused by capacitance mismatch is corrected, error calculation is realized outside piece, circuit simple and convenient, calibration effect is good, with
The change of the external environments such as temperature, voltage is smaller.
The digital calibrating method of multistage many bit sub-circuits in a kind of analog-digital converter, the pipeline ADC is comprising multiple
Pipelining-stage, each pipelining-stage includes sub- ADC, sub- DAC, amplifier and subtracter, and analog input signal Vi is input in sub- ADC
Row quantifies to produce numeral output, and digital-to-analogue conversion is carried out in sub- DAC while the numeral output is sent into, and exports analog quantity, will simulate
Input signal Vi and the output analog quantity carry out subtraction in subtracter, then obtain after amplifier amplifies output electricity
Press Vo, as MDAC output.Sub- DAC, adder and amplifier have collectively constituted MADC.
Because the MDAC in circuit uses differential configuration output, differential comparator is used.As shown in figure 4, setting
Qp, qn are the difference output of comparator level, and law of conservation of charge is used for same virtual earth point：
(a) qp=0 is worked as, during qn=1, VreftSwitch OFF, VrefbSwitch closure, comparator is output as 0.If x1, x2 distinguish
For amplifier differential output pair, VL1And VL2Common mode electrical level during for direct current.
If virtual earth point voltage is 0, equation below is obtained by charge conservation for ina points:
(0-VL1)·C1.1+(0-VL2)·2Cx1=(0-Vrefb)·C1.1+(0-x1)·2Cx1 (1)
It can derive：
Similarly for inb points,
(0-VL1)·C2.1+(0-VL2)·2Cx2=(0-Vreft)·C2.1+(0-x2)·2Cx2 (3)
It can derive：
Amplifier analog differential output when first comparison point is output as 0 is obtained by (2) and (4),
It is similar for other comparison point derivation formulas.
(b) qp=1 is worked as, during qn=0, VreftSwitch closure, VrefbSwitch OFF, comparator is output as 1.
The difference output of each comparison point can be obtained according to above-mentioned analysis：
It is similar for other comparison point derivation formulas.
Fig. 5 is the transference curve of 3.5bit grades of circuits, there is 16 comparison points as can be seen from Fig..3.5bit grades of son electricity
The digital coding of each comparator output interval of road output is 0000~1111, interval for the 1st：
Coding is output as 0000, qp [15:0]=16 ' h0000, qn [15:0]=16 ' hffff, sub-circuit is output as：
It is interval for the 2nd：
Coding is output as 0001, qp [15:0]=16 ' h0001, qn [15:0]=16 ' hfffe, sub-circuit is output as：
Output for the 3rd to the 16th interval is similar
Formula (7) is subtracted by formula (8) can obtain：
VoutB-VoutA=Vdiff16.1-Vdiff16.0≈1 (9)
It can be from which further followed that with reference to above-mentioned analysis：
In the ideal case, electric capacity C1.16Equal to Cx1, C2.16Equal to Cx2, the right and left of formula (9) is essentially equal.Actual work
When making, due to the non-ideal type C of device1.16And Cx1, C2.16And Cx2It is inconsistent, cause sub- ADC output to there is error.
Obtain the error amount at the comparison point：
Error=(Vdiff16.1-Vdiff16.0)-1 (11)
After the error amount is compensated, error amount of the area than remaining relatively point is calculated with same method.For 1.5 bit-levels electricity
The capacitor mismatch calibration on road, can also use this technical scheme.
According to the analysis of above-mentioned technical method, the digital calibration of multistage many bit sub-circuits in the analog-digital converter is drawn
Circuit, including：1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, pulse-generating circuit, calibration value measurement electricity
Road, data synthesis circuit, clock generation circuit, SPI register circuits and chip periphery control circuit.Wherein peripheral control circuits
Including SPI control circuit, calibration controls circuit and calibration value counting circuit.
Its specific technical scheme is：In order to solve problem above, the invention provides multistage many in a kind of analog-digital converter
The digital calibrating method and circuit of bit sub-circuit.
The digital calibrating method of multistage many bit sub-circuits in a kind of analog-digital converter, it is characterised in that：
The first step：The initialization of calibration control word first in peripheral control circuits, the effective situation of signal is enabled in calibration
Under, into circulation, cycle-index is the number of the comparison point of sub-circuit；Peripheral control circuits send the interval code of pressure so that son
Comparator in MDAC is in corresponding operation interval；Analog circuit is received after this code, obtains the output numeral of this current grade
Code, digital calibration circuit receives the digital code of this grade, and the data that the digital code of multistage sub-circuit is completed by data synthesis circuit are closed
Into, obtain current ADC numeral output, completed by parameter value of the calibration value measuring circuit in SPI register circuits work as
The accumulating operation of quantized value at preceding comparison point, and store into SPI register circuits；Peripheral control circuits read the accumulated value,
Carry out error op and take the mean, obtain the calibration value relatively pointed out, and the calibration value is written to SPI register circuits
In, calculated subsequently into the error amount of next comparison point；After this grade of sub-circuit calibration is completed, by error amount compensation to number
According in the output of combiner circuit, the calibration of next stage sub-circuit is carried out；
Second step：Peripheral control circuits complete the flow that calibrates for error of preceding 3 grades of sub-circuits according to the flow described in the first step
Control；First using 4~m grades of sub-circuits as ideal circuit, its m >=4 calibrates 3rd level, obtains the calibration value and benefit of 3rd level
Repay, then using 3~m grades of sub-circuits as ideal circuit, calibrate the 2nd grade, obtain the 2nd grade of calibration value and compensation, then by 2~m grades
Sub-circuit calibrates the 1st grade as ideal circuit, obtains the 1st grade of calibration value post-compensation, is finally completed the calibration of whole circuit.
The digital calibration circuit of multistage many bit sub-circuits in a kind of analog-digital converter, it is characterised in that：Including digital school
Quasi- circuit, SPI register circuits, peripheral control circuits；Digital calibration circuit, SPI register circuits, peripheral control circuits are set
In chip periphery；
The input of the digital calibration circuit for analog circuit quantized value and SPI register circuits controlling value, it is defeated
It is the output without calibration output accumulated value and the analog-digital converter after calibration to go out end；
The peripheral control circuits are used to control calibration flow, the SPI register circuit read-write capabilitys of calibration parameter；
The SPI register circuits are used to deposit the parameter needed for analog circuit and digital calibration circuit, and storage modulus turns
The status signal of parallel operation internal circuit, based on the working condition and calibration value at different levels of the reading chip of peripheral control circuits
Calculate.
The digital calibration circuit includes clock generation circuit, pulse-generating circuit, calibration value measuring circuit, the 1st grade of drive
It is dynamic
Circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit；
The clock generation circuit, the control signal for receiving SPI register circuits produces gated clock, to pulse
Generation circuit, calibration value measuring circuit, the 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, Data Synthesis electricity
Road provides controllable clock, and the circuit for being not at working condition can close clock, be at resting state, reduces
Power consumption.
The stage drive circuit of digital calibration the 1st：Control signal for receiving SPI register circuits, according to simulation electricity
Sequential needed for road produces the pressure control signal needed for the 1st grade of comparator circuit output of analog circuit；
The stage drive circuit of digital calibration the 2nd：Control signal for receiving SPI register circuits, according to simulation electricity
Sequential needed for road produces the pressure control signal needed for the 2nd grade of comparator circuit output of analog circuit；
The digital calibration 3rd level drive circuit：Control signal for receiving SPI register circuits, according to simulation electricity
Sequential needed for road produces the pressure control signal needed for the output of analog circuit 3rd level comparator circuit；
The pulse-generating circuit：Control signal for receiving SPI register circuits, the numeral of the pulse width variability of generation
Signal, SECO and the accumulation calculating of calibration value measuring circuit for data synthesis circuit；
The calibration value measuring circuit：Control signal for receiving SPI register circuits, to the numeral after Data Synthesis
Signal carries out summation operation, and result is stored in into SPI register circuits.
The data synthesis circuit：For each sub- level circuit digital in pipeline ADC to be exported, it is encoded after according to prolonging
When aligned array sequential carry out Data Synthesis and receive the calibration value in SPI register circuits, carry out compensation for calibrating errors, produce final
Analog-digital converter output.
The peripheral control circuits include SPI configuration circuits, calibrate Row control circuit, calibration value counting circuit；
Described SPI configuration circuits, the running parameter for configuring digital calibration circuit reads digital calibration circuit and produced
Accumulated value be used for error calculation, to needed for ADC internal analogue circuits control signal configuration and to the work shape of analog circuit
State is read out；
The calibration control circuit is used for carrying out the control of the align mode inside adc circuit, according to needed for analog circuit
Sequential relationship send the control codes of respective bins, and the circuit output in each subinterval control, in addition, also carrying out 3
Calibrate the control that sub- level calibrates flow.
The calibration value counting circuit is that the accumulated value read according to SPI configuration circuits carries out doing difference operation, obtains each
The average value of error amount at comparison point, and error amount at each comparison point is deposited into SPI configuration circuits, for ADC
The compensation of circuit internal calibrators.
Described calibrate controls the calibration control flow of circuit to be：Initialization of calibration is controlled first in peripheral control circuits
Word, in the case of calibration enable signal is effective, into circulation, cycle-index is the number of the comparison point of sub-circuit；Contain outside
Circuit processed sends the interval code of pressure so that the comparator in sub- MDAC is in corresponding operation interval；Analog circuit receives this
After code, the output digital code of this current grade is obtained, digital calibration circuit receives the digital code of this grade, completed by data synthesis circuit
The Data Synthesis of the digital code of multistage sub-circuit, obtains current ADC numeral output, is posted by calibration value measuring circuit according to SPI
Parameter value in latch circuit completes the accumulating operation of quantized value at current comparison point, and stores into SPI register circuits；
Peripheral control circuits read the accumulated value, carry out error op and take the mean, obtain the calibration value relatively pointed out, and should
Calibration value is written in SPI register circuits, is calculated subsequently into the error amount of next comparison point；When this grade of sub-circuit calibration
After completion, by error amount compensation into the output of data synthesis circuit, the calibration of next stage sub-circuit is carried out；
Peripheral control circuits complete the Row control that calibrates for error of preceding 3 grades of sub-circuits according to the flow described in the first step；It is first
First using 4~m grades of sub-circuits as ideal circuit, 3rd level is calibrated in its m >=4, obtains calibration value and the compensation of 3rd level, then by 3
~m grades of sub-circuits calibrate the 2nd grade as ideal circuit, obtain the 2nd grade of calibration value and compensation, then 2~m grades of sub-circuits are made
For ideal circuit, the 1st grade is calibrated, the 1st grade of calibration value post-compensation is obtained, is finally completed the calibration of whole circuit.
Main advantages of the present invention are to propose a kind of Capacitor Mismatch Calibration of multistage many bit sub-circuits, and are used
Digital circuit.Calibration control flow is realized outside the piece of analog-digital converter, reduces the complexity of whole Design of A/D Converter
Degree, calibration method is easy to be reliable, and calibration effect is good.
1st, there is provided a kind of multistage many sub- level ADC of bit Capacitor Mismatch Calibration.
2nd, there is provided the calibration method of a kind of outer error calculation, the scale and complexity of digital circuit in design can be reduced
Degree.
3rd, calibration circuit can be designed applied to HIGH-SPEED HIGH-ACCURACY A/D CONVERTER, improves the dynamic property of chip.
4th, new generation High Speed High Precision ADC chip or SOC on the basis of achievement of the present invention and experience, drop
The complexity of low chip, and the Performance And Reliability of product can be improved.
Brief description of the drawings
Fig. 1 is the system structure diagram of typical pipeline ADC
Fig. 2 is the transmission characteristic schematic diagram of 1.5 bit-level circuits.
Fig. 3 is curve of output schematic diagram when there is error between level.
Fig. 4 is 3.5bit grades of sub-circuit structural representations.
Fig. 5 illustrates for the transmission characteristic of 3.5 bit-level circuits.
Fig. 6 is that digital calibration circuit realizes schematic diagram.
Fig. 7 delay alignment register array schematic diagrames.
Fig. 8 is that the bit sub-circuit of single-stage 3.5 calibrates schematic flow sheet.
Fig. 9 is 3 grades of sub- pipelining-stage calibration schematic flow sheets.
Embodiment
Below so that the tactile son of metal is vane type as an example, and Structure Figure, the present invention is described in further detail.
The invention provides a kind of digital calibrating method of the pipeline ADC of multistage many bit architectures, calibration flow is：It is first
First, peripheral control circuits are designed, ADC working condition is controlled, controls its sub- pipelining-stage circuit calibrated to needs
System, and to there is being read out with error output for each sub- level in the register inside ADC, carrying out error calculation, will count
Obtained error amount, is deposited into ADC internal registers, the error compensation for being calculated each sub- level by Data Synthesis module
Into last output, calibration is completed.
N is 11 in the structure chart of this pipeline ADC shown in Fig. 1, the present invention.Wherein, k1 and k2 is 3.5 bit architectures, k3
It is 1.5 bit architectures to k11.The present invention influences larger the 1st grade on error caused by capacitance mismatch, and the 2nd grade, 3rd level is carried out
Calibration.
Fig. 5 show the transmission curve of the 3.5bit of the 1st grade of sub-circuit and the 2nd grade of sub-circuit in the present invention.3.5 bits
Circuit comparator exports 17 kinds of output codes, and 16 are respectively 0000~1111 and 1 negative value output c0 on the occasion of output c1~c16
For 1111 (to prevent from overflowing increased 1 Interval Coding), corresponding is 17 output intervals and 16 comparison points.Due to
There is the capacitance mismatch of comparator at each comparison point, for the 1st comparison point, calibration circuit tries to achieve y0 points and y1 respectively
The accumulated value of point, by asking difference operation to draw the 1st comparison point error amount error1, after the error amount is compensated, then tries to achieve the 2nd
Error amount error2 at individual comparison point, similarly obtains error amount error3~error16 at the 3rd to 16 comparison point.
As shown in fig. 6, the invention provides a kind of digital calibration circuit of multistage many bit sub-circuits in analog-digital converter,
Its chip internal includes digital calibration circuit, SPI register circuits；Chip periphery includes peripheral control circuits.
The input of the digital calibration circuit for analog circuit quantized value and SPI register circuits controlling value, it is defeated
Go out the output that end is the accumulated value and the analog-digital converter after calibration without calibration output；
The peripheral control circuits are used to control calibration flow, the SPI register circuit read-write capabilitys of calibration parameter；
The SPI register circuits turn for depositing the parameter needed for analog circuit sum deposits calibration circuit, storage modulus
The status signal of parallel operation internal circuit, based on the working condition and calibration value at different levels of the reading chip of peripheral control circuits
Calculate；
The digital calibration circuit includes clock generation circuit, pulse-generating circuit, calibration value measuring circuit, the 1st grade of drive
Dynamic circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit；
The clock generation circuit, the control signal for receiving SPI register circuits produces gated clock, to pulse
Generation circuit, calibration value measuring circuit, the 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, Data Synthesis electricity
Road provides controllable clock, and the circuit for being not at working condition can close clock, be at resting state；
The stage drive circuit of digital calibration the 1st：Control signal for receiving SPI register circuits, according to simulation electricity
Sequential needed for road produces the pressure control signal needed for the 1st grade of comparator circuit output of analog circuit；
The stage drive circuit of digital calibration the 2nd：Control signal for receiving SPI register circuits, according to simulation electricity
Sequential needed for road produces the pressure control signal needed for the 2nd grade of comparator circuit output of analog circuit；
The digital calibration 3rd level drive circuit：The control signal of circuit is controlled for receiving SPI registers, according to mould
Sequential needed for intending circuit produces the pressure control signal needed for the output of analog circuit 3rd level comparator circuit；
The pulse-generating circuit：Control signal for receiving SPI register circuits, the numeral of the pulse width variability of generation
Signal, SECO and the accumulation calculating of calibration value measuring circuit for data synthesis circuit；
The calibration value measuring circuit：Control signal for receiving SPI register circuits, to the numeral after Data Synthesis
Signal carries out summation operation, and result is stored in into SPI register circuits.
The data synthesis circuit：For each sub- level circuit digital output in pipeline ADC to be passed through after coding circuit, press
Data Synthesis is carried out according to the delay aligned array sequential in the present invention, and receives the calibration value in SPI register circuits, school is carried out
Quasi- compensation, produces the output of final analog-digital converter.Fig. 7 is the delay alignment circuit of the pipeline ADC of the present invention, wherein the
1 grade identical with the delay of the 2nd grade of circuit, 3rd level and the 4th grade of delay the 1st, 2 grades of clock cycle, the 5th grade and the 6th grade delay
3rd, 4 grades of clock cycle, the 7th grade and the 8th grade delay the 5th, 6 grades of clock cycle, the 9th grade and the 10th grade postpone the 7th,
8 grades of clock cycle, the 11st grade of delay the 9th, 10 grades of clock cycle.The data synthesis circuit will also calculate 3 obtained
The error amount of level circuit is compensated into the circuit, and the control signal for controlling circuit always according to register carries out output gain adjustment.
The peripheral control circuits include SPI configuration circuits, calibrate Row control circuit, calibration value counting circuit；
Described SPI configuration circuits, the running parameter for configuring digital calibration circuit reads digital calibration circuit and produced
Accumulated value be used for error calculation, to needed for ADC internal analogue circuits control signal configuration and to the work shape of analog circuit
State is read out；
The calibration Row control circuit, for carrying out the control of the align mode inside adc circuit, for according to this hair
Flow shown in bright middle Fig. 8 and Fig. 9, the control code of respective bins is sent according to the sequential relationship needed for analog circuit, and respectively
The control of the circuit output in individual subinterval, in addition, also carrying out the control that 3 sub- levels of calibration calibrate flow.
The calibration value counting circuit is that the accumulated value read according to SPI configuration circuits carries out doing difference operation, obtains each
The average value of error amount at comparison point, and error amount at each comparison point is deposited into SPI configuration circuits, for ADC
The compensation of circuit internal calibrators.
Fig. 8 is the bit sub-circuit of single-stage 3.5 calibration flow, the initialization of calibration control word first in peripheral control circuits,
In the case of calibration enable signal is effective, into circulation, cycle-index is the number of the comparison point of sub-circuit；Peripheral control electricity
Road sends the interval code of pressure so that the comparator in sub- MDAC is in corresponding operation interval；Analog circuit is received after this code,
The output digital code of this current grade is obtained, digital calibration circuit receives the digital code of this grade, complete multistage by data synthesis circuit
The Data Synthesis of the digital code of sub-circuit, obtains current ADC numeral output, by calibration value measuring circuit according to SPI registers
Parameter value in circuit completes the accumulating operation of quantized value at current comparison point, and stores into SPI register circuits；Periphery
Control circuit reads the accumulated value, carries out error op and takes the mean, obtains the calibration value relatively pointed out, and this is calibrated
Value is written in SPI register circuits, is calculated subsequently into the error amount of next comparison point；When this grade of sub-circuit calibration is completed
Afterwards, error amount compensation is subjected to the calibration of next stage sub-circuit into the output of data synthesis circuit；
Fig. 9 is the calibration Row control of preceding 3 grades of sub-circuits, before peripheral control circuits are completed according to the flow described in the first step
The Row control that calibrates for error of 3 grades of sub-circuits；It regard 4~m grades of sub-circuits as ideal circuit, its m >=4, calibration the 3rd first
Level, obtains calibration value and the compensation of 3rd level, then using 3~m grades of sub-circuits as ideal circuit, calibrates the 2nd grade, obtain the 2nd grade
Calibration value is simultaneously compensated, then using 2~m grades of sub-circuits as ideal circuit, calibrates the 1st grade, obtains the 1st grade of calibration value post-compensation,
It is finally completed the calibration of whole circuit.
The preferred embodiments of the present invention are the foregoing is only, the present invention is not restricted to, for the technology of this area
For personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included within scope of the presently claimed invention.
Claims (5)
1. the digital calibrating method of multistage many bit sub-circuits in a kind of analog-digital converter, it is characterised in that：
The first step：The initialization of calibration control word first in peripheral control circuits, in the case of calibration enable signal is effective, enters
Enter circulation, cycle-index is the number of the comparison point of sub-circuit；Peripheral control circuits send the interval code of pressure so that in sub- MDAC
Comparator be in corresponding operation interval；Analog circuit is received after this code, obtains the output digital code of this current grade, numeral
Calibration circuit receives the digital code of this grade, and the Data Synthesis of the digital code of multistage sub-circuit is completed by data synthesis circuit, is obtained
Current ADC numeral output, current comparison point is completed by parameter value of the calibration value measuring circuit in SPI register circuits
Locate the accumulating operation of quantized value, and store into SPI register circuits；Peripheral control circuits read accumulated value, carry out error fortune
Calculate and take the mean, obtain the calibration value of the comparison point, and the calibration value is written in SPI register circuits, subsequently into
The error amount of next comparison point is calculated；After this grade of sub-circuit calibration is completed, data synthesis circuit is arrived into error amount compensation
Output in, carry out next stage sub-circuit calibration；
Second step：Peripheral control circuits complete the Row control that calibrates for error of preceding 3 grades of sub-circuits according to the first step；First by the 4th ~
M grades of sub-circuits calibrate 3rd level as ideal circuit, its m >=4, obtain calibration value and the compensation of 3rd level, then 3 ~ m grades of sons are electric
Road calibrates the 2nd grade as ideal circuit, obtains the 2nd grade of calibration value and compensation, then using 2 ~ m grades of sub-circuits as ideal circuit,
The 1st grade is calibrated, the 1st grade of calibration value post-compensation is obtained, is finally completed the calibration of whole circuit.
2. the digital calibration circuit of multistage many bit sub-circuits in a kind of analog-digital converter, it is characterised in that：Including digital calibration
Circuit, SPI register circuits, peripheral control circuits；Digital calibration circuit, SPI register circuits are arranged in chip, are contained outside
Circuit processed is arranged on chip periphery；
The input of the digital calibration circuit is the quantized value of analog circuit and the controlling value of SPI register circuits, output end
For without calibration, the output of the accumulated value of output and the analog-digital converter after calibration；
The peripheral control circuits are used to control calibration flow, the SPI register circuit read-write capabilitys of calibration parameter；
The SPI register circuits are used to deposit the parameter needed for analog circuit and digital calibration circuit, store analog-digital converter
The status signal of internal circuit, working condition and the calculating of calibration value at different levels for the reading chip of peripheral control circuits.
3. the digital calibration circuit of multistage many bit sub-circuits in analog-digital converter according to claim 2, its feature exists
In：The digital calibration circuit includes clock generation circuit, pulse-generating circuit, calibration value measuring circuit, the 1st grade of driving electricity
Road, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit；
The clock generation circuit, the control signal for receiving SPI register circuits produces gated clock, to pulses generation
Circuit, calibration value measuring circuit, the 1st stage drive circuit, the 2nd stage drive circuit, 3rd level drive circuit, data synthesis circuit is carried
For controllable clock, the circuit for being not at working condition can close clock, be at resting state；
The stage drive circuit of digital calibration the 1st：Control signal for receiving SPI register circuits, according to analog circuit institute
The sequential needed produces the pressure control signal needed for the 1st grade of comparator circuit output of analog circuit；
The stage drive circuit of digital calibration the 2nd：Control signal for receiving SPI register circuits, according to analog circuit institute
The sequential needed produces the pressure control signal needed for the 2nd grade of comparator circuit output of analog circuit；
The digital calibration 3rd level drive circuit：Control signal for receiving SPI register circuits, according to analog circuit institute
The sequential needed produces the pressure control signal needed for the output of analog circuit 3rd level comparator circuit；
The pulse-generating circuit：The control signal of circuit, the numeral of the pulse width variability of generation are controlled for receiving SPI registers
Signal, SECO and the accumulation calculating of calibration value measuring circuit for data synthesis circuit；
The calibration value measuring circuit：The control signal of circuit is controlled for receiving register, the numeral after Data Synthesis is believed
Number carry out summation operation, result is stored in SPI register circuits；
The data synthesis circuit：For each sub- level circuit digital in pipeline ADC to be exported, it is encoded after, according to delay
Aligned array sequential carries out Data Synthesis, and receives the calibration value in SPI register circuits, carries out compensation for calibrating errors, produces final
Analog-digital converter output.
4. the digital calibration circuit of multistage many bit sub-circuits in analog-digital converter according to claim 2, its feature exists
In：The peripheral control circuits include SPI configuration circuits, calibrate Row control circuit, calibration value counting circuit；
Described SPI configuration circuits, the running parameter for configuring digital calibration circuit reads the tired of digital calibration circuit generation
It is value added to be used for error calculation, the control signal needed for ADC internal analogue circuits is configured and the working condition of analog circuit is entered
Row is read；
The calibration control circuit is used for carrying out the control of align mode inside adc circuit, according to needed for analog circuit when
Order relation sends the control code of respective bins, and the circuit output in each subinterval control, in addition, also carrying out 3 calibrations
Sub- level calibrates the control of flow；
The calibration value counting circuit is that the accumulated value read according to SPI configuration circuits carries out doing difference operation, obtains each and compares
The average value of error amount at point, and error amount at each comparison point is deposited into SPI configuration circuits, for adc circuit
The compensation of internal calibrators.
5. according to claim 3 in analog-digital converter multistage many bit sub-circuits digital calibration circuit, it is characterised in that：
Described calibrate controls the calibration control flow of circuit to be：The initialization of calibration control word first in peripheral control circuits, in calibration
In the case of enable signal is effective, into circulation, cycle-index is the number of the comparison point of sub-circuit；Peripheral control circuits are sent
Force interval code so that the comparator in sub- MDAC is in corresponding operation interval；Analog circuit is received after this code, is worked as
The output digital code of preceding level, digital calibration circuit receives the digital code of this grade, and multistage sub-circuit is completed by data synthesis circuit
Digital code Data Synthesis, current ADC numeral output is obtained, by calibration value measuring circuit according in SPI register circuits
Parameter value complete the accumulating operation of quantized value at current comparison point, and store into SPI register circuits；Peripheral control electricity
Accumulated value is read on road, is carried out error op and is taken the mean, obtains the calibration value of the comparison point, and the calibration value is written to
In SPI register circuits, calculated subsequently into the error amount of next comparison point；, will after this grade of sub-circuit calibration is completed
Error amount is compensated into the output of data synthesis circuit, carries out the calibration of next stage sub-circuit；
Peripheral control circuits complete the Row control that calibrates for error of preceding 3 grades of sub-circuits according to the flow described in the first step；First will
4 ~ m grades of sub-circuits calibrate 3rd level, obtain calibration value and the compensation of 3rd level as ideal circuit, its m >=4, then by 3 ~ m grades
Sub-circuit calibrates the 2nd grade, obtains the 2nd grade of calibration value and compensation, then regard 2 ~ m grades of sub-circuits as ideal as ideal circuit
Circuit, calibrates the 1st grade, obtains the 1st grade of calibration value post-compensation, is finally completed the calibration of whole circuit.
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| CN117728838B (en) * | 2024-02-08 | 2024-05-28 | 深圳市山海半导体科技有限公司 | Analog-to-digital conversion device and calibration method for ADC offset error |
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