CN104168022A - X-ray CCD reading system based on discrete time incremental model sigma delta ADC - Google Patents
X-ray CCD reading system based on discrete time incremental model sigma delta ADC Download PDFInfo
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Abstract
The invention relates to a low-power-consumption and low-noise X-ray CCD reading system based on a discrete time incremental model sigma delta ADC. The X-ray CCD reading system is composed of a front-end reading circuit, a digital control unit and the discrete time incremental model sigma delta ADC, the front-end reading circuit provides gains and adjusts input signals to the dynamic range of the ADC, the discrete time incremental model sigma delta ADC carries out analog-digital conversion on the signals, and the digital control unit can adjust the gains of a front-end amplifier, change the height of the front-end output floating level and adjust a time window of an ADC sample in a forward and backward mode. The discrete time incremental model sigma delta ADC is provided with two passages, each passage is composed of a pre-modulator, an incremental model sigma delta modulator and a downsampling filter, and quantization of CCD signals is realized through a special comb-shaped filter of a truncation coefficient. When the X-ray CCD reading system works under power voltage 3.3 V and the reading speed is 100 kHz, the accuracy can reach 10-11 bits, the equivalent reading noise is smaller than 10 electrons, and the requirements of actual science research and application can be met.
Description
Technical field
The invention belongs to integrated circuit (IC) design technical field, be specifically related to a kind of X ray CCD read-out system based on incremental Σ Δ ADC.
Technical background
X ray CCD camera becomes the main flow detector that is applied to X ray astronomical telescope gradually in the last few years.X ray CCD has very high energy resolution and angular resolution.For reaching the low noise requirement of high accuracy, traditional X ray CCD read-out system normally forms with discrete component, but read-out system weight and power consumption that discrete component forms are very large, has increased to a great extent the cost of rocket launching.In addition, because the read-out speed of traditional read-out system is very low, a frame image signal of reading whole CCD plane needs the even longer time in several seconds, has caused the temporal resolution of CCD read-out system to be not enough to meet the needs of the researchs such as astrophysics.In the last few years, dedicated IC chip (ASIC) substituted traditional discrete device just gradually, became the solution of the X ray read-out system of main flow.Dedicated IC chip can carry out the index that custom circuit design reaches specific precision, noise and read-out speed.Along with the development of integrated circuit technology, the area of integrated circuit (IC) chip, speed and power consumption constantly reduce, and the advantage that integrated circuit is compared traditional discrete component is more remarkable.By design single-chip multi-channel parallel, process the read-out speed that ccd signal can improve whole system.
For eliminating low-frequency noise, imbalance and the 1/f noise in ccd output signal, conventionally all need to adopt Correlated Double Sampling (CDS) to reduce noise.Correlated Double Sampling to floating level and signal level double sampling subtract each other, be it is generally acknowledged in this double sampling and is comprised identical low-frequency noise component and imbalance component, realized thus the object of noise reduction.And in side circuit, also there are white noise, high-frequency noise and switching noise etc., these noises can not well be eliminated by CDS technology, therefore, on the basis of CDS technology, have invented again the technology (iCDS) of integration correlated-double-sampling.ICDS is by level and the signal level integration within a certain period of time of floating, and its transfer function is equivalent to a band pass filter, has both eliminated low-frequency noise, again can filter away high frequency noise.The technology that is similar to iCDS is the CDS that repeatedly samples, and this technology is by float level and signal level are repeatedly sampled, to average to reach to fall low noise object.
Σ Δ ADC is applicable to being applied to low noise X ray read-out system, due to the over-sampling characteristic of Σ Δ ADC itself, thereby can carry out the noise that over-sampling reduces reading circuit by float level and signal level to a picture element signal.But traditional Σ Δ ADC needs very complicated digital filter, the response time of digital filter is very long, and numeral output and analog input be relation one to one not, cannot be applied to picture signal and read application.In recent years, a kind of incremental Σ Δ ADC framework was suggested and was used widely in high precision instrument instrument measurement field.The advantage of incremental Σ Δ ADC is the one-to-one relationship with input and output, and its digital filter has the output characteristic of zero propagation, is therefore applicable to being very much applied to X ray CCD read-out system.
Summary of the invention
The object of the present invention is to provide a kind of low noise X ray read-out system of low-power consumption based on incremental Σ Δ ADC.
The low noise X ray CCD of low-power consumption provided by the invention read-out system, by front end reading circuit (1), digital control unit (2) and discrete time incremental Σ Δ ADC(3) form.
The Vinp input of described front end reading circuit (1) is connected with Vinn with outside analog input signal Vinp respectively with Vinn input; Its clamp1 input, clamp2 input and DAC_en input respectively with the clamp1 output of described digital control unit (2), clamp2 output is connected with DAC_en output; Its Voutp output and Voutn output respectively with described discrete time incremental Σ Δ ADC(3) Vinp input be connected with Vinn input;
The CLK input of described digital control unit (2) is connected with outside clock input signal CLK; Its RST input is connected with outside CCD reset synchronization signal RST; Its CS input, SCLK input and MOSI input respectively with outside SPI write signal CS, SCLK is connected with MOSI; Its CLK1 output, RST1 output, deint1 output, int1 output, post1 output respectively with described discrete time incremental Σ Δ ADC(3) CLK1 input, RST1 input, deint1 input, int1 input, post1 input is connected; Its CLK2 output, RST2 output, deint2 output, int2 output, post2 output respectively with described discrete time incremental Σ Δ ADC(3) CLK2 input, RST2 input, deint2 input, int2 input, post2 input is connected;
Described discrete time incremental Σ Δ ADC(3) Vcom input is connected with outside simulation common-mode signal Vcom; Its output is connected with Dout output, the result of output read-out system.
In the present invention, described front end reading circuit (1) is comprised of two trsanscondutance amplifiers, 8 electric capacity, four switches and 1 DAC.Wherein, one end of capacitor C 1p is connected with described input Vinp, the other end with the in-phase input end of trsanscondutance amplifier OTA1, one end of switch S 1p be connected with one end of capacitor C 2p; One end of capacitor C 1n is connected with described input Vinn, the other end with the inverting input of trsanscondutance amplifier OTA1, one end of switch S 1n be connected with one end of capacitor C 2n; One end of the other end of capacitor C 2p, the other end of switch S 1p and capacitor C 3p is connected with the reversed-phase output of trsanscondutance amplifier OTA1; One end of the other end of capacitor C 2n, the other end of switch S 1n and capacitor C 3n is connected with the in-phase output end of trsanscondutance amplifier OTA1; The other end of capacitor C 3p with the in-phase input end of trsanscondutance amplifier OTA2, one end of one end of switch S 2p, capacitor C 5p be connected with one end of capacitor C 4p; The other end of capacitor C 3n with the inverting input of trsanscondutance amplifier OTA2, one end of one end of switch S 2n, capacitor C 5n be connected with one end of capacitor C 4n; The reversed-phase output of the other end of capacitor C 4p, the other end of switch S 2p, trsanscondutance amplifier OTA2 is connected with described output end vo utp; The in-phase output end of the other end of capacitor C 4n, the other end of switch S 2n, trsanscondutance amplifier OTA2 is connected with described output end vo utn; The control end of the control end of switch S 1p and switch S 1n is connected with described input clamp1; The control end of the control end of switch S 2p and switch S 2n is connected with described input clamp2; The input control signal of DAC is connected with described input DAC_en; The other end of capacitor C 5p is connected with the in-phase output end of DAC; The other end of capacitor C 5n is connected with the reversed-phase output of DAC.
In the present invention, described digital control unit (2) is by SPI module, and reset signal circuit for generating and clamp state machine, channel1 state machine and channel2 state machine form.Outside input clock signal CLK is connected with above-mentioned three state machines with reset signal circuit for generating; Outside input reset signal RST is connected with clamp state machine with reset signal circuit for generating; Reset signal circuit for generating produces the reset signal RST1 of passage 1 and the reset signal RST2 of passage 2, and they are connected with state machine channel2 with state machine channel1 respectively.External input signal MOSI, CS is connected with SPI with SCLK, the output sdac of SPI, sclamp1 is connected with state machine clamp with sclamp2, and the output S1-S7 of SPI is connected with state machine channel2 with state machine channel1.Digital control unit (2) is realized the clamp switch ON time in front end reading circuit (1) and the configuration in ADC sampling time by writing the value of SPI register.
In the present invention, described discrete time incremental Σ Δ ADC(3) there are two passages, each passage is respectively by submodulator, and incremental sigma Delta modulator and desampling fir filter form.Submodulator 1 is comprised of 6 sampling switchs; One end of first sampling switch of submodulator 1 and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the in-phase input end of incremental sigma Delta modulator 1, its control signal and described incremental Σ Δ ADC(3) input deint1 be connected; One end of second sampling switch of submodulator 1 and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the in-phase input end of incremental sigma Delta modulator 1, its control signal and described incremental Σ Δ ADC(3) input int1 be connected; One end of the 3rd sampling switch of submodulator 1 and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the in-phase input end of incremental sigma Delta modulator 1, its control signal and described incremental Σ Δ ADC(3) input post1 be connected; One end of the 4th sampling switch of submodulator 1 and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the inverting input of incremental sigma Delta modulator 1, its control signal and described incremental Σ Δ ADC(3) input deint1 be connected; One end of the 5th sampling switch of submodulator 1 and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the inverting input of incremental sigma Delta modulator 1, its control signal and described incremental Σ Δ ADC(3) input int1 be connected; One end of the 6th sampling switch of submodulator 1 and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the inverting input of incremental sigma Delta modulator 1, its control signal and described incremental Σ Δ ADC(3) input post1 be connected; Submodulator 2 is comprised of 6 gating switches equally; One end of first sampling switch of submodulator 2 and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the in-phase input end of incremental sigma Delta modulator 2, its control signal and described incremental Σ Δ ADC(3) input deint2 be connected; One end of second sampling switch of submodulator 2 and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the in-phase input end of incremental sigma Delta modulator 2, its control signal and described incremental Σ Δ ADC(3) input int2 be connected; One end of the 3rd sampling switch of submodulator 2 and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the in-phase input end of incremental sigma Delta modulator 2, its control signal and described incremental Σ Δ ADC(3) input post2 be connected; One end of the 4th sampling switch of submodulator 2 and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the inverting input of incremental sigma Delta modulator 2, its control signal and described incremental Σ Δ ADC(3) input deint2 be connected; One end of the 5th sampling switch of submodulator 2 and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the inverting input of incremental sigma Delta modulator 2, its control signal and described incremental Σ Δ ADC(3) input int2 be connected; One end of the 6th sampling switch of submodulator 2 and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the inverting input of incremental sigma Delta modulator 2, its control signal and described incremental Σ Δ ADC(3) input post2 be connected; The clock signal clk 1 of incremental sigma Delta modulator 1 and reset signal RST1 respectively with described incremental Σ Δ ADC(3) input CLK1 be connected with input RST1, the output of incremental sigma Delta modulator 1 is connected with the input of desampling fir filter 1; The clock signal clk 1 of desampling fir filter 1 and reset signal RST1 respectively with described incremental Σ Δ ADC(3) input CLK1 be connected with input RST1; The clock signal clk 2 of incremental sigma Delta modulator 2 and reset signal RST2 respectively with described incremental Σ Δ ADC(3) input CLK2 be connected with input RST2, the output of incremental sigma Delta modulator 2 is connected with the input of desampling fir filter 2; The clock signal clk 2 of desampling fir filter 2 and reset signal RST2 respectively with described incremental Σ Δ ADC(3) input CLK2 be connected with input RST2; The output of desampling fir filter 1 and desampling fir filter 2 is connected with the MUX of an alternative, and MUX exports from output Dout after two paths of signals is merged into a road.
In the present invention, described desampling fir filter 1 and desampling fir filter 2, in order to realize the demodulation to the incremental sigma Delta modulator with submodulator, have adopted the comb filter structure of a truncation function.The system configuration of comb filter and traditional comb filter structure are similar, and the down-sampled clock of down-sampled module produces down-sampled clock heterogeneous by internal digital state machine.
The low noise X ray read-out system of low-power consumption work based on discrete time incremental Σ Δ ADC of the present invention has advantages of high linearity, the low noise of reading, compare with the system that traditional discrete device is realized, reduced volume, weight and power consumption, so the present invention is applied to have larger advantage in astronomical X ray read-out system.
Accompanying drawing explanation
Fig. 1 is the system block diagram of the X ray CCD reading circuit based on incremental Σ Δ ADC of the present invention.
Fig. 2 is the main signal oscillogram in the X ray CCD read-out system based on incremental Σ Δ ADC of the present invention.
Fig. 3 is the front end reading circuit structure figure regulating with clamp switch ON time of the present invention.
Fig. 4 is the system block diagram of digital control unit of the present invention.
Fig. 5 works as N
s=50, N
pthe sequential chart of the comb filter of=238 o'clock truncation functions for demodulation incremental sigma Delta modulator of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the invention will be further described.
Fig. 1 is the system block diagram of the X ray CCD reading circuit based on incremental Σ Δ ADC of the present invention.The ccd signal of input as shown in Figure 2, mainly comprises 3 parts: reset signal, float level and signal level, the poor energy size that represents this pixel X ray signal of float level and signal level.On actual ccd signal, there is clock feedthrough, burr signal and 1/f noise, therefore conventionally use Correlated Double Sampling to process ccd signal.Whole system is by front end reading circuit (1), digital control unit (2) and incremental Σ Δ ADC(3) form.Front end reading circuit amplifies CCD read output signal, digital control unit is by output clamper control signal clamp1, clamp2 and DAC control signal DAC_en regulate signal amplitude and the DC component of front end output, and object is the input dynamic range that can make full use of ADC.The output of front-end circuit is connected to incremental Σ Δ ADC below, because CCD read output signal maximum rate is 100kHz, and single channel Σ Δ ADC has one-period time delay from sampled signal to output, therefore the fastest processing speed of ADC is 50kHz, need two passages alternately to input signal sampling, output merges the data of two ADC by an either-or switch.The sampling control signal of ADC and gated clock are produced by digital control part, and sampling control signal can avoid ADC to sample the clock feedthrough burr signal in ccd signal.The clock of incremental sigma Delta modulator is the gated clock that digital control part produces, and when sigma Delta modulator is not sampled, gated clock does not overturn, thereby has reduced the power consumption of the numerical portion of Σ Δ ADC.The chief component of digital control part is that SPI module, reset signal circuit for generating, clamp state machine, channel1 state machine and channel2 state machine form, and SPI writes register by outside and realizes the clamp switch ON time of front end reading circuit (1) and the configuration in ADC sampling time.
Fig. 2 has provided the main signal waveform in the X ray CCD reading circuit based on incremental Σ Δ ADC of the present invention.The input of digital control unit is the clock of 16MHz and the reset signal RST that frequency is 100kHz.Digital control unit can be that 2 frequencies reset signal RST1 that is 50kHz and RST2 are as the reset signal of passage 1 and passage 2 using RST frequency division.Deint1, int1 and post1 are the control gating signal of submodulator 1; Deint2, int2 and post2 are the control gating signal of submodulator 2.When there is high level in RST1, integrator zero clearing to incremental sigma Delta modulator inside, sigma Delta modulator 1 is started working, first be that deint1 is that high level is effective, corresponding control switch conducting, the signal (Vinp-Vinn) of incremental sigma Delta modulator input stage sampling front end reading circuit, first stage sampling N
sindividual, sampling window length is N
sthe individual clock cycle; When deint1 becomes low level, gated clock CLK1 does not overturn, and modulator stops sampling, the feedthrough burr signal that can avoid sampling to float between level and signal level; When int1 is that high level is when effective, corresponding control switch conducting, the signal (Vinn-Vinp) of incremental sigma Delta modulator input stage sampling front end reading circuit, the anti-phase signal level of having sampled of modulator like this, therefore the result obtaining is the poor of level and signal level of floating, and second stage is sampling N equally
sindividual, sampling window length is N
sthe individual clock cycle; The last stage post1 is that high level is effective, corresponding control switch conducting, incremental sigma Delta modulator input stage sampling common mode electrical level (Vcom-Vcom=0), modulator sampling zero-signal, this stage sampling N
pindividual, by the post stage, can improve the conversion accuracy of modulator.When modulator 1 is also operated in post, cannot sample to input signal, at this moment just by the incremental Σ Δ ADC of passage 2, float level and the signal level of ccd signal to be sampled, sampling process is identical with passage 1.The modulator of each passage is processed the pixel 2*N that need to work
s+ N
pindividual clock cycle, wherein N
sand N
pcan configure by SPI.
Fig. 3 is the front end reading circuit structure figure in the present invention, mainly two-stage gain amplifier, consists of, and every stage gain can be fixed, and also can adjust.Switch S 1p, S1n, S2p, S2n, S3p, S3n, S4p, S4n is clamp switch, by short circuit amplifier input and output, brings in the DC point of determining amplifier.The time that clamp switch disconnects can configure by SPI, the value that the time finishing by change clamper can regulate the CCD of preamplifier output to float level, and the oscillogram of clamp switch control signal clamp1 and clamp2 is as shown in Figure 2.Because the signal level of ccd signal own is always less than the level of floating, thus the value that quantizes of ADC always one be less than 0 signal, the ADC just input dynamic range of half part is not fully utilized.For addressing this problem, need to, between first order amplifier and second level amplifier, add the square wave input of DAC; The input control signal DAC_en oscillogram of DAC as shown in Figure 2, when DAC_en is high level, DAC output difference is divided into 0V, when DAC_en is low level, DAC is output as several different adjustable differential magnitudes of voltage (regulating by SPI), as 200mV, and 400mV etc.By regulate the ON time of clamp switch can change the height of level and signal level of floating simultaneously, and DAC can increase the height of signal level, clamper ON time regulates and the adjusting of DAC coordinates jointly, thereby can make the dynamic range of ccd signal level about 0 symmetry.
Fig. 4 is the system block diagram of digital control unit of the present invention.Reset signal circuit for generating can produce 2 reset signals that passage is required; The output sdac of SPI, scalmp1 is connected with state machine clamp with sclamp2, the time that control clamp level finishes and the time of DAC_en upset.The inside of state machine clamp is a counter, each zero clearing start counting when RST is high level, sdac, sclamp1 and sclamp2 are the periodicity of the high level of DAC_en and clamp level, change the level of output signal when the count value of counter is identical with the value of SPI configuration.The output S1-S7 of SPI is connected with state machine channel2 with state machine channel1, controls the sampling control signal RST1 of ADC passage 1 and passage 2, deint1, int1, post1 and RST2, deint2, int2, the width of post2 and the zero hour.
Fig. 5 is for working as N
s=50, N
pthe sequential chart of the truncation function comb filter for demodulation incremental sigma Delta modulator in the present invention in=138 o'clock, in figure, T represents the cycle of outside input clock CLK.In order to realize the demodulation to the incremental sigma Delta modulator with submodulator, adopted an asymmetric comb filter structure, need to block the part coefficient of filter.The transfer function of traditional comb filter can be expressed as:
（1）
Here, M is down-sampled ratio, the exponent number that L is comb filter.Such as getting L=5, during M=76, before not blocking, the length of this filter can be expressed as:
（2）
The length of this filter can be divided into 4 sections, and first paragraph is pretreatment stage, the second stage sampling level of floating, and phase III sampled signal level, fourth stage is post-processing stages.Second stage and phase III equal in length, all equals modulator float level or signal level is carried out to counting of over-sampling
n sif establish N
s=50, the length that calculates thus pretreatment stage and post-processing stages is:
（3）
Because pretreatment stage can be omitted in modulator, so front 138 coefficients of filter are 0, and blocking non-vanishing coefficient number in these coefficient postfilters is this new filter length:
（4）
This asymmetric comb filter is by inhomogeneous down-sampled recently realization, as shown in Figure 5.Down-sampled ratio is for the first time:
（5）
Here mod is the operation of remainder number.Still adopt afterwards the down-sampled ratio of M=76 at every turn, down-sampled through 3 times after, the filter output after just being blocked.
Embodiment of the present invention design adopts GlobalFoundry 0.35 μ m CMOS technique, supply voltage is 3.3V, and when being operated in read-out speed and being 100kHz, the integral nonlinearity of reading circuit is 0.06%, equivalent input noise is 41.98 μ V, and whole chip power-consumption is only 16.2mW.The above results shows that this X ray CCD read-out system can meet in actual astrophysics research high accuracy and low noise requirement, compares with the system that traditional component device is realized, and has volume little, advantage low in energy consumption.
Claims (5)
1. the X ray read-out system based on discrete time incremental Σ Δ ADC, by front end reading circuit (1), discrete time incremental Σ Δ ADC(2) and digital control unit (3) form, it is characterized in that:
The Vinp input of described front end reading circuit (1), Vinn input are connected with outside analog input signal Vinp, Vinn respectively; Its clamp1 input, clamp2 input, DAC_en input are connected with clamp1 output, clamp2 output, the DAC_en output of described digital control unit (2) respectively; Its Voutp output, Voutn output respectively with described discrete time incremental Σ Δ ADC(3) Vinp input, Vinn input be connected;
The CLK input of described digital control unit (2) is connected with outside clock input signal CLK; Its RST input is connected with outside CCD reset synchronization signal RST; Its CS input, SCLK input, MOSI input are connected with outside SPI write signal CS, SCLK, MOSI respectively; Its CLK1 output, RST1 output, deint1 output, int1 output, post1 output respectively with described discrete time incremental Σ Δ ADC(3) CLK1 input, RST1 input, deint1 input, int1 input, post1 input be connected; Its CLK2 output, RST2 output, deint2 output, int2 output, post2 output respectively with described discrete time incremental Σ Δ ADC(3) CLK2 input, RST2 input, deint2 input, int2 input, post2 input be connected;
Described discrete time incremental Σ Δ ADC(3) Vcom input is connected with outside simulation common-mode signal Vcom; Its output is connected with Dout output, the result of output read-out system.
2. the X ray read-out system based on discrete time incremental Σ Δ ADC according to claim 1, is characterized in that:
Described front end reading circuit (1) is comprised of two trsanscondutance amplifiers, 8 electric capacity, four switches and 1 DAC; Wherein, one end of capacitor C 1p is connected with described input Vinp, the other end with the in-phase input end of trsanscondutance amplifier OTA1, one end of switch S 1p be connected with one end of capacitor C 2p; One end of capacitor C 1n is connected with described input Vinn, the other end with the inverting input of trsanscondutance amplifier OTA1, one end of switch S 1n be connected with one end of capacitor C 2n; One end of the other end of capacitor C 2p, the other end of switch S 1p, capacitor C 3p is connected with the reversed-phase output of trsanscondutance amplifier OTA1; One end of the other end of capacitor C 2n, the other end of switch S 1n, capacitor C 3n is connected with the in-phase output end of trsanscondutance amplifier OTA1; The other end of capacitor C 3p with the in-phase input end of trsanscondutance amplifier OTA2, one end of one end of switch S 2p, capacitor C 5p be connected with one end of capacitor C 4p; The other end of capacitor C 3n with the inverting input of trsanscondutance amplifier OTA2, one end of one end of switch S 2n, capacitor C 5n be connected with one end of capacitor C 4n; The reversed-phase output of the other end of capacitor C 4p, the other end of switch S 2p, trsanscondutance amplifier OTA2 is connected with described output end vo utp; The in-phase output end of the other end of capacitor C 4n, the other end of switch S 2n, trsanscondutance amplifier OTA2 is connected with described output end vo utn; The control end of the control end of switch S 1p and switch S 1n is connected with described input clamp1; The control end of the control end of switch S 2p and switch S 2n is connected with described input clamp2; The input control signal of DAC is connected with described input DAC_en; The other end of capacitor C 5p is connected with the in-phase output end of DAC; The other end of capacitor C 5n is connected with the reversed-phase output of DAC.
3. the X ray read-out system based on discrete time incremental Σ Δ ADC according to claim 1, is characterized in that:
Described digital control unit (2) is comprised of SPI module, reset signal circuit for generating and clamp state machine, channel1 state machine and channel2 state machine; Outside input clock signal CLK is connected with above-mentioned three state machines with reset signal circuit for generating; Outside input reset signal RST is connected with clamp state machine with reset signal circuit for generating; Reset signal circuit for generating produces the reset signal RST1 of passage 1 and the reset signal RST2 of passage 2, is connected respectively with state machine channel1 with state machine channel2; External input signal MOSI, CS are connected with SPI with SCLK, and output sdac, the sclamp1 of SPI is connected with state machine clamp with sclamp2, and the output S1-S7 of SPI is connected with state machine channel2 with state machine channel1; Digital control unit (2) is realized the clamp switch ON time in front end reading circuit (1) and the configuration in ADC sampling time by writing the value of SPI register.
4. the X ray read-out system based on discrete time incremental Σ Δ ADC according to claim 1, is characterized in that:
Described discrete time incremental Σ Δ ADC(3) have two passages, each passage is comprised of submodulator, incremental sigma Delta modulator and desampling fir filter respectively; Wherein, the first submodulator is comprised of 6 sampling switchs; One end of first sampling switch of the first submodulator and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the in-phase input end of the first incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input deint1 be connected; One end of second sampling switch of the first submodulator and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the in-phase input end of the first incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input int1 be connected; One end of the 3rd sampling switch of the first submodulator and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the in-phase input end of the first incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input post1 be connected; One end of the 4th sampling switch of the first submodulator and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the inverting input of the first incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input deint1 be connected; One end of the 5th sampling switch of the first submodulator and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the inverting input of the first incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input int1 be connected; One end of the 6th sampling switch of the first submodulator and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the inverting input of the first incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input post1 be connected; The second submodulator is comprised of 6 gating switches equally; One end of first sampling switch of the second submodulator and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the in-phase input end of the second incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input deint2 be connected; One end of second sampling switch of the second submodulator and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the in-phase input end of the second incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input int2 be connected; One end of the 3rd sampling switch of the second submodulator and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the in-phase input end of the second incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input post2 be connected; One end of the 4th sampling switch of the second submodulator and described incremental Σ Δ ADC(3) input Vinn be connected, the other end is connected with the inverting input of the second incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input deint2 be connected; One end of the 5th sampling switch of the second submodulator and described incremental Σ Δ ADC(3) input Vinp be connected, the other end is connected with the inverting input of the second incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input int2 be connected; One end of the 6th sampling switch of the second submodulator and described incremental Σ Δ ADC(3) input Vcom be connected, the other end is connected with the inverting input of the second incremental sigma Delta modulator, its control signal and described incremental Σ Δ ADC(3) input post2 be connected; The clock signal clk 1 of the first incremental sigma Delta modulator and reset signal RST1 respectively with described incremental Σ Δ ADC(3) input CLK1 be connected with input RST1, the output of the first incremental sigma Delta modulator is connected with the input of the first desampling fir filter; The clock signal clk 1 of the first desampling fir filter and reset signal RST1 respectively with described incremental Σ Δ ADC(3) input CLK1 be connected with input RST1; The clock signal clk 2 of the second incremental sigma Delta modulator and reset signal RST2 respectively with described incremental Σ Δ ADC(3) input CLK2 be connected with input RST2, the output of the second incremental sigma Delta modulator is connected with the input of the second desampling fir filter; The clock signal clk 2 of the second desampling fir filter and reset signal RST2 respectively with described incremental Σ Δ ADC(3) input CLK2 be connected with input RST2; The output of the first desampling fir filter and the second desampling fir filter is connected with the MUX of an alternative, and MUX exports from output Dout after two paths of signals is merged into a road.
5. the X ray read-out system based on discrete time incremental Σ Δ ADC according to claim 4, it is characterized in that: the first described desampling fir filter and the second desampling fir filter, in order to realize the demodulation to the incremental sigma Delta modulator with submodulator, adopt the comb filter structure of a truncation function; The down-sampled clock of down-sampled module produces down-sampled clock heterogeneous by internal digital state machine.
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| CN116137532A (en) * | 2023-02-06 | 2023-05-19 | 广芯微电子（广州）股份有限公司 | Method, device, equipment and medium for improving sampling value precision of analog-to-digital converter |
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