CN107070450A - Multichannel DAC phase errors calibration circuit based on charge-domain signal transacting - Google Patents

Abstract

Circuit is calibrated the invention provides a kind of multichannel DAC phase errors based on charge-domain signal transacting, it is characterized in that including：Current sense resistor Rd, reference clock generation circuit, phase discriminator, loop filter, charge-domain voltage amplifier circuit, K charge-domain analog-digital converters, control circuit and 1~delay circuit of delay circuit M.The error calibration circuit includes calibration mode and compensation model, and calibration mode is introduced into when circuit works, compensation model is entered afterwards.The charge-domain Small Current Signal amplifying circuit can be widely applied in the detection and amplification system of all kinds of electric signals.

Description

Multi-channel DAC Phase Error Calibration Circuit Based on Charge Domain Signal Processing

technical field

The invention relates to an error calibration circuit, in particular to a circuit for self-calibration of phase errors between multi-channel DACs using charge domain signal processing technology.

Background technique

A digital-to-analog converter (DAC) is an electronic circuit that converts an input digital signal into an output analog signal. The value represented by the digital signal input to the DAC is equivalent to the amplitude of the analog signal output by the DAC. Various factors determine the performance of a DAC, including speed, resolution, and noise.

The current steering digital-analog converter is the most popular high-speed and high-precision digital-analog converter structure, which generally includes a decoding circuit, a latch array and a current element array. Among them, the decoding circuit usually converts the input binary digital signal into a thermometer-encoded digital signal, and inputs it to the latch array, and the latch uses the clock signal to synchronize the digital signal output by the decoding circuit, and the synchronized The digital signal is transmitted to the current element, and the current element determines the flow direction of its own current according to the input digital signal. So far, the digital-to-analog converter has completed the conversion from the input digital signal to the output analog signal.

However, due to the mismatch between the latch array and the current element array, there is a delay difference in the output of different current element units, and this delay difference greatly reduces the dynamic performance of the digital-to-analog converter, so a certain correction method is required to remove it. . Especially when multi-channel DACs are integrated on the same chip, the delay and phase asynchrony between different channel DACs will be very obvious. This phase asynchronization has a great impact on the performance of systems such as radar and multi-channel wireless communication. Therefore, it is very meaningful to design a circuit that can self-calibrate the phase error between multi-channel DACs.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide a circuit for self-calibrating the phase error between multi-channel DACs.

The purpose of the present invention can be achieved through the following technical solutions:

A multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that it includes: a current detection resistor Rd, a reference clock generation circuit, a phase detector, a loop filter, a charge domain voltage amplification circuit, and a K-bit charge domain An analog-to-digital converter, a control circuit, and a set of delay circuits;

The connection relationship of the above-mentioned circuit is: the current detection resistor Rd is connected to the differential current output terminal of the N-digit analog converter to be calibrated in the M channel, and is respectively connected to the first and second input terminals of the phase detector; the control of the reference clock generation circuit The input terminal is connected to the K bit selection code output port of the control circuit, the reference clock output terminal of the reference clock generation circuit is connected to the third input terminal of the phase detector; the phase error signal output terminal Vp of the phase detector is connected to the loop filter The input terminal of the loop filter; the output voltage Vi of the loop filter is input to the analog signal input terminal of the charge domain voltage amplifying circuit; the differential signal output terminal of the charge domain voltage amplifying circuit is connected to the differential voltage input of the K-bit charge domain analog-to-digital converter terminal; the K-bit quantization code of the K-bit charge domain analog-to-digital converter is output to the error input port of the control circuit; the N-bit calibration code and K-bit delay code output terminals of the control circuit are respectively connected to the first and second of all delay circuits Input port, the calibration control signal clock X of the control circuit is linked to the third input port of the delay circuit X, and the calibration control signal Ctrl output port of the control circuit is connected to the phase detector, loop filter, charge domain voltage amplification circuit and K at the same time The calibration control signal Ctrl input port of the bit charge domain analog-to-digital converter; the N-bit input code X is connected to the fourth input port of the delay circuit X, and the output port of the delay circuit X is connected to the decoding circuit of the N-bit digital-to-analog converter X ;

Wherein, N and M are any positive integers, K is a positive integer not greater than N, and X is a positive integer not greater than M.

The multi-pass digital-to-analog converter phase error calibration circuit based on charge domain signal processing is characterized in that it includes a calibration mode and a compensation mode; and when the circuit is working, it first enters the calibration mode and then enters the compensation mode;

When entering the calibration mode, all N-bit input codes and K-bit delay codes are invalid, and N-bit calibration codes are input to all delay circuits, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing sequentially performs N-bit M channel The digital-to-analog converter performs phase error calibration; when entering the compensation mode, the N-bit input code X is input to the delay circuit X, the N-bit calibration code is invalid, and the K-bit delay code is valid. The multi-channel DAC phase based on charge domain signal processing The error calibration circuit performs phase compensation to the N-bit digital-to-analog converter of the M channel at the same time.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that when entering the calibration mode, the working order of the circuit is as follows:

The control circuit first controls the phase detector, the loop filter, the charge domain voltage amplifier circuit and the K-bit charge domain analog-to-digital converter to enter the calibration mode, and at the same time outputs the K-bit selection code to the reference clock generation circuit to enter the calibration mode; in addition, the output Calibrate the control signal clock 1 signal to the delay circuit 1 to control the delay circuit 1 to enter the calibration mode, and start the phase error calibration of the N-digit digital-to-analog converter circuit 1;

The control circuit then generates the first group of N-bit calibration codes and the first group of K-bit selection codes; the first group of N-bit calibration codes enters the delay circuit and obtains N-bit conversion codes, and the N-bit conversion codes enter the N-bit digital-to-analog conversion to be calibrated The reference clock generation circuit obtains the first reference clock corresponding to the N-bit calibration code; the first and second input terminals of the phase detector circuit will obtain an input differential voltage, and compare the input differential voltage with the first The reference clock obtains the phase error signal Vp; the Vp signal is filtered by the loop filter and amplified by the charge domain voltage amplifier circuit to obtain the error voltage; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the error voltage to obtain the first group The K-bit quantization code is output to the control circuit; the control circuit stores the received first group of K-bit quantization codes in its internal K-bit register set, and completes phase error quantization under a calibration code condition;

Cycle in turn, when the controller generates the L group of N-bit calibration codes and the L-th group of K-bit selection codes, and obtains the L-th group of K-bit quantization codes, and stores them in its internal K-bit register group, the control circuit internal The operation circuit will calculate the L groups of K-bit quantization codes stored in the K-bit register group to obtain the first group of K-bit delay codes; the control circuit will output the first group of K-bit compensation codes to the delay circuit 1 at this time, And keep the first group of K-bit compensation codes unchanged, and complete the phase error calibration of the N-bit digital-to-analog converter circuit 1;

Immediately afterwards, the control circuit outputs the calibration control signal clock 2 signal to control the delay circuit 2 to enter the calibration mode, and begins to perform phase error calibration of the N-bit digital-to-analog converter circuit 2; the multi-channel DAC phase error calibration circuit based on charge domain signal processing The second group of K-bit delay codes is obtained by the same calibration process as that of the N-digit digital-to-analog converter circuit 1; the control circuit also outputs the second group of K-bit compensation codes to the delay circuit 2, and maintains the second group of K-bit compensation codes unchanged, the phase error calibration of the N-digit digital-to-analog converter circuit 2 is completed;

According to the same calibration method, the control circuit outputs the Y-th group of K-bit compensation codes to the delay circuit Y, and keeps the Y-th group of K-bit compensation codes unchanged; when the control circuit outputs the M-th group of K-bit compensation codes to the delay circuit In M, and keep the M group of K-bit compensation codes unchanged, the calibration mode of the multi-channel DAC phase error calibration circuit based on charge domain signal processing ends;

Wherein, L is a positive integer not greater than 2 ^K , and Y is a positive integer greater than 1 and less than M.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that when entering the compensation mode, the working sequence of the circuit is as follows: the control circuit sets all the delay circuits to the compensation mode at the same time, and starts to adjust the N bit of the M channel The phase error of the digital-to-analog converter is compensated; finally, the control circuit turns off the N-bit calibration code, turns off the phase detector, the loop filter, the charge domain voltage amplifier circuit, the K-bit charge domain analog-to-digital converter and the reference clock generation circuit .

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that: when the circuit enters the calibration mode, each group of N-bit calibration codes output to the compensation circuit and output to the reference clock generated by the control circuit simultaneously The K-bit selection codes of the circuit must be in one-to-one correspondence, that is, the J-th group of N-bit calibration codes must be used in conjunction with the J-th group of K-bit selection codes;

Wherein, J is a positive integer not greater than L.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the K-bit charge domain analog-to-digital converter includes: P-level pipeline sub-level circuits based on charge domain signal processing technology, which are used for The sampled charge packets are processed to complete analog-to-digital conversion and margin amplification, and the output digital codes of each sub-level circuit are input to the delay synchronization register, and the charge packets output by each sub-level circuit enter the next level Repeat the above process; the last stage (P+1 stage) A-bit Flash analog-to-digital converter circuit, which reconverts the charge packet transmitted from the Nth stage into a voltage signal, and performs the final stage of analog-to-digital conversion , and input the output digital code of this stage circuit to the delay synchronization register, this stage circuit only completes the analog-to-digital conversion, and does not perform margin amplification; the delay synchronization register is used to perform digital code output by each sub-pipeline stage delay alignment, and input the aligned digital code to the digital correction module; the digital correction circuit module is used to receive the output digital code of the synchronous register, and shift and add the received digital code to obtain an analog-to-digital converter The R-bit digital output code;

Wherein, P and A are any positive integers not greater than K.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the reference clock generation circuit includes: a programmable frequency adjustment circuit and a programmable duty ratio adjustment circuit; the programmable frequency adjustment circuit and the programmable duty ratio adjustment circuit are all controlled by the K-bit selection code; under the control of the K-bit selection code, the input clock with a fixed frequency and duty ratio passes through the programmable frequency adjustment circuit and the programmable clock successively. After the duty ratio adjustment circuit, the reference clocks with different frequencies and duty ratios can be obtained.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the delay circuit includes: a set of delay buffer units and a set of K-bit delay registers;

The delay code input terminals of all K-bit delay registers are all connected to the K-bit delay code, and the control signal input terminals are all connected to the clock X; the delay code input terminals of the delay buffer unit X are connected to the delay code output terminals of the K-bit delay register X , the data output end of the delay buffer unit X is connected to the X-bit conversion code and output, the first control signal input end of the delay buffer unit X is connected to Ctrln, and the second control signal input end of the delay buffer unit X is connected to clock x;

Among them, clock X and Ctrln are reverse clocks.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the delay circuit can work in two modes of calibration and compensation mode; in the calibration mode, the clock X signal is valid, and the Z-bit input code Invalid, the input code has no effect on the output of the N-bit conversion code, the Z-bit calibration code is passed through the delay buffer circuit Z to obtain the Z-bit conversion code and output, the K-bit delay code is input into the K-bit delay register Z and It is latched and remains unchanged; in the compensation mode, the Ctrln signal is valid, the Z-bit input code is valid, and the Z-bit conversion code is obtained and output after the delay buffer circuit, the Z-bit calibration code is invalid, and the K-bit delay The K-bit delay code stored in the register Z is input to the delay buffer circuit Z for delay compensation; wherein, Z is any positive integer not greater than N.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the control circuit includes: a core control circuit, a calibration code generation circuit, a selection code generation circuit, an arithmetic circuit, a K-bit register group, a set of delay A code output register and a channel selection circuit; the connection relationship of the control circuit is:

The first output end of the core control circuit is connected to the input end of the calibration code generation circuit, the second output end of the core control circuit is connected to the control input end of the channel selection circuit, and the third output end of the core control circuit is connected to the control circuit of the arithmetic circuit. Input, the fourth output of the core control circuit is connected to the control input of the selection code generation circuit, the fifth output of the core control circuit is connected to the control input of the K-bit register group, and the W output of the core control circuit generates Calibration control signal clock X, the input end of the core control circuit is connected to the calibration start control signal;

The calibration code generation circuit generates N-bit calibration codes according to the control instructions of the core control circuit; the data input terminal of the arithmetic circuit receives the data sent by the output terminal of the K-bit register group, and generates a K-bit error code according to the control instructions of the core control circuit; all delays The data input terminals of the code output register are all connected to the K-bit error code output terminal of the arithmetic circuit, the control signal input terminal of the delay code output register X is connected to the calibration control signal clock X, and the output terminal of the delay code output register X is connected to the channel selection circuit The X data input terminal of the X; the channel selection circuit outputs the K-bit delay code to the delay circuit X according to the control instruction of the core control circuit; the selection code generation circuit generates the K-bit selection code according to the control instruction of the core control circuit; the K-bit register group The data input end receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter, and sends the data stored in its internal register to the arithmetic circuit according to the control instruction of the core control circuit;

Wherein, W is any positive integer greater than 5 and less than M+5.

The invention has the advantages that the proposed high-precision phase error calibration circuit can automatically trade off the calibration precision according to system precision and hardware overhead, and has the characteristics of low power consumption.

Description of drawings

Fig. 1 is a block diagram of a multi-channel DAC phase error calibration circuit based on charge domain signal processing in the present invention.

Fig. 2 is a schematic diagram of the circuit principle of the phase detector of the present invention.

Fig. 3 is a schematic diagram of the charge domain voltage amplification circuit of the present invention.

Fig. 4 is a working waveform diagram of the charge domain voltage amplifying circuit of the present invention.

Fig. 5 is a circuit block diagram of the charge domain analog-to-digital converter of the present invention.

Fig. 6 is a circuit block diagram of the charge domain pipeline sub-stage of the present invention.

Fig. 7 is a structural block diagram of the reference clock generation circuit of the present invention.

Fig. 8 is a structural block diagram of the delay circuit of the present invention.

Fig. 9 is a block diagram of the control circuit of the present invention.

detailed description

The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a block diagram of a multi-channel DAC phase error calibration circuit based on charge domain signal processing in the present invention. The multi-channel DAC phase error calibration circuit based on charge domain signal processing includes: current detection resistor Rd, reference clock generation circuit, phase detector, loop filter, charge domain voltage amplification circuit, K-bit charge domain analog-to-digital converter , a control circuit and a set of delay circuits.

The connection relationship of the above circuit is as follows: the two ends of the current detection resistor Rd are connected to the differential current output terminals of the N-digit digital-to-analog converter to be calibrated in the M channel, and are respectively connected to the first and second input terminals of the phase detector; the reference clock is generated The control input terminal of the circuit is connected to the K bit selection code output port of the control circuit, the reference clock output terminal of the reference clock generation circuit is connected to the third input terminal of the phase detector; the phase error signal output terminal Vp of the phase detector is connected to the loop The input terminal of the loop filter; the output voltage Vi of the loop filter is input to the analog signal input terminal of the charge domain voltage amplifying circuit; the differential signal output terminal of the charge domain voltage amplifying circuit is connected to the K-bit charge domain analog-to-digital converter The differential voltage input terminal; the K-bit quantization code of the K-bit charge domain analog-to-digital converter is output to the error input port of the control circuit; the N-bit calibration code and K-bit delay code output terminals of the control circuit are respectively connected to the delay circuit 1 ~ delay circuit The first and second input ports of M, the calibration control signal clock 1 ~ clock M signal ports of the control circuit are respectively connected to the third input port of the delay circuit 1 ~ delay circuit M, and the calibration control signal Ctrl output port of the control circuit is connected simultaneously The calibration control signal Ctrl input port to the phase detector, loop filter, charge domain voltage amplifying circuit and K-bit charge domain analog-to-digital converter; N-bit input codes 1 to N-bit input codes M are respectively connected to delay circuits 1 to The fourth input port of the delay circuit M, and the output ports of the delay circuit 1 to the delay circuit M are respectively connected to the decoding circuits of the N-bit digital-to-analog converters 1 to N-bit digital-to-analog converters M.

The multi-channel DAC phase error calibration circuit based on charge domain signal processing includes two working modes: calibration mode and compensation mode. When the circuit is working, enter the calibration mode first, and then enter the compensation mode; when entering the calibration mode, the N-bit input code and the K-bit delay code are invalid, and the N-bit calibration code is input to the delay circuit 1 ~ delay circuit M. The multi-channel DAC phase error calibration circuit for signal processing performs phase error calibration on the N-bit digital-to-analog converter 1 to the N-bit digital-to-analog converter M in turn; when entering the compensation mode, the N-bit input code 1 to the N-bit input code M are respectively Input to delay circuit 1～delay circuit M, N-bit calibration code is invalid, K-bit delay code is valid, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing simultaneously performs N-digit digital-to-analog converter 1-N digital The analog-to-analog converter M performs phase compensation.

The working principle of the above circuit is: when the calibration mode is turned on, the control circuit first controls the phase detector, the loop filter, the charge domain voltage amplifier circuit and the K-bit charge domain analog-to-digital converter to enter the calibration mode through the Ctrl signal, and simultaneously outputs K The bit selection code is given to the reference clock generation circuit and enters the calibration mode; in addition, the calibration control signal clock 1 is output to the delay circuit 1 to control the first delay circuit to enter the calibration mode, and the phase error calibration of the N-digit digital-to-analog converter circuit 1 is started .

The control circuit then generates the first group of N-bit calibration codes cali(1) and the first group of K-bit selection codes; the first group of N-bit calibration codes cali(1) enters the delay circuit and obtains N-bit conversion codes, and the N-bit conversion codes enter The N-digit digital-to-analog converter circuit 1 to be calibrated obtains the differential output current corresponding to the N-bit calibration code through digital-to-analog conversion; the reference clock generation circuit obtains the N-bit calibration code under the control of the first K-bit selection code Corresponding to the first reference clock; since the current detection resistor Rd is respectively connected to the differential current output terminals of the digital-to-analog converter, the first and second input terminals of the phase detector circuit will obtain an input differential voltage of Voutp-Voutn ; Since there is an offset error in the N-digit digital-to-analog converter to be calibrated, the phase detector obtains the phase error signal Vp by comparing the input differential voltage with the first reference clock; the Vp signal is filtered by the loop filter to obtain the error voltage Vi; Vi is obtained by Output to the charge domain voltage amplification circuit and be amplified to obtain the error voltage Vop-Von; the K-bit charge domain analog-to-digital converter converts the error voltage Vop-Von to analog-digital conversion to obtain the first group of K-bit quantization codes and output to the control circuit; the control circuit stores the received first group of K-bit quantization codes in its internal K-bit register group, and completes the phase error quantization under the condition of a calibration code.

Immediately afterwards, the control circuit will generate a second group of N-bit calibration code cali(2) and a second group of K-bit selection codes, and the second group of N-bit calibration code cali(2) enters the delay circuit 1 to obtain an N-bit conversion code, N The bit conversion code enters the N-bit digital-to-analog converter circuit to be calibrated, and the differential output current corresponding to the second group of N-bit calibration codes is obtained through digital-to-analog conversion; the reference clock generation circuit is obtained under the control of the K-bit selection code. The second reference clock corresponding to the two sets of N-bit calibration codes; the phase detector obtains the second phase error signal by comparing the second set of input differential voltages with the second reference clock, and the second phase error signal can be obtained through the loop filter and the charge domain voltage amplification circuit. Two sets of error voltage Vop-Von; the K-bit charge domain analog-to-digital converter converts the second set of error voltage Vop-Von to analog-digital conversion, and the second set of K-bit quantization codes can be obtained and output to the control circuit; the control circuit will receive The second group of K-bit quantization codes is stored in its internal K-bit register group to complete phase error quantization under the second calibration code condition.

Then, the control circuit will generate a third group of N-bit calibration codes cali(3) and a third group of K-bit selection codes, and obtain a third group of K-bit quantization codes, and store them in its internal K-bit register group. Cycle in turn, when the controller generates the L group of N-bit calibration code cali(L) and the L-th group of K-bit selection codes, and obtains the L-th group of K-bit quantization codes, and stores them in its internal K-bit register group, The arithmetic circuit inside the control circuit will calculate the L groups of K-bit quantization codes stored in the K-bit register group to obtain the first group of K-bit delay codes. At this time, the control circuit will output the first group of K-bit compensation codes to the delay circuit 1 and keep the first group of K-bit compensation codes unchanged.

Immediately afterwards, the control circuit outputs the calibration control signal clock 2 signal to the delay circuit 2 to control the second delay circuit to enter the calibration mode, and begins to perform phase error calibration of the N-digit digital-to-analog converter circuit 2; The channel DAC phase error calibration circuit adopts the same calibration process as the N-digit digital-to-analog converter circuit 1 to obtain the second group of K-bit delay codes; the control circuit also outputs the second group of K-bit compensation codes to the delay circuit 2, and keeps the first The two sets of K-bit compensation codes remain unchanged. According to the same calibration method, when the control circuit outputs the M-th group of K-bit compensation codes to the delay circuit M, and keeps the M-th group of K-bit compensation codes unchanged, the multi-channel DAC phase error calibration based on charge domain signal processing The calibration mode of the circuit ends.

The control circuit simultaneously sets the delay circuit 1 to the delay circuit M to the compensation mode, and starts to compensate the phase errors of the N-digit digital-to-analog converters 1 to N-digit digital-to-analog converters M. Finally, the control circuit turns off the N-bit calibration code, turns off the phase detector, the loop filter, the charge domain voltage amplifier circuit, the K-bit charge domain analog-to-digital converter, and the reference clock generation circuit. The channel DAC phase error calibration circuit enters compensation mode.

In the above description, N is any positive integer, K is a positive integer not greater than N, L is a positive integer not greater than 2 ^K , and M is any positive integer. In the above-mentioned phase error calibration process, each group of N-bit calibration codes output to the delay circuit and K-bit selection codes output to the reference clock generation circuit simultaneously generated by the control circuit must correspond one-to-one, that is, the J-th group of N-bit calibration codes It must be used in conjunction with the K-bit selection code of the J-th group, and J is a positive integer not greater than L. During the actual use of the phase error calibration circuit of the digital-to-analog converter of the present invention, the accuracy of phase error calibration, the size of hardware overhead and the length of calibration time can be set according to the selection of different K and L values to meet different accuracy and Calibration accuracy and speed requirements for speed DACs.

FIG. 2 shows an implementation of the phase detector circuit of the present invention. The circuit consists of a signal shaping block and a subtractor sub-block. The signal shaping module shapes the input differential signals Voutp and Voutn to obtain the input phase, the reference clock output by the reference clock is used as the reference phase, and the subtractor sub-module subtracts the input phase from the reference phase to obtain the phase error signal Vp.

FIG. 3 is a schematic diagram of the charge domain voltage amplification circuit of the present invention. The charge domain voltage amplifying circuit includes: a first positive terminal charge storage node Nip, a first negative terminal charge storage node Nin, a second positive terminal charge storage node Nop, and a second negative terminal charge storage node Non, one connected between the first and the second A positive-end charge transfer control switch 301 between two positive-end charge storage nodes Nip and Nop, a negative-end charge transfer control switch 302 connected between the first and second negative-end charge storage nodes Nin and Non, connected to the first A positive terminal capacitor 303 connected to the positive terminal charge storage node Nip, a positive terminal capacitance programmable capacitor 309 connected to the second positive terminal charge storage node Nop, a negative terminal capacitor 304 connected to the first negative terminal charge storage node Nin, connected to The negative terminal capacity programmable capacitor 310 connected to the second negative terminal charge storage node Non, the first positive terminal voltage transmission switch 305 connected to the first positive terminal charge storage node Nip, the first positive terminal charge storage node Nip connected to The second positive terminal voltage transmission switch 307, the third positive terminal voltage transmission switch 313 connected to the second positive terminal charge storage node Nop, and the fourth positive terminal voltage transmission switch 311 connected to the second positive terminal charge storage node Nop, connected The first negative terminal voltage transmission switch 306 to the first negative terminal charge storage node Nin, the second negative terminal voltage transmission switch 308 connected to the first negative terminal charge storage node Nin, the second negative terminal voltage transmission switch 308 connected to the second negative terminal charge storage node Non The third negative terminal voltage transmission switch 314 and the fourth negative terminal voltage transmission switch 312 connected to the second negative terminal charge storage node Non. For the embodiment of the present invention, any one of the two analog voltage input terminals of the charge domain voltage amplifying circuit is connected to Vi, and the other terminal is connected to a reference signal.

FIG. 4 is a schematic diagram of a working sequence control waveform of the circuit shown in FIG. 3 . The control clocks Clk and Clkn are clocks with opposite phases, and the switch control signals Clkr, Clks and Clkt are clocks with non-overlapping phases.

Before time t0, all charge storage nodes store independent charges, all voltage transfer switches and charge transfer control switches are in the off state, and the circuit is not started.

When time t0 arrives, the state of Clkr changes, Clkr switches from low level to high level, the first positive terminal voltage transmission switch 307, the third positive terminal voltage transmission switch 311, the first negative terminal voltage transmission switch 308 and The third negative terminal voltage transmission switch 312 is turned on; the first positive terminal charge storage node Nip is reset to the reference voltage 1Vr1 by the first positive terminal voltage transmission switch; the second positive terminal charge storage node Nop is reset by the third positive terminal voltage transmission switch to the reference voltage 2 Vr2; the first negative-end charge storage node Nin is reset to the reference voltage 1 Vr1 by the first negative-end voltage transfer switch; the second negative-end charge storage node Non is reset to the reference voltage 2 by the third negative-end voltage transfer switch Vr2.

When time t1 arrives, the states of Clkr and Clks change, Clkr becomes low level, and Clks switches from low level to high level; the first positive terminal voltage transmission switch 307, the third positive terminal voltage transmission switch 311, The first negative terminal voltage transmission switch 308 and the third negative terminal voltage transmission switch 312 are turned off, the second positive terminal and the negative terminal voltage transmission switch are turned on; the first positive terminal charge storage node Nip is connected by the second positive terminal voltage transmission switch to the input voltage Vip; the first negative terminal charge storage node Nin is connected to the input voltage Vin by the second negative terminal voltage transmission switch; the second positive terminal and the second negative terminal charge storage node No keep Vr2 unchanged.

When time t2 arrives, the states of the control clocks Clks, Clk and Clkn change, Clks becomes low level, Clkn switches from low level to high level, and Clk switches from high level to low level. The charges stored in the capacitors connected to each charge storage node will not change abruptly, the voltages on all charge storage nodes will undergo a step change, and the voltages on the first positive terminal and the first negative terminal charge storage node will be pulled down, And the voltage on the charge storage node of the second positive terminal and the second negative terminal is pulled up, because there is no discharge path for the charge on the charge storage node at this time, the voltage on the charge storage node of the first positive terminal and the second positive terminal will remain constant and have a significant voltage difference, and the voltages on the first negative and second negative charge storage nodes will remain constant and also have a significant voltage difference.

When time t3 arrives, the switch control signal Clkt of the charge transfer control switch becomes high level, the charge transfer control switch 301 is turned on, and there is a charge discharge path between the first positive terminal and the second positive terminal charge storage node, There is a charge discharge path between the first negative terminal and the second negative terminal charge storage node, because there is an obvious voltage difference between the voltage on the charge storage node at this time, that is, V _Nip is smaller than V _Nop , V _Nin is smaller than V _Non , The existence of the voltage difference will cause an induced electric field between the storage nodes, causing the charge stored on the charge storage node to transfer under the action of the induced electric field. Assuming that the charge moves in the form of electrons, it will cause the first positive terminal and The voltage of the first negative terminal charge storage node increases, the voltage of the second positive terminal and the second negative terminal charge storage node decreases, and as the charge continues to transfer, the voltage difference between the two charge storage nodes continues to decrease, causing charge storage The induced electric field between the nodes gradually decreases, the charge transfer speed decreases, and the voltage change rate also decreases. If the two charge transfer control switches are always turned on, the charge transfer process will continue until the charge storage The voltages between nodes Nip and Nop and Nin and Non are equal, and the induced electric field is zero.

With the arrival of time t4, Clkt becomes low level, the charge transfer control switch is turned off, the charge discharge path between the charge storage nodes is disconnected, and the charge transfer between the charge storage nodes ends. Since there is no bleeder path, the voltage on the charge storage node will remain constant. The charge is transferred from the first positive terminal and the first negative terminal charge storage node to the second positive terminal and the second negative terminal charge storage node.

In the above process, if there is no loss in the charge transfer process, assuming that the capacitance values of the positive terminal capacitor and the positive terminal capacitance programmable capacitor are C ₃₀₃ and C _{309 respectively,} according to the charge conservation principle, the charge is effectively transferred between t ₁ and t ₄ , Calculate the outgoing charge Q _S on C ₃₀₃ .

(1)

After finishing, we can get:

(2)

in, , V _L , VP and V _S are all fixed voltages, V _L is the voltage at point Nip before t3, _VP is the voltage at Nop before t3; V _S is the voltage at _Nip at t4. After the circuit is designed, the disturbance caused by the change of the reference voltage is ignored, and Q _T is a constant. After performing differential processing on formula (2), since the circuit structure is a differential structure, the capacitance values of the positive terminal capacitor and the negative terminal capacitor are equal, and the capacitance values of the positive terminal and negative terminal capacitance programmable capacitors are also equal, Q _T will be Eliminate to get the following formula:

(3)

(4)

After the voltage transmission is completed, the relationship between the output voltage and the input voltage is a linear relationship with an amplification factor of -C ₃₀₃ /C ₃₀₉ .

The charge transmission control switch described in the present invention can be realized by the implementation method described in the invention patent with the invention number 201010291245.6, and the voltage transmission switch can be realized by a general MOS transistor or a BJT switch.

As shown in Figure 5, the K-bit charge domain analog-to-digital converter designed in the present invention includes: P-level pipeline sub-level circuits based on charge domain signal processing technology, the last level (P+1 level) A-bit Flash modulus Converter circuit, delay synchronous register and digital correction circuit module. In addition, the working mode control module is also an auxiliary working module necessary for the operation of the analog-to-digital converter, which is not marked in the figure. In the charge domain analog-to-digital converter circuit in Figure 5, the work of two adjacent sub-level circuits is controlled by two sets of multi-phase clocks, the working states are completely complementary, and the number of sub-level circuits and the number of bits k of each level circuit are the same Can be adjusted flexibly. For example, for a 14-bit analog-to-digital converter with K=14, a structure of 12 levels of 1.5bit/level + 1 level of 2bit Flash with a total of 13 levels can be used, or 4 levels of 2.5bit/level + 3 levels of 1.5bit/level + 1 level of 3bit Flash can be used A total of 8 levels of structure.

The charge domain analog-to-digital converter designed by the present invention includes the following contents: P-level charge domain pipeline sub-level circuit based on charge domain signal processing technology, which is used to perform various processes on the sampled charge packets to complete analog-to-digital conversion and margin Amplify, and input the output digital code of each sub-level circuit to the delay synchronization register, and the charge packet output by each sub-level circuit enters the next level to repeat the above process; the last level (P+1 level) A- bit Flash Analog-to-digital converter circuit, which reconverts the charge packet transmitted by the P-level into a voltage signal, and performs the last-level analog-to-digital conversion work, and inputs the output digital code of the current-level circuit to the delay synchronization register , the circuit at this stage only completes the analog-to-digital conversion without margin amplification; the delay synchronization register is used to delay align the digital codes output by each sub-pipeline stage, and input the aligned digital codes to the digital correction module ; A digital correction circuit module, which is used to receive the output digital code of the synchronous register, and shift and add the received digital code to obtain the R-bit digital output code of the analog-to-digital converter.

Figure 6 shows the schematic diagram of the sub-stage circuit of the charge domain pipeline. The circuit is composed of a fully differential signal processing channel. The whole circuit includes: 2 current-stage charge transfer control switches, 2 charge storage nodes, 6 charge storage capacitors connected to the charge storage nodes, C charge comparators, and C receivers The reference signal selection circuit controlled by the output result of the comparator, 2B+2 voltage transmission switches, where B is a positive integer. When the circuit is working normally, the front-stage differential charge packet is first transmitted through the charge transmission control switch and stored in the charge storage node of the current stage. Voltage 4 is compared to obtain the C-bit quantized output digital codes D1~DB of this stage; the digital output codes D1~DB will be output to the delay synchronization register, and at the same time D1~DB will also control the reference signal selection circuit of the stage respectively, so that They respectively generate a pair of complementary reference signals to respectively control the charge addition and subtraction capacitor bottom plate of the positive and negative terminals of the current stage, and perform corresponding addition and subtraction processing on the differential charge packets transmitted from the previous stage to the current stage to obtain the differential residual charge packets of the current stage ; Finally, the circuit completes the transmission of the differential residual charge packet of the current stage from the current stage to the next stage, the reference voltage 2 resets the differential charge storage node of the current stage, and completes the work of a complete clock cycle of the sub-stage circuit of the charge domain pipeline. Among them, C is a positive integer.

It can be seen from Fig. 6 that the charge domain pipeline sub-stage circuit of the present invention has a single-ended form including: a charge transfer control switch, one end of the charge transfer control switch is connected to the charge storage node of the charge domain pipeline sub-stage circuit of the upper stage, and the other One end is the charge storage node of the current-level circuit, the charge storage node of the current-level circuit is respectively connected to the control clock through the first capacitor, connected to the reference signal through the second capacitor, and also connected to the input terminals of one or more comparators, And connected to the reference voltage through a voltage transmission switch, the reference signal is generated by a reference signal selection circuit controlled by the result of the comparator; the full differential form of the charge domain sub-stage pipeline circuit except the last stage is composed of two groups of connection methods The above-mentioned single-ended form charge domain sub-stage pipeline circuit is formed by complementary connection, and the working phase of the control clock is the same as that of the single-ended form.

For the last stage (P+1 stage) of the charge domain pipeline analog-to-digital converter designed by the present invention in Fig. 5, the pipeline sub-stage circuit A-bit Flash analog-to-digital converter circuit based on the charge domain signal processing technology, the sub-stage The circuit only needs to perform the final analog-to-digital conversion on the received charge packet, and input the output digital code of this stage circuit to the delay synchronous register without margin processing. Just remove the reference signal selection circuit in Figure 6 and the 4 capacitors controlled by the reference signal selection circuit. In the above description, both P and A are any positive integers not greater than K.

Fig. 7 is a structural block diagram of the reference clock generation circuit of the present invention. The reference clock generation circuit includes: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit. Both the programmable frequency adjustment circuit and the programmable duty cycle adjustment circuit are controlled by a K-bit selection code. Under the control of the K-bit selection code, after the input clock with fixed frequency and duty ratio passes through the programmable frequency adjustment circuit and the programmable duty ratio adjustment circuit successively, the reference clocks with different frequencies and duty ratios can be obtained Clock Clkref.

Fig. 8 is a structural block diagram of the delay circuit of the present invention. The delay circuit includes: a delay buffer unit 1 to a delay buffer unit N and a K-bit delay register 1 to a K-bit delay register N. The delay code input ends of the K-bit delay register 1～K-bit delay register N are all connected to the K-bit delay code, and the control signal input terminals are all connected to the clock X, where X is a positive integer not greater than M; the delay buffer unit 1～delay The delay code input terminals of the time buffer unit N are respectively connected to the delay code output terminals of the K-bit delay register 1 to the K-bit delay register N, and the data output terminals of the delay buffer unit 1 to the delay buffer unit N are respectively connected to the first bit Conversion code to Nth bit conversion code and output, the first control signal input terminals of delay buffer unit 1 to delay buffer unit N are all connected to Ctrln, the second control signal of delay buffer unit 1 to delay buffer unit N The inputs are all connected to clock X. Wherein, clock X and Ctrln are reverse clocks, and clock X is any one of the calibration control signal clock 1 to clock M output by the control circuit.

The delay circuit can work in two modes of calibration and compensation under the control of the clock X signal. In the calibration mode, the clock X signal is valid, the 1st to Nth input code is invalid, and the input code has no effect on the output of the N-bit conversion code, and the 1st to Nth calibration codes are respectively passed After the delay buffer circuit 1 ~ delay buffer circuit N, the conversion code of the 1st bit to the Nth bit is obtained and output, and the K-bit delay code is input into the K-bit delay register 1 ~ K-bit delay register N and latched constant. In the compensation mode, the Ctrln signal is valid, the conversion code of the 1st digit to the input code of the Nth digit is valid, and the conversion code of the 1st digit to the Nth digit is obtained and output after the delay buffer circuit, and the calibration code of the first digit ~The Nth calibration code is invalid, and the K-bit delay code stored in the K-bit delay register 1~K-bit delay register N is input to the delay buffer circuit 1~Delay buffer circuit N for delay compensation

Fig. 9 is a block diagram of the control circuit of the present invention. The control circuit includes: a core control circuit, a calibration code generation circuit, a selection code generation circuit, an operation circuit, a K-bit register group, delay code output register 1 to delay code output register M and a channel selection circuit.

The connection relationship of the control circuit is: the first output end of the core control circuit is connected to the input end of the calibration code generation circuit, the second output end of the core control circuit is connected to the control input end of the channel selection circuit, and the first output end of the core control circuit is connected to the input end of the channel selection circuit. The three output ends are connected to the control input end of the arithmetic circuit, the fourth output end of the core control circuit is connected to the control input end of the selection code generation circuit, the fifth output end of the core control circuit is connected to the control input end of the K-bit register group, The sixth to M+5th output ends of the core control circuit generate calibration control signal clock 1 to clock M, and the input end of the core control circuit is connected to the calibration start control signal;

The calibration code generation circuit generates N-bit calibration codes according to the control instructions of the core control circuit; the data input terminal of the arithmetic circuit receives the data sent by the output terminal of the K-bit register group, and generates a K-bit error code according to the control instructions of the core control circuit; the delay code The data input ends of output register 1 ~ delay code output register M are all connected to the K-bit error code output end of the arithmetic circuit, and the control signal input ends of delay code output register 1 ~ delay code output register M are respectively connected to the calibration control signal clock 1 ~ The clock M, the output terminals of delay code output register 1 ~ delay code output register M are respectively connected to the 1st ~ M data input terminals of the channel selection circuit; the channel selection circuit outputs K-bit delay codes to all channels according to the control instructions of the core control circuit Delay circuit 1 ~ delay circuit M; selection code generating circuit generates K-bit selection code according to the control instruction of the core control circuit; the data input terminal of the K-bit register group receives the output terminal of the K-bit charge domain analog-to-digital converter. K-bit quantization code, and send the data stored in its internal register to the operation circuit according to the control instruction of the core control circuit.

The K-bit register group described in the circuit shown in Figure 9 has the same number of internal K-bit registers as the phase error calibration circuit of the digital-to-analog converter of the present invention to the single-channel N-bit digital-to-analog converter phase error detection times. , must be L. In the calibration mode of the calibration control signals clock 1 to clock M, only one signal is valid at any time. For the processing and calculation of the L K-bit quantized codes stored in the L K-bit registers, the operation circuit can calculate the best error compensation amount by means of quantizing code error statistics and averaging, and generate K-bit error code.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (10)

1. Multichannel DAC phase error calibration circuit based on charge domain signal processing, characterized by includes: the circuit comprises a current detection resistor Rd, a reference clock generating circuit, a phase discriminator, a loop filter, a charge domain voltage amplifying circuit, a K-bit charge domain analog-to-digital converter, a control circuit and a group of delay circuits;

the connection relationship of the circuits is as follows: two ends of the current detection resistor Rd are respectively connected to a first input end and a second input end of the phase discriminator; the control input end of the reference clock generating circuit is connected to the K bit selection code output port of the control circuit, and the reference clock output end of the reference clock generating circuit is connected to the third input end of the phase discriminator; the phase error signal output end Vp of the phase discriminator is connected to the input end of the loop filter; the output voltage Vi of the loop filter is input to the analog signal input end of the charge domain voltage amplifying circuit; the differential signal output end of the charge domain voltage amplifying circuit is connected to the differential voltage input end of the K-bit charge domain analog-to-digital converter; the K bit quantization code of the K bit charge domain analog-to-digital converter is output to an error input port of the control circuit; the output ends of an N-bit calibration code and a K-bit delay code of the control circuit are respectively connected to the first input port and the second input port of all the delay circuits, a calibration control signal clock X of the control circuit is linked to a third input port of the delay circuit X, and the output port of a calibration control signal Ctrl of the control circuit is simultaneously connected to the input ports of a phase discriminator, a loop filter, a charge domain voltage amplification circuit and a calibration control signal Ctrl of a K-bit charge domain analog-to-digital converter; the N-bit input code X is connected to a fourth input port of the delay circuit X, and an output port of the delay circuit X is connected to a decoding circuit of the N-bit digital-to-analog converter X;

wherein N and M are any positive integer, K is a positive integer not greater than N, and X is a positive integer not greater than M.

2. The phase error calibration circuit of a multi-pass digital-to-analog converter based on charge domain signal processing as claimed in claim 1, characterized by comprising a calibration mode and a compensation mode; when the circuit works, the circuit firstly enters a calibration mode and then enters a compensation mode;

when the multi-channel digital-to-analog converter enters a calibration mode, all N-bit input codes and K-bit delay codes are invalid, the N-bit calibration codes are input into all delay circuits, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing sequentially performs phase error calibration on the N-bit digital-to-analog converters of M channels; when the multi-channel DAC enters a compensation mode, an N-bit input code X is input into a delay circuit X, an N-bit calibration code is invalid, a K-bit delay code is valid, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing simultaneously carries out phase compensation on an N-bit digital-to-analog converter of an M channel.

3. A multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 2, characterised in that when entering the calibration mode the circuit operates in the following sequence:

the control circuit firstly controls the phase discriminator, the loop filter, the charge domain voltage amplifying circuit and the K-bit charge domain analog-to-digital converter to enter a calibration mode, and simultaneously outputs a K-bit selection code to the reference clock generating circuit and also enters the calibration mode; in addition, a clock 1 signal of a calibration control signal is output to the delay circuit 1 to control the delay circuit 1 to enter a calibration mode, and the phase error calibration of the N-bit digital-to-analog converter circuit 1 is started;

the control circuit then generates a first set of N-bit calibration codes and a first set of K-bit selection codes; the first group of N-bit calibration codes enter a delay circuit and obtain N-bit conversion codes, and the N-bit conversion codes enter an N-bit digital-to-analog converter circuit 1 to be calibrated; a reference clock generating circuit obtains a first reference clock corresponding to the N-bit calibration code; the first input end and the second input end of the phase discriminator circuit can obtain an input differential voltage, and a phase error signal Vp is obtained by comparing the input differential voltage with a first reference clock; the Vp signal is filtered by a loop filter and amplified by a charge domain voltage amplifying circuit to obtain an error voltage; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the error voltage to obtain a first group of K-bit quantization codes and outputs the first group of K-bit quantization codes to the control circuit; the control circuit stores the received first group of K-bit quantization codes in a K-bit register group inside the control circuit to finish phase error quantization under the condition of a calibration code;

sequentially circulating, when the controller generates an L-th group of N-bit calibration codes and an L-th group of K-bit selection codes, an L-th group of K-bit quantization codes are obtained and stored in a K-bit register group in the controller, an operation circuit in the control circuit calculates the L-th group of K-bit quantization codes stored in the K-bit register group to obtain a first group of K-bit delay codes; the control circuit outputs the first group of K-bit compensation codes to the delay circuit 1 at the moment, and keeps the first group of K-bit compensation codes unchanged to finish the phase error calibration of the N-bit digital-to-analog converter circuit 1;

next, the control circuit outputs a calibration control signal clock 2 signal to control the delay circuit 2 to enter a calibration mode, and starts to perform phase error calibration of the N-bit digital-to-analog converter circuit 2; the multichannel DAC phase error calibration circuit based on charge domain signal processing obtains a second group of K-bit delay codes by adopting the same calibration process as the N-bit digital-to-analog converter circuit 1; the control circuit outputs the second group of K-bit compensation codes to the delay circuit 2, and keeps the second group of K-bit compensation codes unchanged, so as to finish the phase error calibration of the N-bit digital-to-analog converter circuit 2;

according to the same calibration mode, the control circuit outputs the Y-th group of K-bit compensation codes to the delay circuit Y and keeps the Y-th group of K-bit compensation codes unchanged; when the control circuit outputs the Mth group of K bit compensation codes to the delay circuit M and keeps the Mth group of K bit compensation codes unchanged, the calibration mode of the multi-channel DAC phase error calibration circuit based on the charge domain signal processing is ended;

wherein L is not more than 2^KY is a positive integer greater than 1 and less than M.

4. A multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 2, characterised in that when entering the compensation mode the circuit operates in the following sequence:

the control circuit sets all the delay circuits to be in a compensation mode simultaneously and starts to compensate the phase error of the N-bit digital-to-analog converter of the M channel;

and finally, the control circuit turns off the N-bit calibration code, and closes the phase discriminator, the loop filter, the charge domain voltage amplification circuit, the K-bit charge domain analog-to-digital converter and the reference clock generation circuit.

5. A multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 3, characterized by:

when the circuit enters the calibration mode, each group of the N-bit calibration codes output to the compensation circuit and the K-bit selection codes output to the reference clock generation circuit, which are simultaneously generated by the control circuit, must correspond to one another, namely: the J-th group of N-bit calibration codes and the J-th group of K-bit selection codes must be matched for use;

wherein J is a positive integer not greater than L.

6. The multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 1, wherein said K-bit charge domain analog-to-digital converter comprises: the P-stage pipeline sub-stage circuit based on the charge domain signal processing technology is used for carrying out various processing on the charge packets obtained by sampling to complete analog-to-digital conversion and margin amplification, inputting the output digital code of each sub-stage circuit into a delay synchronous register, and enabling the charge packets output by each sub-stage circuit to enter the next stage to repeat the process; the last stage (P +1 stage) A-bit Flash analog-to-digital converter circuit converts the charge packet transmitted by the Nth stage into a voltage signal again, performs analog-to-digital conversion work of the last stage, inputs the output digital code of the stage circuit into a delay synchronous register, and only completes analog-to-digital conversion without margin amplification; the delay synchronous register is used for carrying out delay alignment on the digital code output by each sub-flow water level and inputting the aligned digital code to the digital correction module; the digital correction circuit module is used for receiving the output digital code of the synchronous register and carrying out shift addition on the received digital code to obtain an R-bit digital output code of the analog-to-digital converter;

wherein, P and A are any positive integer not more than K.

7. The multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 1, wherein said reference clock generation circuit comprises: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit; the programmable frequency adjusting circuit and the programmable duty cycle adjusting circuit are both controlled by a K-bit selection code; under the control of the K-bit selection code, the input clock with fixed frequency and duty ratio passes through the programmable frequency adjusting circuit and the programmable duty ratio adjusting circuit in sequence, and then the reference clocks with different frequencies and duty ratios can be obtained.

8. The multi-channel DAC phase error calibration circuit based on charge domain signal processing according to claim 1, wherein said delay circuit internally comprises: a group of delay buffer units and a group of K-bit delay registers;

the delay code input ends of all the K-bit delay registers are all connected to the K-bit delay codes, and the control signal input ends are all connected to the clock X;

the input end of a delay code of the delay buffer unit X is connected to the output end of a delay code of the K-bit delay register X, the data output end of the delay buffer unit X is connected to the X-th conversion code and outputs the X-th conversion code, the first control signal input end of the delay buffer unit X is connected to Ctrln, and the second control signal input end of the delay buffer unit X is connected to the clock X;

where the clocks X and ctrl n are inverted clocks.

9. The multi-channel DAC phase error calibration circuit based on charge domain signal processing according to claim 8, wherein said delay circuit is operable in both calibration and compensation modes;

in the calibration mode, a clock X signal is valid, a Z-th bit input code is invalid, the input code has no influence on the output of the N-bit conversion code, the Z-th bit calibration code obtains the Z-th bit conversion code after passing through a delay buffer circuit Z and is output, and a K-bit delay code is input into a K-bit delay register Z and is latched and kept unchanged;

in the compensation mode, the Ctrln signal is valid, the Z-th bit input code is valid, the Z-th bit conversion code is obtained and output after passing through the delay buffer circuit, the Z-th bit calibration code is invalid, and the K-bit delay code stored in the K-bit delay register Z is input into the delay buffer circuit Z for delay compensation;

wherein Z is any positive integer not greater than N.

10. The charge domain signal processing based multi-channel DAC phase error calibration circuit of claim 1, wherein the control circuit comprises: the device comprises a core control circuit, a calibration code generating circuit, a selection code generating circuit, an arithmetic circuit, a K-bit register group, a group of delay code output registers and a channel selection circuit; the connection relation of the control circuit is as follows:

a first output end of the core control circuit is connected to an input end of the calibration code generating circuit, a second output end of the core control circuit is connected to a control input end of the channel selection circuit, a third output end of the core control circuit is connected to a control input end of the arithmetic circuit, a fourth output end of the core control circuit is connected to a control input end of the selection code generating circuit, a fifth output end of the core control circuit is connected to a control input end of the K-bit register group, a Wth output end of the core control circuit generates a calibration control signal clock X, and an input end of the core control circuit is connected to a calibration starting control signal;

the calibration code generating circuit generates an N-bit calibration code according to a control instruction of the core control circuit; the data input end of the arithmetic circuit receives the data sent by the output end of the K-bit register group and generates a K-bit error code according to a control instruction of the core control circuit; the data input ends of all delay code output registers are all connected to the K-bit error code output end of the arithmetic circuit, the control signal input end of a delay code output register X is connected with a calibration control signal clock X, and the output end of the delay code output register X is connected to the Xth data input end of the channel selection circuit; the channel selection circuit outputs a K-bit delay code to the delay circuit X according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the data input end of the K-bit register group receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter, and sends the data stored in the internal register of the K-bit charge domain analog-to-digital converter to the arithmetic circuit according to the control instruction of the core control circuit;

wherein W is any positive integer greater than 5 and less than M + 5.