CN107070450A - Multichannel DAC phase errors calibration circuit based on charge-domain signal transacting - Google Patents
Multichannel DAC phase errors calibration circuit based on charge-domain signal transacting Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
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- H—ELECTRICITY
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Abstract
Circuit is calibrated the invention provides a kind of multichannel DAC phase errors based on charge-domain signal transacting, it is characterized in that including：Current sense resistor Rd, reference clock generation circuit, phase discriminator, loop filter, charge-domain voltage amplifier circuit, K charge-domain analog-digital converters, control circuit and 1~delay circuit of delay circuit M.The error calibration circuit includes calibration mode and compensation model, and calibration mode is introduced into when circuit works, compensation model is entered afterwards.The charge-domain Small Current Signal amplifying circuit can be widely applied in the detection and amplification system of all kinds of electric signals.
Description
Technical Field
The invention relates to an error calibration circuit, in particular to a circuit for self-calibrating phase errors among multi-channel DACs by adopting a charge domain signal processing technology.
Background
A digital-to-analog converter (DAC) is an electronic circuit that converts an input digital signal to an output analog signal. The value represented by the digital signal input to the DAC corresponds to the amplitude of the analog signal output by the DAC. Various factors determine the performance of the DAC, including speed, resolution, and noise.
The current steering dac is the most popular high-speed high-precision dac architecture at present, and generally includes a decoding circuit, a latch array and a current cell array. The decoding circuit converts an input binary digital signal into a thermometer-coded digital signal and inputs the thermometer-coded digital signal into the latch array, the latch performs synchronous processing on the digital signal output by the decoding circuit by using a clock signal and transmits the synchronous digital signal to the current cell, the current cell determines the flow direction of the current cell according to the input digital signal, and thus, the digital-to-analog converter completes the conversion from the input digital signal to the output analog signal.
However, because the latch array and the current cell array are mismatched, there is a delay difference between the outputs of different current cell units, and the delay difference greatly reduces the dynamic performance of the digital-to-analog converter, and therefore a certain correction method is required to remove the delay difference. Especially, when multi-channel DACs are integrated on the same chip, delay and phase asynchronism among the DACs of different channels can be obvious, and the phase asynchronism has great influence on system performances such as radar, multi-channel wireless communication and the like. It is therefore of practical significance to design a circuit that can self-calibrate the phase error between multi-channel DACs.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a circuit for self-calibrating phase errors among multi-channel DACs.
The purpose of the invention can be realized by the following technical scheme:
a multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized by comprising: the circuit comprises a current detection resistor Rd, a reference clock generating circuit, a phase discriminator, a loop filter, a charge domain voltage amplifying circuit, a K-bit charge domain analog-to-digital converter, a control circuit and a group of delay circuits;
the connection relationship of the circuits is as follows: the current detection resistor Rd is connected with a differential current output end of the M-channel to-be-calibrated N-bit digital-to-analog converter and is respectively connected with a first input end and a second input end of the phase discriminator; the control input end of the reference clock generating circuit is connected to the K bit selection code output port of the control circuit, and the reference clock output end of the reference clock generating circuit is connected to the third input end of the phase discriminator; the phase error signal output end Vp of the phase discriminator is connected to the input end of the loop filter; the output voltage Vi of the loop filter is input to the analog signal input end of the charge domain voltage amplifying circuit; the differential signal output end of the charge domain voltage amplifying circuit is connected to the differential voltage input end of the K-bit charge domain analog-to-digital converter; the K bit quantization code of the K bit charge domain analog-to-digital converter is output to an error input port of the control circuit; the output ends of an N-bit calibration code and a K-bit delay code of the control circuit are respectively connected to the first input port and the second input port of all the delay circuits, a calibration control signal clock X of the control circuit is linked to a third input port of the delay circuit X, and the output port of a calibration control signal Ctrl of the control circuit is simultaneously connected to the input ports of a phase discriminator, a loop filter, a charge domain voltage amplification circuit and a calibration control signal Ctrl of a K-bit charge domain analog-to-digital converter; the N-bit input code X is connected to a fourth input port of the delay circuit X, and an output port of the delay circuit X is connected to a decoding circuit of the N-bit digital-to-analog converter X;
wherein N and M are any positive integer, K is a positive integer not greater than N, and X is a positive integer not greater than M.
The multi-pass digital-to-analog converter phase error calibration circuit based on charge domain signal processing is characterized by comprising a calibration mode and a compensation mode; when the circuit works, the circuit firstly enters a calibration mode and then enters a compensation mode;
when the multi-channel digital-to-analog converter enters a calibration mode, all N-bit input codes and K-bit delay codes are invalid, the N-bit calibration codes are input into all delay circuits, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing sequentially performs phase error calibration on the N-bit digital-to-analog converters of M channels; when the multi-channel DAC enters a compensation mode, an N-bit input code X is input into a delay circuit X, an N-bit calibration code is invalid, a K-bit delay code is valid, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing simultaneously carries out phase compensation on an N-bit digital-to-analog converter of an M channel.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that when a calibration mode is entered, the working sequence of the circuit is as follows:
the control circuit firstly controls the phase discriminator, the loop filter, the charge domain voltage amplifying circuit and the K-bit charge domain analog-to-digital converter to enter a calibration mode, and simultaneously outputs a K-bit selection code to the reference clock generating circuit and also enters the calibration mode; in addition, a clock 1 signal of a calibration control signal is output to the delay circuit 1 to control the delay circuit 1 to enter a calibration mode, and the phase error calibration of the N-bit digital-to-analog converter circuit 1 is started;
the control circuit then generates a first set of N-bit calibration codes and a first set of K-bit selection codes; the first group of N-bit calibration codes enter a delay circuit and obtain N-bit conversion codes, and the N-bit conversion codes enter an N-bit digital-to-analog converter circuit 1 to be calibrated; a reference clock generating circuit obtains a first reference clock corresponding to the N-bit calibration code; the first input end and the second input end of the phase discriminator circuit can obtain an input differential voltage, and a phase error signal Vp is obtained by comparing the input differential voltage with a first reference clock; the Vp signal is filtered by a loop filter and amplified by a charge domain voltage amplifying circuit to obtain an error voltage; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the error voltage to obtain a first group of K-bit quantization codes and outputs the first group of K-bit quantization codes to the control circuit; the control circuit stores the received first group of K-bit quantization codes in a K-bit register group inside the control circuit to finish phase error quantization under the condition of a calibration code;
sequentially circulating, when the controller generates an L-th group of N-bit calibration codes and an L-th group of K-bit selection codes, an L-th group of K-bit quantization codes are obtained and stored in a K-bit register group in the controller, an operation circuit in the control circuit calculates the L-th group of K-bit quantization codes stored in the K-bit register group to obtain a first group of K-bit delay codes; the control circuit outputs the first group of K-bit compensation codes to the delay circuit 1 at the moment, and keeps the first group of K-bit compensation codes unchanged to finish the phase error calibration of the N-bit digital-to-analog converter circuit 1;
next, the control circuit outputs a calibration control signal clock 2 signal to control the delay circuit 2 to enter a calibration mode, and starts to perform phase error calibration of the N-bit digital-to-analog converter circuit 2; the multichannel DAC phase error calibration circuit based on charge domain signal processing obtains a second group of K-bit delay codes by adopting the same calibration process as the N-bit digital-to-analog converter circuit 1; the control circuit outputs the second group of K-bit compensation codes to the delay circuit 2, and keeps the second group of K-bit compensation codes unchanged, so as to finish the phase error calibration of the N-bit digital-to-analog converter circuit 2;
according to the same calibration mode, the control circuit outputs the Y-th group of K-bit compensation codes to the delay circuit Y and keeps the Y-th group of K-bit compensation codes unchanged; when the control circuit outputs the Mth group of K bit compensation codes to the delay circuit M and keeps the Mth group of K bit compensation codes unchanged, the calibration mode of the multi-channel DAC phase error calibration circuit based on the charge domain signal processing is ended;
wherein L is not more than 2KY is a positive integer greater than 1 and less than M.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that when a compensation mode is entered, the working sequence of the circuit is as follows: the control circuit sets all the delay circuits to be in a compensation mode simultaneously and starts to compensate the phase error of the N-bit digital-to-analog converter of the M channel; and finally, the control circuit turns off the N-bit calibration code, and closes the phase discriminator, the loop filter, the charge domain voltage amplification circuit, the K-bit charge domain analog-to-digital converter and the reference clock generation circuit.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that: when the circuit enters the calibration mode, each group of the N-bit calibration codes output to the compensation circuit and the K-bit selection codes output to the reference clock generation circuit, which are simultaneously generated by the control circuit, must correspond to one another, namely: the J-th group of N-bit calibration codes and the J-th group of K-bit selection codes must be matched for use;
wherein J is a positive integer not greater than L.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the K-bit charge domain analog-to-digital converter comprises: the P-stage pipeline sub-stage circuit based on the charge domain signal processing technology is used for carrying out various processing on the charge packets obtained by sampling to complete analog-to-digital conversion and margin amplification, inputting the output digital code of each sub-stage circuit into a delay synchronous register, and enabling the charge packets output by each sub-stage circuit to enter the next stage to repeat the process; the last stage (P +1 stage) A-bit Flash analog-to-digital converter circuit converts the charge packet transmitted by the Nth stage into a voltage signal again, performs analog-to-digital conversion work of the last stage, inputs the output digital code of the stage circuit into a delay synchronous register, and only completes analog-to-digital conversion without margin amplification; the delay synchronous register is used for carrying out delay alignment on the digital code output by each sub-flow water level and inputting the aligned digital code to the digital correction module; the digital correction circuit module is used for receiving the output digital code of the synchronous register and carrying out shift addition on the received digital code to obtain an R-bit digital output code of the analog-to-digital converter;
wherein, P and A are any positive integer not more than K.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the reference clock generation circuit comprises: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit; the programmable frequency adjusting circuit and the programmable duty cycle adjusting circuit are both controlled by a K-bit selection code; under the control of the K-bit selection code, the input clock with fixed frequency and duty ratio passes through the programmable frequency adjusting circuit and the programmable duty ratio adjusting circuit in sequence, and then the reference clocks with different frequencies and duty ratios can be obtained.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the delay circuit internally comprises: a group of delay buffer units and a group of K-bit delay registers;
the delay code input ends of all the K-bit delay registers are all connected to the K-bit delay codes, and the control signal input ends are all connected to the clock X; the input end of a delay code of the delay buffer unit X is connected to the output end of a delay code of the K-bit delay register X, the data output end of the delay buffer unit X is connected to the X-th conversion code and outputs the X-th conversion code, the first control signal input end of the delay buffer unit X is connected to Ctrln, and the second control signal input end of the delay buffer unit X is connected to the clock X;
where the clocks X and ctrl n are inverted clocks.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the delay circuit can work in two modes of a calibration mode and a compensation mode; in the calibration mode, a clock X signal is valid, a Z-th bit input code is invalid, the input code has no influence on the output of the N-bit conversion code, the Z-th bit calibration code obtains the Z-th bit conversion code after passing through a delay buffer circuit Z and is output, and a K-bit delay code is input into a K-bit delay register Z and is latched and kept unchanged; in the compensation mode, the Ctrln signal is valid, the Z-th bit input code is valid, the Z-th bit conversion code is obtained and output after passing through the delay buffer circuit, the Z-th bit calibration code is invalid, and the K-bit delay code stored in the K-bit delay register Z is input into the delay buffer circuit Z for delay compensation; wherein Z is any positive integer not greater than N.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing is characterized in that the control circuit comprises: the device comprises a core control circuit, a calibration code generating circuit, a selection code generating circuit, an arithmetic circuit, a K-bit register group, a group of delay code output registers and a channel selection circuit; the connection relation of the control circuit is as follows:
a first output end of the core control circuit is connected to an input end of the calibration code generating circuit, a second output end of the core control circuit is connected to a control input end of the channel selection circuit, a third output end of the core control circuit is connected to a control input end of the arithmetic circuit, a fourth output end of the core control circuit is connected to a control input end of the selection code generating circuit, a fifth output end of the core control circuit is connected to a control input end of the K-bit register group, a Wth output end of the core control circuit generates a calibration control signal clock X, and an input end of the core control circuit is connected to a calibration starting control signal;
the calibration code generating circuit generates an N-bit calibration code according to a control instruction of the core control circuit; the data input end of the arithmetic circuit receives the data sent by the output end of the K-bit register group and generates a K-bit error code according to a control instruction of the core control circuit; the data input ends of all delay code output registers are all connected to the K-bit error code output end of the arithmetic circuit, the control signal input end of a delay code output register X is connected with a calibration control signal clock X, and the output end of the delay code output register X is connected to the Xth data input end of the channel selection circuit; the channel selection circuit outputs a K-bit delay code to the delay circuit X according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the data input end of the K-bit register group receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter, and sends the data stored in the internal register of the K-bit charge domain analog-to-digital converter to the arithmetic circuit according to the control instruction of the core control circuit;
wherein W is any positive integer greater than 5 and less than M + 5.
The invention has the advantages that: the high-precision phase error calibration circuit can automatically compromise and select calibration precision according to system precision and hardware overhead, and has the characteristic of low power consumption.
Drawings
FIG. 1 is a block diagram of a multi-channel DAC phase error calibration circuit based on charge domain signal processing.
Fig. 2 is a schematic diagram of the phase detector circuit of the present invention.
FIG. 3 is a schematic diagram of a charge domain voltage amplifying circuit according to the present invention.
FIG. 4 is a waveform diagram illustrating the operation of the charge domain voltage amplifying circuit according to the present invention.
FIG. 5 is a block diagram of a charge domain analog-to-digital converter circuit according to the present invention.
FIG. 6 is a block diagram of a charge domain pipeline sub-stage of the present invention.
FIG. 7 is a block diagram of a reference clock generating circuit according to the present invention.
Fig. 8 is a block diagram of the delay circuit structure of the present invention.
FIG. 9 is a block diagram of a control circuit according to the present invention.
Detailed Description
Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a block diagram of a multi-channel DAC phase error calibration circuit based on charge domain signal processing according to the present invention. The multi-channel DAC phase error calibration circuit based on charge domain signal processing comprises: the circuit comprises a current detection resistor Rd, a reference clock generating circuit, a phase discriminator, a loop filter, a charge domain voltage amplifying circuit, a K-bit charge domain analog-to-digital converter, a control circuit and a group of delay circuits.
The connection relationship of the circuits is as follows: two ends of the current detection resistor Rd are connected with a differential current output end of the M-channel to-be-calibrated N-bit digital-to-analog converter and are respectively connected to a first input end and a second input end of the phase discriminator; the control input end of the reference clock generating circuit is connected to the K bit selection code output port of the control circuit, and the reference clock output end of the reference clock generating circuit is connected to the third input end of the phase discriminator; the phase error signal output end Vp of the phase discriminator is connected to the input end of the loop filter; the output voltage Vi of the loop filter is input to the analog signal input end of the charge domain voltage amplifying circuit; the differential signal output end of the charge domain voltage amplifying circuit is connected to the differential voltage input end of the K-bit charge domain analog-to-digital converter; the K bit quantization code of the K bit charge domain analog-to-digital converter is output to an error input port of the control circuit; the output ends of an N-bit calibration code and a K-bit delay code of the control circuit are respectively connected to first and second input ports of the delay circuit 1-the delay circuit M, signal ports of a calibration control signal clock 1-the clock M of the control circuit are respectively linked to third input ports of the delay circuit 1-the delay circuit M, and an output port of a calibration control signal Ctrl of the control circuit is simultaneously connected to input ports of calibration control signals Ctrl of a phase discriminator, a loop filter, a charge domain voltage amplifying circuit and a K-bit charge domain analog-to-digital converter; the N-bit input codes 1-N-bit input codes M are respectively connected to the fourth input ports of the delay circuits 1-M, and the output ports of the delay circuits 1-M are respectively connected to the decoding circuits of the N-bit digital-to-analog converters 1-M.
The multi-channel DAC phase error calibration circuit based on charge domain signal processing comprises two working modes, namely a calibration mode and a compensation mode. When the circuit works, firstly entering a calibration mode and then entering a compensation mode; when entering a calibration mode, an N-bit input code and a K-bit delay code are invalid, the N-bit calibration code is input into the delay circuit 1 to the delay circuit M, and the multichannel DAC phase error calibration circuit based on charge domain signal processing sequentially carries out phase error calibration on the N-bit digital-to-analog converter 1 to the N-bit digital-to-analog converter M; when the multi-channel DAC enters a compensation mode, N-bit input codes 1-N-bit input codes M are respectively input into the delay circuit 1-delay circuit M, the N-bit calibration codes are invalid, the K-bit delay codes are valid, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing simultaneously performs phase compensation on the N-bit digital-to-analog converters 1-N.
The working principle of the circuit is as follows: when the calibration mode is started, the control circuit firstly controls the phase discriminator, the loop filter, the charge domain voltage amplifying circuit and the K-bit charge domain analog-to-digital converter to enter the calibration mode through the Ctrl signal, and simultaneously outputs a K-bit selection code to the reference clock generating circuit to enter the calibration mode; in addition, the output of the calibration control signal clock 1 signal to the delay circuit 1 controls the 1 st delay circuit to enter the calibration mode, and starts the phase error calibration of the N-bit digital-to-analog converter circuit 1.
The control circuit then generates a first set of N-bit calibration codes cali (1) and a first set of K-bit selection codes; a first group of N-bit calibration codes cali (1) enter a delay circuit to obtain N-bit conversion codes, the N-bit conversion codes enter an N-bit digital-to-analog converter circuit 1 to be calibrated, and differential output current corresponding to the N-bit calibration codes is obtained through digital-to-analog conversion; a reference clock generating circuit obtains a first reference clock corresponding to the N-bit calibration code under the control of the first group of K-bit selection codes; because the current detection resistor Rd is respectively connected with the differential current output end of the digital-to-analog converter, the first input end and the second input end of the phase discriminator circuit can obtain an input differential voltage with the size of Voutp-Voutn; because the N-bit digital-to-analog converter to be calibrated has offset errors, the phase discriminator obtains a phase error signal Vp by comparing the input differential voltage with the first reference clock; the Vp signal is filtered by a loop filter to obtain an error voltage Vi; vi is output to a charge domain voltage amplifying circuit and is amplified to obtain an error voltage Vop-Von; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the error voltage Vop-Von to obtain a first group of K-bit quantization codes and outputs the first group of K-bit quantization codes to the control circuit; the control circuit stores the received first group of K-bit quantization codes in a K-bit register group inside the control circuit, and phase error quantization under the condition of a calibration code is completed.
Next, the control circuit generates a second group of N-bit calibration codes cali (2) and a second group of K-bit selection codes, the second group of N-bit calibration codes cali (2) enters the delay circuit 1 to obtain N-bit conversion codes, the N-bit conversion codes enter the N-bit digital-to-analog converter circuit to be calibrated, and differential output currents corresponding to the second group of N-bit calibration codes are obtained through digital-to-analog conversion; the reference clock generating circuit obtains a second reference clock corresponding to a second group of N-bit calibration codes under the control of the K-bit selection codes; the phase discriminator obtains a second phase error signal by comparing a second group of input differential voltages with a second reference clock, and a second group of error voltages Vop-Von can be obtained through the loop filter and the charge domain voltage amplifying circuit; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the second group of error voltages Vop-Von to obtain a second group of K-bit quantization codes and outputs the second group of K-bit quantization codes to the control circuit; the control circuit stores the received second group of K-bit quantization codes in the internal K-bit register group to finish the phase error quantization under the condition of the second calibration code.
Then, the control circuit will generate a third set of N-bit calibration code cali (3) and a third set of K-bit selection code, and obtain a third set of K-bit quantization code, which is stored in its internal K-bit register set. And sequentially circulating, wherein when the controller generates an L-th group of N-bit calibration codes cali (L) and an L-th group of K-bit selection codes, and an L-th group of K-bit quantization codes are obtained and stored in a K-bit register group in the controller, an operation circuit in the control circuit calculates the L-th group of K-bit quantization codes stored in the K-bit register group to obtain a first group of K-bit delay codes. The control circuit will output the first set of K-bit compensation codes to the delay circuit 1 and keep the first set of K-bit compensation codes unchanged.
Next, the control circuit outputs a clock 2 signal of the calibration control signal to the delay circuit 2 to control the 2 nd delay circuit to enter the calibration mode, and starts to calibrate the phase error of the N-bit digital-to-analog converter circuit 2; the multichannel DAC phase error calibration circuit based on charge domain signal processing obtains a second group of K-bit delay codes by adopting the same calibration process as the N-bit digital-to-analog converter circuit 1; the control circuit likewise outputs the second set of K-bit compensation codes into the delay circuit 2 and keeps the second set of K-bit compensation codes unchanged. In the same calibration manner, when the control circuit outputs the Mth group of K bit compensation codes to the delay circuit M and keeps the Mth group of K bit compensation codes unchanged, the calibration mode of the multi-channel DAC phase error calibration circuit based on charge domain signal processing is ended.
The control circuit sets the delay circuit 1 to the delay circuit M to a compensation mode at the same time, and starts to compensate for phase errors of the N-bit digital-to-analog converters 1 to M. And finally, the control circuit turns off the N-bit calibration code, the phase discriminator, the loop filter, the charge domain voltage amplification circuit, the K-bit charge domain analog-to-digital converter and the reference clock generation circuit are closed, and the multi-channel DAC phase error calibration circuit based on the charge domain signal processing enters a compensation mode.
In the above description, N is any positive integer, K is a positive integer not greater than N, and L is not greater than 2KM is any positive integer. In the phase error calibration process, each set of N-bit calibration codes output to the delay circuit and K-bit selection codes output to the reference clock generation circuit, which are simultaneously generated by the control circuit, must correspond to each other one by one, that is: the J-th group of N-bit calibration codes and the J-th group of K-bit selection codes must be matched for use, and J is a positive integer not larger than L. In the practical use process of the phase error calibration circuit of the digital-to-analog converter, the accuracy of phase error calibration, the hardware overhead and the calibration time can be performed according to different K and L valuesAnd setting to meet the calibration accuracy and speed requirements of digital-to-analog converters with different accuracies and speeds.
Fig. 2 shows an implementation of the phase detector circuit according to the invention. The circuit is composed of a signal shaping module and a subtracter submodule. The signal shaping module shapes the input differential signals Voutp and Voutn to obtain an input phase, a reference clock output by the reference clock is used as a reference phase, and the subtractor submodule subtracts the input phase from the reference phase to obtain a phase error signal Vp.
Fig. 3 is a schematic diagram of a charge domain voltage amplifying circuit according to the present invention. The charge domain voltage amplifying circuit includes: a first positive side charge storage node Nip, a first negative side charge storage node Nin, a second positive side charge storage node Nop and a second negative side charge storage node Non, a positive side charge transfer control switch 301 connected between the first and second positive side charge storage nodes Nip and Nop, a negative side charge transfer control switch 302 connected between the first and second negative side charge storage nodes Nin and Non, a positive side capacitor 303 connected to the first positive side charge storage node Nip, a positive capacitance value programmable capacitor 309 connected to the second positive side charge storage node Nop, a negative side capacitor 304 connected to the first negative side charge storage node Nin, a negative capacitance value programmable capacitor 310 connected to the second negative side charge storage node Non, a first positive side voltage transfer switch 305 connected to the first positive side charge storage node Nip, a second positive side voltage transfer switch 307 connected to the first positive side charge storage node Nip, A third positive side voltage transfer switch 313 connected to the second positive side charge storage node Nop and a fourth positive side voltage transfer switch 311 connected to the second positive side charge storage node Nop, a first negative side voltage transfer switch 306 connected to the first negative side charge storage node Nin, a second negative side voltage transfer switch 308 connected to the first negative side charge storage node Nin, a third negative side voltage transfer switch 314 connected to the second negative side charge storage node Non and a fourth negative side voltage transfer switch 312 connected to the second negative side charge storage node Non. For the embodiment of the invention, one end of any one of two analog voltage input ends of the charge domain voltage amplifying circuit is connected with Vi, and the other end is connected with a reference signal.
FIG. 4 is a waveform diagram illustrating the operation timing control of the circuit shown in FIG. 3. The control clocks Clk and Clkn are clocks of opposite phases, and the switch control signals Clkr, Clks, and Clkt are clocks of non-overlapping phases.
Until time t0, all of the charge storage nodes have their own independent charge stored thereon, all of the voltage transfer switches and charge transfer control switches are closed, and the circuit is inactive.
When the time t0 comes, the state of Clkr changes, Clkr switches from low level to high level, and the first positive terminal voltage transmission switch 307, the third positive terminal voltage transmission switch 311, the first negative terminal voltage transmission switch 308, and the third negative terminal voltage transmission switch 312 are turned on; the first positive side charge storage node Nip is reset by the first positive side voltage transfer switch to the reference voltage 1Vr 1; the second positive side charge storage node Nop is reset to the reference voltage 2 Vr2 by the third positive side voltage transfer switch; the first negative side charge storage node Nin is reset to the reference voltage 1Vr1 by the first negative side voltage transfer switch; the second negative side charge storage node Non is reset to the reference voltage 2 Vr2 by the third negative side voltage transfer switch.
When the time t1 comes, the states of Clkr and Clks change, Clkr changes to low level, and Clks switches from low level to high level; the first positive side voltage transfer switch 307, the third positive side voltage transfer switch 311, the first negative side voltage transfer switch 308, and the third negative side voltage transfer switch 312 are turned off, and the second positive side and negative side voltage transfer switches are turned on; the first positive side charge storage node Nip is connected to the input voltage Vip by a second positive side voltage transfer switch; the first negative side charge storage node Nin is connected to the input voltage Vin by a second negative side voltage transfer switch; the second positive terminal and second negative terminal charge storage node No hold Vr2 constant.
When time t2 arrives, the states of the control clocks Clks, Clk, and Clkn change, Clks changes to a low level, Clkn switches from a low level to a high level, and Clk switches from a high level to a low level, at which time, since the charges stored on the capacitors connected to the charge storage nodes do not change abruptly, the voltages on all the charge storage nodes change in steps, the voltages on the first positive side and first negative side charge storage nodes are pulled low, and the voltages on the second positive side and second negative side charge storage nodes are pulled high, since there is no bleed path for the charges on the charge storage nodes at this time, the voltages on the first positive side and second positive side charge storage nodes will remain unchanged and there will be a significant voltage difference, and the voltages on the first negative side and second negative side charge storage nodes will remain unchanged and also have a significant voltage difference.
When the time t3 comes, the switch control signal Clkt of the charge transfer control switch changes to high level, the charge transfer control switch 301 is turned on, a charge bleed path exists between the first positive terminal and the second positive terminal charge storage node, a charge bleed path exists between the first negative terminal and the second negative terminal charge storage node, and since there is an obvious voltage difference in the voltage at the charge storage node, i.e., VNipLess than VNop，VNinLess than VNonIf the charges move in the form of electrons, the voltages of the charge storage nodes at the first positive end and the first negative end are increased, the voltages of the charge storage nodes at the second positive end and the second negative end are decreased, the induced electric field between the charge storage nodes is gradually decreased along with the continuous transfer of the charges, the charge transfer speed is continuously decreased, the voltage change rate is also decreased, and if the two charge transfer control switches are always turned on, the charge transfer process is continued until the voltages between the charge storage nodes Nip and Nop and between Nip and Non are equal, and the induced electric field is 0.
With the arrival of the time t4, Clkt becomes low, the charge transfer control switch is turned off, the charge draining path existing between the charge storage nodes is disconnected, and the charge transfer operation between the charge storage nodes is ended. Since there is no bleed path, the voltage on the charge storage node will remain unchanged. Charge transfer from the first positive and first negative side charge storage nodes to the second positive and second negative side charge storage nodes is accomplished.
In the above process, if there is no loss in the charge transfer process, it is assumed that the capacitance values of the positive side capacitor and the positive side capacitor programmable capacitor are respectively C303And C309，According to the theorem of conservation of charge,t 1tot 4Effective charge transfer between, calculatingC 303Upward transferred electric chargeQ S。
（1）
After finishing, the following can be obtained:
（2）
wherein,，V L、V PandV Sare all at a fixed voltage and are,V Lthe voltage at the Nip point before time t3,V Pvoltage at Nop point before time t 3;V Sis the voltage at the Nip point at time t 4. After the circuit is designed, the disturbance caused by the change of the reference voltage is ignored,Q Tis a constant. After the differential processing is performed on the formula (2), because the circuit structure is a differential structure, the capacitance values of the positive end capacitor and the negative end capacitor are equal, and the capacitance values of the positive end capacitor and the negative end capacitor programmable capacitor are also equal,Q Twill be eliminated, giving the following formula:
（3）
（4）
after the voltage transmission is completed, the output voltage and the input voltage have the relation that the amplification factor is-C303/C309The linear relationship of (c).
The charge transmission control switch can be realized by the embodiment of the invention patent with the invention number of 201010291245.6, and the voltage transmission switch can be realized by a general MOS transistor or a BJT switch.
As shown in fig. 5, the K-bit charge domain analog-to-digital converter of the present invention comprises: the device comprises a P-stage pipeline sub-stage circuit based on a charge domain signal processing technology, a last stage (P +1 st stage) A-bit Flash analog-to-digital converter circuit, a delay synchronous register and a digital correction circuit module. In addition, the operation mode control module is also an auxiliary operation module necessary for the operation of the analog-to-digital converter, and is not identified in the figure. The operation of two adjacent stages of sub-stage circuits in the charge domain analog-to-digital converter circuit in fig. 5 is controlled by two groups of multiphase clocks, the operation states are completely complementary, and the stage number of the sub-stage circuits and the bit number k of each stage of circuit can be flexibly adjusted. For example, for a 14-bit analog-to-digital converter with K ═ 14, a structure with 13 stages of 12 stages, 1.5 bits/stage and 1 stage, 2 bits Flash, or a structure with 8 stages of 4 stages, 2.5 bits/stage and 3 stages, 1.5 bits/stage and 1 stage, 3 bits Flash, may be adopted.
The charge domain analog-to-digital converter comprises the following contents: the P-stage charge domain pipeline sub-stage circuit based on the charge domain signal processing technology is used for carrying out various processing on the charge packets obtained by sampling to complete analog-to-digital conversion and margin amplification, inputting the output digital code of each sub-stage circuit into a delay synchronous register, and enabling the charge packets output by each sub-stage circuit to enter the next stage to repeat the process; the last stage (P +1 stage) A-bit Flash analog-to-digital converter circuit converts the charge packet transmitted by the P stage into a voltage signal again, performs analog-to-digital conversion work of the last stage, inputs the output digital code of the stage circuit into a delay synchronous register, and only completes analog-to-digital conversion without margin amplification; the delay synchronous register is used for carrying out delay alignment on the digital code output by each sub-flow water level and inputting the aligned digital code to the digital correction module; and the digital correction circuit module is used for receiving the output digital code of the synchronous register and carrying out shift addition on the received digital code to obtain an R-bit digital output code of the analog-to-digital converter.
Fig. 6 is a schematic diagram of a charge domain pipeline sub-stage circuit. The circuit is formed by fully differential signal processing channels, and the whole circuit comprises: the circuit comprises 2 current-stage charge transfer control switches, 2 charge storage nodes, 6 charge storage capacitors connected to the charge storage nodes, C charge comparators, C reference signal selection circuits controlled by output results of the comparators and 2B +2 voltage transfer switches, wherein B is a positive integer. When the circuit normally works, a preceding stage differential charge packet is transmitted through a charge transmission control switch and stored in a current stage charge storage node, and a comparator compares the voltage difference variable quantity between the nodes caused by the input of the differential charge packet with a reference voltage 3 and a reference voltage 4 to obtain a current stage C bit quantized output digital code D1-DB; the digital output codes D1-DB are output to a delay synchronous register, and D1-DB respectively control the reference signal selection circuit of the stage to generate a pair of complementary reference signals to respectively control the positive and negative end charges of the stage to add and subtract the capacitor bottom plate, and carry out addition and subtraction processing with corresponding size on the differential charge packet transmitted to the stage from the previous stage to obtain the differential residual charge packet of the stage; and finally, the circuit completes transmission of the current-stage differential residual charge packet from the current stage to the next stage, and the reference voltage 2 resets the current-stage differential charge storage node to complete the work of one complete clock cycle of the charge domain pipeline sub-stage circuit. Wherein C is a positive integer.
In fig. 6, it can be seen that the charge domain pipeline sub-stage circuit of the present invention comprises, in single-ended form: a charge transmission control switch, one end of the charge transmission control switch is connected with the charge storage node of the previous stage charge domain pipeline sub-stage circuit, the other end is the charge storage node of the current stage circuit, the charge storage node of the current stage circuit is respectively connected with a control clock through a first capacitor, is connected with a reference signal through a second capacitor, is also connected to the input ends of one or more comparators and is connected to a reference voltage through a voltage transmission switch, and the reference signal is generated by a reference signal selection circuit controlled by the result of the comparator; the charge domain sub-stage pipeline circuit except the last stage is formed by complementary connection of two groups of single-ended charge domain sub-stage pipeline circuits which are connected in the same way, and the working phase of the control clock is the same as the single-ended form.
For the last stage (the P +1 st stage) of the charge domain pipeline analog-to-digital converter designed in the invention in fig. 5, the pipeline sub-stage circuit A-bit Flash analog-to-digital converter circuit based on the charge domain signal processing technology only needs to perform the analog-to-digital conversion work of the last stage on the received charge packet, and inputs the digital code output by the sub-stage circuit into the delay synchronous register without performing margin processing. The reference signal selection circuit and the 4 capacitors controlled by the reference signal selection circuit in fig. 6 may be eliminated. In the above description, P and A are any positive integer not greater than K.
FIG. 7 is a block diagram of a reference clock generating circuit according to the present invention. The reference clock generating circuit includes: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit. The programmable frequency adjusting circuit and the programmable duty cycle adjusting circuit are both controlled by a K-bit selection code. Under the control of the K bit selection code, the input clock with fixed frequency and duty ratio passes through the programmable frequency adjusting circuit and the programmable duty ratio adjusting circuit in sequence, and then the reference clock Clkref with different frequency and duty ratio can be obtained.
Fig. 8 is a block diagram of the delay circuit according to the present invention. The delay circuit internally includes: delay buffer unit 1-delay buffer unit N and K-bit delay register 1-K-bit delay register N. The input ends of delay codes of the K-bit delay registers 1-N are all connected to the K-bit delay codes, the input ends of control signals are all connected to a clock X, and X is a positive integer not greater than M; the input ends of delay codes of the delay buffer units 1 to N are respectively connected to the output ends of delay codes of the K-bit delay registers 1 to N, the data output ends of the delay buffer units 1 to N are respectively connected to and output from the 1 st bit conversion code to the Nth bit conversion code, the input ends of first control signals of the delay buffer units 1 to N are all connected to Ctrln, and the input ends of second control signals of the delay buffer units 1 to N are all connected to the clock X. The clock X and the clock Ctrln are reverse clocks, and the clock X is any one of the calibration control signal clocks 1-clock M output by the control circuit.
The delay circuit is operable in both a calibration mode and a compensation mode under control of the clock X signal. In the calibration mode, a clock X signal is valid, a 1 st bit conversion code to an Nth bit input code are invalid, the input codes have no influence on the output of the N bit conversion code, the 1 st bit calibration code to the Nth bit calibration code respectively pass through a delay buffer circuit 1 to a delay buffer circuit N to obtain the 1 st bit conversion code to the Nth bit conversion code and are output, and a K bit delay code is input into a K bit delay register 1 to a K bit delay register N and is latched and kept unchanged. In the compensation mode, Ctrln signals are valid, the 1 st to Nth bit conversion codes are valid and output after passing through the delay buffer circuit, the 1 st to Nth bit conversion codes are obtained and output, the 1 st to Nth bit calibration codes are invalid, and the K bit delay codes stored in the K bit delay registers 1 to N are input into the delay buffer circuit 1 to N for delay compensation
Fig. 9 is a block diagram of the control circuit according to the present invention. The control circuit includes: the circuit comprises a core control circuit, a calibration code generating circuit, a selection code generating circuit, an arithmetic circuit, a K-bit register group, a delay code output register 1-a delay code output register M and a channel selection circuit.
The connection relation of the control circuit is as follows: a first output end of the core control circuit is connected to an input end of the calibration code generating circuit, a second output end of the core control circuit is connected to a control input end of the channel selection circuit, a third output end of the core control circuit is connected to a control input end of the arithmetic circuit, a fourth output end of the core control circuit is connected to a control input end of the selection code generating circuit, a fifth output end of the core control circuit is connected to a control input end of the K-bit register group, sixth to M +5 output ends of the core control circuit generate calibration control signal clocks 1 to M, and an input end of the core control circuit is connected to a calibration start control signal;
the calibration code generating circuit generates an N-bit calibration code according to a control instruction of the core control circuit; the data input end of the arithmetic circuit receives the data sent by the output end of the K-bit register group and generates a K-bit error code according to a control instruction of the core control circuit; the data input ends of the delay code output register 1 to the delay code output register M are all connected to the K-bit error code output end of the arithmetic circuit, the control signal input ends of the delay code output register 1 to the delay code output register M are respectively connected with the calibration control signal clock 1 to the clock M, and the output ends of the delay code output register 1 to the delay code output register M are respectively connected to the 1 st to the Mth data input ends of the channel selection circuit; the channel selection circuit outputs K bit delay codes to the delay circuit 1-the delay circuit M according to the control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; and the data input end of the K-bit register group receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter, and sends the data stored in the internal register of the K-bit charge domain analog-to-digital converter to the arithmetic circuit according to the control instruction of the core control circuit.
In the K-bit register set in the circuit shown in fig. 9, the number of K-bit registers inside the K-bit register set is the same as the number of times of detecting the phase error of the single-channel N-bit digital-to-analog converter by the phase error calibration circuit of the digital-to-analog converter of the present invention, and must be L. And in the calibration mode, only one signal is valid at any time when the calibration control signal clocks 1-M are in the calibration mode. The arithmetic circuit can calculate the optimal error compensation quantity for the processing calculation of L K bit quantization codes stored in L K bit registers by adopting the methods of quantization code error statistics and averaging, and generate K bit error codes.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like that fall within the spirit and principle of the present invention are intended to be included therein.
Claims (10)
1. Multichannel DAC phase error calibration circuit based on charge domain signal processing, characterized by includes: the circuit comprises a current detection resistor Rd, a reference clock generating circuit, a phase discriminator, a loop filter, a charge domain voltage amplifying circuit, a K-bit charge domain analog-to-digital converter, a control circuit and a group of delay circuits;
the connection relationship of the circuits is as follows: two ends of the current detection resistor Rd are respectively connected to a first input end and a second input end of the phase discriminator; the control input end of the reference clock generating circuit is connected to the K bit selection code output port of the control circuit, and the reference clock output end of the reference clock generating circuit is connected to the third input end of the phase discriminator; the phase error signal output end Vp of the phase discriminator is connected to the input end of the loop filter; the output voltage Vi of the loop filter is input to the analog signal input end of the charge domain voltage amplifying circuit; the differential signal output end of the charge domain voltage amplifying circuit is connected to the differential voltage input end of the K-bit charge domain analog-to-digital converter; the K bit quantization code of the K bit charge domain analog-to-digital converter is output to an error input port of the control circuit; the output ends of an N-bit calibration code and a K-bit delay code of the control circuit are respectively connected to the first input port and the second input port of all the delay circuits, a calibration control signal clock X of the control circuit is linked to a third input port of the delay circuit X, and the output port of a calibration control signal Ctrl of the control circuit is simultaneously connected to the input ports of a phase discriminator, a loop filter, a charge domain voltage amplification circuit and a calibration control signal Ctrl of a K-bit charge domain analog-to-digital converter; the N-bit input code X is connected to a fourth input port of the delay circuit X, and an output port of the delay circuit X is connected to a decoding circuit of the N-bit digital-to-analog converter X;
wherein N and M are any positive integer, K is a positive integer not greater than N, and X is a positive integer not greater than M.
2. The phase error calibration circuit of a multi-pass digital-to-analog converter based on charge domain signal processing as claimed in claim 1, characterized by comprising a calibration mode and a compensation mode; when the circuit works, the circuit firstly enters a calibration mode and then enters a compensation mode;
when the multi-channel digital-to-analog converter enters a calibration mode, all N-bit input codes and K-bit delay codes are invalid, the N-bit calibration codes are input into all delay circuits, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing sequentially performs phase error calibration on the N-bit digital-to-analog converters of M channels; when the multi-channel DAC enters a compensation mode, an N-bit input code X is input into a delay circuit X, an N-bit calibration code is invalid, a K-bit delay code is valid, and the multi-channel DAC phase error calibration circuit based on charge domain signal processing simultaneously carries out phase compensation on an N-bit digital-to-analog converter of an M channel.
3. A multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 2, characterised in that when entering the calibration mode the circuit operates in the following sequence:
the control circuit firstly controls the phase discriminator, the loop filter, the charge domain voltage amplifying circuit and the K-bit charge domain analog-to-digital converter to enter a calibration mode, and simultaneously outputs a K-bit selection code to the reference clock generating circuit and also enters the calibration mode; in addition, a clock 1 signal of a calibration control signal is output to the delay circuit 1 to control the delay circuit 1 to enter a calibration mode, and the phase error calibration of the N-bit digital-to-analog converter circuit 1 is started;
the control circuit then generates a first set of N-bit calibration codes and a first set of K-bit selection codes; the first group of N-bit calibration codes enter a delay circuit and obtain N-bit conversion codes, and the N-bit conversion codes enter an N-bit digital-to-analog converter circuit 1 to be calibrated; a reference clock generating circuit obtains a first reference clock corresponding to the N-bit calibration code; the first input end and the second input end of the phase discriminator circuit can obtain an input differential voltage, and a phase error signal Vp is obtained by comparing the input differential voltage with a first reference clock; the Vp signal is filtered by a loop filter and amplified by a charge domain voltage amplifying circuit to obtain an error voltage; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the error voltage to obtain a first group of K-bit quantization codes and outputs the first group of K-bit quantization codes to the control circuit; the control circuit stores the received first group of K-bit quantization codes in a K-bit register group inside the control circuit to finish phase error quantization under the condition of a calibration code;
sequentially circulating, when the controller generates an L-th group of N-bit calibration codes and an L-th group of K-bit selection codes, an L-th group of K-bit quantization codes are obtained and stored in a K-bit register group in the controller, an operation circuit in the control circuit calculates the L-th group of K-bit quantization codes stored in the K-bit register group to obtain a first group of K-bit delay codes; the control circuit outputs the first group of K-bit compensation codes to the delay circuit 1 at the moment, and keeps the first group of K-bit compensation codes unchanged to finish the phase error calibration of the N-bit digital-to-analog converter circuit 1;
next, the control circuit outputs a calibration control signal clock 2 signal to control the delay circuit 2 to enter a calibration mode, and starts to perform phase error calibration of the N-bit digital-to-analog converter circuit 2; the multichannel DAC phase error calibration circuit based on charge domain signal processing obtains a second group of K-bit delay codes by adopting the same calibration process as the N-bit digital-to-analog converter circuit 1; the control circuit outputs the second group of K-bit compensation codes to the delay circuit 2, and keeps the second group of K-bit compensation codes unchanged, so as to finish the phase error calibration of the N-bit digital-to-analog converter circuit 2;
according to the same calibration mode, the control circuit outputs the Y-th group of K-bit compensation codes to the delay circuit Y and keeps the Y-th group of K-bit compensation codes unchanged; when the control circuit outputs the Mth group of K bit compensation codes to the delay circuit M and keeps the Mth group of K bit compensation codes unchanged, the calibration mode of the multi-channel DAC phase error calibration circuit based on the charge domain signal processing is ended;
wherein L is not more than 2KY is a positive integer greater than 1 and less than M.
4. A multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 2, characterised in that when entering the compensation mode the circuit operates in the following sequence:
the control circuit sets all the delay circuits to be in a compensation mode simultaneously and starts to compensate the phase error of the N-bit digital-to-analog converter of the M channel;
and finally, the control circuit turns off the N-bit calibration code, and closes the phase discriminator, the loop filter, the charge domain voltage amplification circuit, the K-bit charge domain analog-to-digital converter and the reference clock generation circuit.
5. A multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 3, characterized by:
when the circuit enters the calibration mode, each group of the N-bit calibration codes output to the compensation circuit and the K-bit selection codes output to the reference clock generation circuit, which are simultaneously generated by the control circuit, must correspond to one another, namely: the J-th group of N-bit calibration codes and the J-th group of K-bit selection codes must be matched for use;
wherein J is a positive integer not greater than L.
6. The multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 1, wherein said K-bit charge domain analog-to-digital converter comprises: the P-stage pipeline sub-stage circuit based on the charge domain signal processing technology is used for carrying out various processing on the charge packets obtained by sampling to complete analog-to-digital conversion and margin amplification, inputting the output digital code of each sub-stage circuit into a delay synchronous register, and enabling the charge packets output by each sub-stage circuit to enter the next stage to repeat the process; the last stage (P +1 stage) A-bit Flash analog-to-digital converter circuit converts the charge packet transmitted by the Nth stage into a voltage signal again, performs analog-to-digital conversion work of the last stage, inputs the output digital code of the stage circuit into a delay synchronous register, and only completes analog-to-digital conversion without margin amplification; the delay synchronous register is used for carrying out delay alignment on the digital code output by each sub-flow water level and inputting the aligned digital code to the digital correction module; the digital correction circuit module is used for receiving the output digital code of the synchronous register and carrying out shift addition on the received digital code to obtain an R-bit digital output code of the analog-to-digital converter;
wherein, P and A are any positive integer not more than K.
7. The multi-channel DAC phase error calibration circuit based on charge domain signal processing as claimed in claim 1, wherein said reference clock generation circuit comprises: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit; the programmable frequency adjusting circuit and the programmable duty cycle adjusting circuit are both controlled by a K-bit selection code; under the control of the K-bit selection code, the input clock with fixed frequency and duty ratio passes through the programmable frequency adjusting circuit and the programmable duty ratio adjusting circuit in sequence, and then the reference clocks with different frequencies and duty ratios can be obtained.
8. The multi-channel DAC phase error calibration circuit based on charge domain signal processing according to claim 1, wherein said delay circuit internally comprises: a group of delay buffer units and a group of K-bit delay registers;
the delay code input ends of all the K-bit delay registers are all connected to the K-bit delay codes, and the control signal input ends are all connected to the clock X;
the input end of a delay code of the delay buffer unit X is connected to the output end of a delay code of the K-bit delay register X, the data output end of the delay buffer unit X is connected to the X-th conversion code and outputs the X-th conversion code, the first control signal input end of the delay buffer unit X is connected to Ctrln, and the second control signal input end of the delay buffer unit X is connected to the clock X;
where the clocks X and ctrl n are inverted clocks.
9. The multi-channel DAC phase error calibration circuit based on charge domain signal processing according to claim 8, wherein said delay circuit is operable in both calibration and compensation modes;
in the calibration mode, a clock X signal is valid, a Z-th bit input code is invalid, the input code has no influence on the output of the N-bit conversion code, the Z-th bit calibration code obtains the Z-th bit conversion code after passing through a delay buffer circuit Z and is output, and a K-bit delay code is input into a K-bit delay register Z and is latched and kept unchanged;
in the compensation mode, the Ctrln signal is valid, the Z-th bit input code is valid, the Z-th bit conversion code is obtained and output after passing through the delay buffer circuit, the Z-th bit calibration code is invalid, and the K-bit delay code stored in the K-bit delay register Z is input into the delay buffer circuit Z for delay compensation;
wherein Z is any positive integer not greater than N.
10. The charge domain signal processing based multi-channel DAC phase error calibration circuit of claim 1, wherein the control circuit comprises: the device comprises a core control circuit, a calibration code generating circuit, a selection code generating circuit, an arithmetic circuit, a K-bit register group, a group of delay code output registers and a channel selection circuit; the connection relation of the control circuit is as follows:
a first output end of the core control circuit is connected to an input end of the calibration code generating circuit, a second output end of the core control circuit is connected to a control input end of the channel selection circuit, a third output end of the core control circuit is connected to a control input end of the arithmetic circuit, a fourth output end of the core control circuit is connected to a control input end of the selection code generating circuit, a fifth output end of the core control circuit is connected to a control input end of the K-bit register group, a Wth output end of the core control circuit generates a calibration control signal clock X, and an input end of the core control circuit is connected to a calibration starting control signal;
the calibration code generating circuit generates an N-bit calibration code according to a control instruction of the core control circuit; the data input end of the arithmetic circuit receives the data sent by the output end of the K-bit register group and generates a K-bit error code according to a control instruction of the core control circuit; the data input ends of all delay code output registers are all connected to the K-bit error code output end of the arithmetic circuit, the control signal input end of a delay code output register X is connected with a calibration control signal clock X, and the output end of the delay code output register X is connected to the Xth data input end of the channel selection circuit; the channel selection circuit outputs a K-bit delay code to the delay circuit X according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the data input end of the K-bit register group receives the K-bit quantization code sent by the output end of the K-bit charge domain analog-to-digital converter, and sends the data stored in the internal register of the K-bit charge domain analog-to-digital converter to the arithmetic circuit according to the control instruction of the core control circuit;
wherein W is any positive integer greater than 5 and less than M + 5.
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| CN108233906A (en) * | 2018-02-07 | 2018-06-29 | 中国电子科技集团公司第三十八研究所 | A kind of booting certainty delayed time system and method based on ADC |
| CN108631783B (en) * | 2018-06-08 | 2021-07-06 | 中国电子科技集团公司第五十八研究所 | Reference voltage mismatch calibration circuit for multichannel ADC |
| CN108631783A (en) * | 2018-06-08 | 2018-10-09 | 中国电子科技集团公司第五十八研究所 | A kind of reference voltage mismatch calibration circuit for multichannel ADC |
| CN108768395A (en) * | 2018-06-08 | 2018-11-06 | 中国电子科技集团公司第五十八研究所 | A kind of gain mismatch errors for multichannel ADC calibrate circuit |
| CN108768396A (en) * | 2018-06-08 | 2018-11-06 | 中国电子科技集团公司第五十八研究所 | A kind of clock phase mismatch calibration circuit for multichannel ADC |
| CN108768396B (en) * | 2018-06-08 | 2022-05-06 | 中国电子科技集团公司第五十八研究所 | Clock phase mismatch calibration circuit for multichannel ADC |
| CN108768395B (en) * | 2018-06-08 | 2021-09-07 | 中国电子科技集团公司第五十八研究所 | Gain mismatch error calibration circuit for multi-channel ADC |
| CN109660254A (en) * | 2018-12-05 | 2019-04-19 | 南京国博电子有限公司 | A kind of resistance calibration device and method for digital analog converter |
| CN111812619A (en) * | 2020-06-23 | 2020-10-23 | 深圳市精嘉微电子有限公司 | Device and method for measuring edge arrival time of picosecond-level resolution electric signal |
| CN111812619B (en) * | 2020-06-23 | 2023-03-21 | 深圳市精嘉微电子有限公司 | Device and method for measuring edge arrival time of picosecond-level resolution electric signal |
| CN112737573A (en) * | 2020-12-21 | 2021-04-30 | 南京极景微半导体有限公司 | Clock skew calibration system, method and equipment based on daisy chain and computer storage medium |
| CN112924849A (en) * | 2021-01-27 | 2021-06-08 | 胜达克半导体科技(上海)有限公司 | Error compensation calculation method applied to phase adjustment circuit |
| CN112924849B (en) * | 2021-01-27 | 2023-02-28 | 胜达克半导体科技(上海)有限公司 | Error compensation calculation method applied to phase adjustment circuit |
| CN113125940A (en) * | 2021-04-16 | 2021-07-16 | 桥弘数控科技（上海）有限公司 | Circuit board correction method and device and electronic equipment |
| CN113125940B (en) * | 2021-04-16 | 2022-08-23 | 桥弘数控科技（上海）有限公司 | Circuit board correction method and device and electronic equipment |
| CN114499147A (en) * | 2022-02-24 | 2022-05-13 | 浙江赛思电子科技有限公司 | Calibration circuit, calibration method, calibration device and medium of delay circuit |
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