CN108768395B - Gain mismatch error calibration circuit for multi-channel ADC - Google Patents
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Abstract
The invention provides a gain mismatch error calibration circuit for a multi-channel ADC (analog to digital converter), and belongs to the technical field of integrated circuits. The gain mismatch error calibration circuit for the multichannel ADC comprises a reference voltage generation circuit, a reference voltage remote driving circuit, M reference voltage adjusting circuits, an M-channel N-bit analog-to-digital converter, M N-bit output registers, a calibration reference signal generation circuit, an N-bit digital subtraction circuit and a control circuit. The gain mismatch error calibration circuit for the multichannel ADC can automatically compromise and select calibration accuracy according to system accuracy and hardware overhead, and has the characteristic of low power consumption.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a gain mismatch error calibration circuit for a multi-channel ADC (analog to digital converter).
Background
A pipeline ADC (analog-to-digital converter) with 14-bit precision and sampling rate of more than 100MSPS is always the main choice of various intermediate frequency sampling systems, and is therefore widely applied to electronic application systems such as multi-carrier broadband wireless communication and radar reception. In order to reduce cost and improve reliability, various electronic systems have increasingly high demands for low power consumption and miniaturization, and the requirements for power consumption and area of ADC circuits used in the electronic systems are increasingly strict. In order to improve the integration level of the pipeline ADC, a single chip integrated multi-channel ADC circuit is usually used to reduce the space occupied by the board-level system design. In order to realize multi-channel integration of the pipeline ADC circuit, the core circuit of the single-channel pipeline ADC used in the circuit has some special requirements: firstly, the ADC kernel must have the characteristics of low power consumption and small area, otherwise, the power consumption and reliability problems caused by multi-channel integration can greatly limit the application of a board-level system; secondly, the ADC core must use as few output ports as possible, otherwise, the packaging problem caused by integration and the wiring problem of the high-speed signal line of the board-level system both cause great limitations.
In addition, when the multi-channel ADCs are integrated on the same chip, matching errors occur in gains between the multi-channel ADCs due to mismatching of device parameters between different chip areas. Particularly for high-speed high-precision ADCs, the influence of gain mismatching among ADCs of different channels is very obvious, and the mismatching error asynchronization has larger influence on the system performances of radar, multi-channel wireless communication and the like. Therefore, a certain correction method is needed to remove the gain mismatch error. It is therefore of practical interest to design a circuit that can self-calibrate the gain mismatch error between multi-channel ADCs.
Disclosure of Invention
The invention aims to provide a gain mismatch error calibration circuit for a multi-channel ADC (analog to digital converter), which is used for solving the problem of gain mismatch among different channel ADCs.
To solve the above technical problem, the present invention provides a gain mismatch error calibration circuit for a multi-channel ADC, comprising: the device comprises a reference voltage generating circuit, a reference voltage remote driving circuit, M reference voltage adjusting circuits, an N-bit analog-to-digital converter of an M channel, M N-bit output registers, a calibration reference signal generating circuit, an N-bit digital subtraction circuit and a control circuit; each reference voltage adjusting circuit, the N-bit analog-to-digital converter of each channel and each N-bit output register correspond to each other one by one;
the reference voltage generating circuit generates a reference voltage and inputs the reference voltage to the reference voltage remote driving circuit; m paths of output reference voltages of the reference voltage remote driving circuit are respectively connected to reference voltage input ends of M reference voltage adjusting circuits, and an M +1 th output reference voltage Vrinref is connected to a reference voltage input end of a calibration reference signal generating circuit; m control signals output by M control signal output ends of the control circuit are respectively connected with control signal input ends of M reference voltage adjusting circuits, and K-bit compensation codes 1-M output by M K-bit compensation code output ends of the control circuit are respectively connected with compensation code input ends of the M reference voltage adjusting circuits; a reference voltage output end of the reference voltage adjusting circuit is connected with a corresponding N-bit analog-to-digital converter, and a calibration voltage signal output end Vr _ cal of the calibration reference signal generating circuit is connected with the N-bit analog-to-digital converter of the M channel; the N-bit digital code output by the N-bit analog-to-digital converter passes through a corresponding N-bit output register to obtain a quantized code; m +1 groups of digital code input ends of the N-bit digital subtraction circuit are respectively connected to the M N-bit output registers and a reference output quantization code output end Dref of the calibration reference signal generating circuit; the control input end of the calibration reference signal generating circuit is connected to the K bit selection code output port of the control circuit; the K bit quantization code output end of the N bit digital subtraction circuit is connected to the error input end of the control circuit; an output port of a calibration control signal Ctrl _ mode of the control circuit is connected to input ports of calibration control signals of the N-bit digital subtraction circuit and the calibration reference signal generating circuit; the K bit global adjusting code output end of the control circuit is connected with the input end of the reference voltage remote driving circuit;
wherein N and M are any positive integer, and K is a positive integer not greater than N.
Optionally, the gain mismatch error calibration circuit for a multi-channel ADC includes a calibration mode and a compensation mode;
when the multi-channel ADC enters a calibration mode, the gain mismatch error calibration circuit for the multi-channel ADC sequentially performs gain mismatch error calibration on N-bit analog-to-digital converters of M channels to sequentially generate M groups of K-bit compensation codes; when entering the compensation mode, the M groups of K-bit compensation codes are kept unchanged, the gain mismatch error calibration circuit for the multi-channel ADC simultaneously performs gain mismatch error compensation on the N-bit digital-to-analog converter of the M channels, and the calibration reference signal generation circuit and the N-bit digital subtraction circuit are turned off to reduce power consumption.
Optionally, the reference voltage remote driving circuit includes: a reference voltage programming adjustment circuit and M +1 voltage remote driving circuits; the output end of the reference voltage programming adjusting circuit is simultaneously connected with M +1 voltage remote driving circuits; the output voltage of the reference voltage programming adjustment circuit is controlled by the K-bit global adjustment code.
Optionally, the calibration reference signal generating circuit includes: a programmable calibration voltage generating circuit and a reference output quantization code generating circuit;
the reference voltage input end of the programmable calibration voltage generation circuit is connected to the M +1 th output reference voltage Vrinref of the reference voltage remote drive circuit, and the programmable calibration voltage generation circuit outputs calibration reference voltage under the control of the K bit selection code; the reference output quantization code generation circuit outputs a reference output quantization code under the control of the K-bit selection code.
Optionally, the reference output quantization code generating circuit only works in a calibration mode, and includes a ROM lookup table, a ROM module, and a reference quantization code output circuit, all of which are controlled by Ctrl _ mode signals; the K bit selection code enters a ROM lookup table to obtain a corresponding address to be sent to a ROM module, the ROM module outputs reference quantization code data stored in a memory unit corresponding to the corresponding address to a reference quantization code output circuit, and the reference quantization code output circuit outputs a reference output quantization code.
Optionally, the control circuit includes: the circuit comprises a core control circuit, a selection code generating circuit, an adjusting code generating circuit, an arithmetic circuit, a K-bit register group, a compensation code output register 1-a compensation code output register M and a channel selection circuit;
the input end of the core control circuit is connected with a calibration starting signal, the first output end of the core control circuit is connected with the control input end of the channel selection circuit, the second output end of the core control circuit is connected with the control input end of the operation circuit, the third output end of the core control circuit is connected with the control input end of the selection code generation circuit, the fourth output end of the core control circuit is connected with the control input end of the adjustment code generation circuit, the fifth output end of the core control circuit is connected with the control input end of the K-bit register group, and M calibration control signals Ctrl 1-Ctrl M generated by the sixth-to-M + 5-th output ends of the core control circuit are respectively connected with the compensation code output register 1-compensation code output register M; the data input end of the arithmetic circuit receives the data sent by the output end of the K-bit register group and generates a K-bit error code according to a control instruction of the core control circuit; the data input ends of the compensation code output register 1 to the compensation code output register M are all connected to the K-bit error code output end of the operational circuit, and the output ends of the compensation code output register 1 to the compensation code output register M are respectively connected to the 1 st to M th data input ends of the channel selection circuit; the channel selection circuit outputs K-bit compensation codes 1-M according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the adjusting code generating circuit generates a K-bit global adjusting code according to a control instruction of the core control circuit; and the data input end of the K-bit register group receives the K-bit quantization code sent by the output end of the N-bit digital subtraction circuit, and sends the data stored in the internal register of the K-bit register group to the arithmetic circuit according to the control instruction of the core control circuit.
Optionally, in the calibration mode, only one of the calibration control signals Ctrl 1-Ctrl M is valid at any time; in the process of calibrating the N-bit analog-to-digital converter of the M channel, the channel selection circuit opens the output of the compensation code output register corresponding to the N-bit analog-to-digital converter for calibration, and closes the outputs of the other compensation code output registers.
Optionally, the operation circuit generates the K-bit error code by using a binary successive approximation algorithm, and only 1 bit of the K-bit error code is changed in each operation; the final output of the K-bit error code which is kept unchanged needs K times of cyclic operation to be determined.
The invention provides a gain mismatch error calibration circuit for a multi-channel ADC, which comprises: the device comprises a reference voltage generating circuit, a reference voltage remote driving circuit, M reference voltage adjusting circuits, an N-bit analog-to-digital converter of an M channel, M N-bit output registers, a calibration reference signal generating circuit, an N-bit digital subtraction circuit and a control circuit. The gain mismatch error calibration circuit for the multichannel ADC can automatically compromise and select calibration accuracy according to system accuracy and hardware overhead, and has the characteristic of low power consumption.
Drawings
FIG. 1 is a schematic diagram of a gain mismatch error calibration circuit for a multi-channel ADC;
FIG. 2 is a schematic diagram of a reference voltage remote driving circuit;
FIG. 3 is a schematic diagram of a reference voltage program adjust circuit;
FIG. 4 is a schematic diagram of a calibration reference signal generating circuit;
FIG. 5 is a schematic diagram of a reference output quantization code generation circuit;
fig. 6 is a schematic diagram of the structure of the control circuit.
Detailed Description
The following describes a gain mismatch error calibration circuit for a multi-channel ADC according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a gain mismatch error calibration circuit for a multi-channel ADC, as shown in FIG. 1. The gain mismatch error calibration circuit for a multi-channel ADC includes: the device comprises a reference voltage generating circuit, a reference voltage remote driving circuit, M reference voltage adjusting circuits, an N-bit analog-to-digital converter of an M channel, M N-bit output registers, a calibration reference signal generating circuit, an N-bit digital subtraction circuit and a control circuit. The M reference voltage adjusting circuits are a reference voltage adjusting circuit 1, a reference voltage adjusting circuit 2, a. And each reference voltage adjusting circuit, each N-bit analog-to-digital converter of each channel and each N-bit output register correspond to each other one by one. Specifically, a reference voltage adjusting circuit 1, an N-bit analog-to-digital converter 1, and an N-bit output register 1 are connected in sequence, a reference voltage adjusting circuit 2, an N-bit analog-to-digital converter 2, and an N-bit output register 2 are connected in sequence, and a reference voltage adjusting circuit M, N, an analog-to-digital converter M, and an N-bit output register M are connected in sequence.
The reference voltage generating circuit generates a reference voltage and inputs the reference voltage to the reference voltage remote driving circuit; the M output reference voltages of the reference voltage remote driving circuit are respectively connected to the reference voltage input ends of the M reference voltage adjusting circuits: the reference voltage Vrin1 is connected with a reference voltage adjusting circuit 1, the reference voltage Vrin2 is connected with a reference voltage adjusting circuit 2, and the reference voltage Vrin M is connected with a reference voltage adjusting circuit M; the M +1 th output reference voltage Vrinref of the reference voltage remote driving circuit is connected to a reference voltage input terminal of the calibration reference signal generating circuit. M control signal Ctrl1~ M of M control signal output of control circuit's output connect M reference voltage adjusting circuit's control signal input end respectively: the control signal Ctrl1 is connected to the control signal input terminal of the reference voltage adjusting circuit 1, the control signal Ctrl2 is connected to the control signal input terminal of the reference voltage adjusting circuit 2. K-bit compensation codes 1-M output by M K-bit compensation code output ends of the control circuit are respectively connected with compensation code input ends of M reference voltage adjusting circuits. The reference voltage output end of each reference voltage adjusting circuit is connected with the corresponding N-bit analog-to-digital converter, and a calibration voltage signal Vr _ cal output by the calibration voltage signal output end of the calibration reference signal generating circuit is transmitted to the N-bit analog-to-digital converter of the M channel; the N-bit digital codes output by the N-bit analog-to-digital converters of all channels pass through corresponding N-bit output registers to obtain quantized codes; m +1 groups of digital code input ends of the N-bit digital subtraction circuit are respectively connected to the M N-bit output registers and a reference output quantization code output end of the calibration reference signal generating circuit. Specifically, the input end of D1 of the N-bit digital subtraction circuit is connected to the output end of the reference output quantization code of the N-bit output register 1, the input end of D1 of the N-bit digital subtraction circuit is connected to the output end D1 of the N-bit output register 1, the input end of D2 of the N-bit digital subtraction circuit is connected to the output end D2 of the N-bit output register 2. The control input end of the calibration reference signal generating circuit is connected to the K bit selection code output port of the control circuit; the K bit quantization code output end of the N bit digital subtraction circuit is connected to the error input end of the control circuit; an output port of a calibration control signal Ctrl _ mode of the control circuit is simultaneously connected to input ports of calibration control signals of the N-bit digital subtraction circuit and the calibration reference signal generating circuit; and the K-bit global adjusting code output end of the control circuit is connected with the input end of the reference voltage remote driving circuit. And N and M are any positive integer, and K is a positive integer not greater than N.
The gain mismatch error calibration circuit for the multi-channel ADC comprises a calibration mode and a compensation mode; when the multi-channel ADC enters a calibration mode, the gain mismatch error calibration circuit for the multi-channel ADC sequentially performs gain mismatch error calibration on N-bit analog-to-digital converters of M channels to sequentially generate M groups of K-bit compensation codes; when entering the compensation mode, the M groups of K-bit compensation codes are kept unchanged, the gain mismatch error calibration circuit for the multi-channel ADC simultaneously performs gain mismatch error compensation on the N-bit digital-to-analog converter of the M channels, and the calibration reference signal generation circuit and the N-bit digital subtraction circuit are turned off to reduce power consumption.
The working principle of the circuit is as follows: when the calibration mode is started, the control circuit firstly controls the N-bit digital subtraction circuit and the calibration reference signal generating circuit to enter the calibration mode through a Ctrl _ mode signal, and simultaneously outputs a K-bit selection code to the calibration reference signal generating circuit; in addition, the control circuit outputs a first calibration control signal Ctrl1 to the reference voltage adjustment circuit 1 to control the reference voltage adjustment circuit 1 to enter the calibration mode, and starts to perform gain mismatch error calibration on the N-bit analog-to-digital converter circuit 1. The control circuit then generates a first set of K bit selection codes; the first group of K bit selection codes enters the calibration reference signal generation circuit and generates a first group of reference output quantization codes Dref (1) and a first calibration reference voltage Vr _ cal (1); the first calibration reference voltage Vr _ cal (1) is used as an analog input signal of the N-bit analog-to-digital converter 1, so that the N-bit analog-to-digital converter 1 performs normal analog-to-digital conversion operation, and first performs gain mismatch error calibration under the 1 st calibration reference voltage.
The control circuit continuously generates a first group of K-bit compensation codes 1cali (1), the first group of K-bit compensation codes enters the reference voltage adjusting circuit 1 and obtains a first channel reference voltage Vr1, the first channel reference voltage Vr1 serves as a reference voltage of the N-bit analog-to-digital converter 1, and a first group of first output quantization codes D1 (1) is obtained through analog-to-digital conversion of the N-bit analog-to-digital converter 1; the N-bit digital subtraction circuit subtracts the first group of first output quantization codes D1 (1) and the first group of reference output quantization codes Dref (1) to obtain a first group of K-bit quantization codes and inputs the first group of K-bit quantization codes into the control circuit; the control circuit stores the received first group of K-bit quantization codes in a K-bit register group inside the control circuit; the control circuit generates a second group of K bit compensation codes 1cali (2) by adopting a binary search method according to the first group of K bit quantization codes;
next, the second group of K-bit compensation codes 1cali (2) enters the reference voltage adjusting circuit 1 and obtains an updated reference voltage Vr1, and a second group of first output quantization codes D1 (2) is obtained through analog-to-digital conversion by the N-bit analog-to-digital converter 1; the N-bit digital subtraction circuit subtracts the updated second group of first output quantization codes D1 (2) from the first group of reference output quantization codes Dref (1) to obtain a second group of K-bit quantization codes, and inputs the second group of K-bit quantization codes into the control circuit; the control circuit generates a third set of K-bit compensation codes 1cali (3) by a binary search method according to the second set of K-bit quantization codes.
And sequentially circulating, the N-bit digital subtraction circuit can continuously generate the L-th group of K-bit quantization codes, and the control circuit can generate the L + 1-th group of K-bit compensation codes 1cali (L +1) by adopting a binary search method. When the control circuit generates the kth K-bit compensation code 1cali (K), the control circuit stores the kth K-bit compensation code 1cali (K) into a new register and selects the K-bit compensation code 1cali (K) R1, ending the calibration of the gain mismatch error under the 1 st calibration reference voltage.
The control circuit then generates a Yth set of K bit selection codes; the Y-th group of K bit selection codes enter the calibration reference signal generating circuit and generate a Y-th group of reference output quantization codes Dref (Y) and a Y-th calibration reference voltage Vr _ cal (Y); a Y calibration reference voltage Vr _ cal (Y) as an analog input signal of the N-bit analog-to-digital converter 1, and performing gain mismatch error calibration under the Y calibration reference voltage; the gain mismatch error calibration circuit for the multichannel ADC obtains a K-bit compensation code 1cali (K) RY in the same way as the gain mismatch error calibration under the calibration reference voltage of the 1 st type, and finishes the gain mismatch error calibration under the calibration reference voltage of the Y type. And sequentially circulating, when the gain mismatch error calibration circuit for the multichannel ADC obtains the last group of K-bit compensation codes 1cali (K) _ RZ and finishes the gain mismatch error calibration under the Z-th calibration reference voltage, the algorithm circuit in the control circuit calculates the obtained Z groups of K-bit compensation codes 1cali (K) _ R1-cali (K) _ RZ to obtain the final K-bit compensation code 1cali _ fin and keeps the final K-bit compensation code 1cali _ fin unchanged, and the gain mismatch error calibration circuit for the multichannel ADC finishes the gain mismatch error calibration of the N-bit analog-to-digital converter circuit 1.
Then, the control circuit outputs an xth calibration control signal Ctrl X to the reference voltage adjustment circuit X to control the reference voltage adjustment circuit X to enter the calibration mode, and starts to perform gain mismatch error calibration of the N-bit analog-to-digital converter circuit X. The gain mismatch error calibration circuit for the multichannel ADC obtains a K-bit compensation code X cali _ fin by adopting the same calibration process as the N-bit analog-to-digital converter circuit 1 and keeps the K-bit compensation code X cali _ fin unchanged, and the gain mismatch error calibration of the N-bit analog-to-digital converter circuit X is finished. According to the same calibration mode, when the control circuit outputs the mth calibration control signal Ctrl M to the reference voltage adjustment circuit M, the K-bit compensation code M cali _ fin is obtained and remains unchanged, and the gain mismatch error calibration of the N-bit analog-to-digital converter circuit M is finished, the calibration mode of the gain mismatch error calibration circuit for the multichannel ADC is finished.
The gain mismatch error calibration circuit for the multichannel ADC starts to enter a compensation mode, the control circuit sets the M reference voltage adjusting circuits to be in the compensation mode at the same time, and the clock reference voltage mismatch error of the N-bit digital-to-analog converter of the M channels starts to be compensated. Finally, the control circuit closes the calibration reference signal generation circuit and the N-bit digital subtraction circuit to reduce power consumption.
In the above description, N and M are both any positive integer, K is a positive integer not greater than N, X is a positive integer not greater than M, L is a positive integer not greater than K, and Z is not greater than 2K-1 and Y is a positive integer not greater than Z.
Fig. 2 is a schematic structural diagram of the reference voltage remote driving circuit. The reference voltage remote driving circuit includes: a reference voltage programming adjustment circuit and M +1 voltage remote driving circuits. The output end of the reference voltage programming adjusting circuit is simultaneously connected with M +1 voltage remote driving circuits. The M +1 voltage remote driving circuits are a voltage remote driving circuit 1, a voltage remote driving circuit 2, a voltage remote driving circuit M and a voltage remote driving circuit ref, respectively. The voltage remote driving circuit 1 generates a reference voltage Vrin1, the voltage remote driving circuit 2 generates a reference voltage Vrin 2. The band-gap reference voltage enters the reference voltage programming adjusting circuit, and the output voltage of the reference voltage programming adjusting circuit is controlled by the K-bit global adjusting code.
Specifically, fig. 3 illustrates an implementation of the reference voltage programming regulator circuit, which is configured as a digital controlled LDO circuit. When the control signal is set to 0, the PMOS transistor M31 is conducted, and the reference voltage is generated by the negative feedback action of the operational amplifierV REFUnder the control of regulating NMOS transistor M30, obtaining an initial voltage output by resistance voltage divisionV R(0) Meanwhile, the current type K-bit DAC also generates a regulation current Ic to the ground, and the regulation current Ic flows through the tail-most resistor R32 to the ground, so that a delta is superposed on the resistor R32VVoltage outputted to the reference signal output circuit corresponding to Ic × R32V Rout＝V R(0)＋⊿V. Outputting a reference voltage signal according to the resistance voltage division relationV RoutChanges will occur accordingly. Therefore, the purpose of changing the output reference voltage can be realized by only controlling the K-bit global adjusting code. In the embodiment of the present invention, all the reference voltage adjusting circuits may adopt the circuit structure shown in fig. 3. For M +1 voltagesThe remote driving circuit can be realized by adopting a voltage follower.
The calibration reference signal generation circuit includes: a programmable calibration voltage generation circuit and a reference output quantization code generation circuit as shown in fig. 4. The reference voltage input end of the programmable calibration voltage generation circuit is connected to the M +1 th output reference voltage Vrinref of the reference voltage remote drive circuit, and the programmable calibration voltage generation circuit outputs the calibration reference voltage Vr _ cal under the control of the K bit selection code; the reference output quantization code generation circuit outputs a reference output quantization code Dref under the control of the K-bit selection code.
Fig. 5 is a schematic structural diagram of a reference output quantization code generation circuit, which operates only in a calibration mode and includes a ROM lookup table, a ROM module, and a reference quantization code output circuit, all controlled by a Ctrl _ mode signal. The K bit selection code enters a ROM lookup table to obtain a corresponding address to be sent to a ROM module, the ROM module outputs reference quantization code data stored in a memory unit corresponding to the corresponding address to a reference quantization code output circuit, and the reference quantization code output circuit outputs a reference output quantization code Dref.
Referring to fig. 6, the control circuit includes: the circuit comprises a core control circuit, a selection code generating circuit, an adjusting code generating circuit, an arithmetic circuit, a K-bit register group, a compensation code output register 1-a compensation code output register M and a channel selection circuit.
The input end of the core control circuit is connected with a calibration starting signal, the first output end of the core control circuit is connected with the control input end of the channel selection circuit, the second output end of the core control circuit is connected with the control input end of the operation circuit, the third output end of the core control circuit is connected with the control input end of the selection code generation circuit, the fourth output end of the core control circuit is connected with the control input end of the adjustment code generation circuit, the fifth output end of the core control circuit is connected with the control input end of the K-bit register group, and M calibration control signals Ctrl 1-Ctrl M generated by the sixth-M +5 th output ends of the core control circuit are respectively connected with the compensation code output register 1-compensation code output register M. Specifically, the calibration control signal Ctrl1 is connected to the compensation code output register 1, the calibration control signal Ctrl2 is connected to the compensation code output register 2,. and the calibration control signal Ctrl M is connected to the compensation code output register M; the data input end of the arithmetic circuit receives the data sent by the output end of the K-bit register group and generates a K-bit error code according to a control instruction of the core control circuit; the data input ends of the compensation code output register 1 to the compensation code output register M are all connected to the K-bit error code output end of the operational circuit, and the output ends of the compensation code output register 1 to the compensation code output register M are respectively connected to the 1 st to M th data input ends of the channel selection circuit; the channel selection circuit outputs a K-bit compensation code 1 and a K-bit compensation code 2 according to a control instruction of the core control circuit. The selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the adjusting code generating circuit generates a K-bit global adjusting code according to a control instruction of the core control circuit; and the data input end of the K-bit register group receives the K-bit quantization code sent by the output end of the N-bit digital subtraction circuit, and sends the data stored in the internal register of the K-bit register group to the arithmetic circuit according to the control instruction of the core control circuit.
In the calibration mode, only one of the calibration control signals Ctrl 1-Ctrl M is valid at any time; in the process of calibrating the N-bit analog-to-digital converter of the M channel, the channel selection circuit opens the output of the compensation code output register corresponding to the N-bit analog-to-digital converter for calibration, and closes the outputs of the other compensation code output registers.
The operation circuit adopts a binary successive approximation algorithm to generate K bit error codes, and only 1 bit in the K bit error codes is changed in each operation; the final output of the K-bit error code which is kept unchanged needs K times of cyclic operation to be determined. Specifically, in the process of calibrating the gain mismatch error under the Y-th calibration reference voltage, the K-bit error code needs to be circularly operated for K times to generate a K-bit compensation code X cali (K) _ RY once; in the process of calibrating the gain mismatch error of the N-bit analog-to-digital converter circuit X, because Z calibration reference voltages need to be calibrated, the K-bit error code needs to be circularly operated for K X Z times to obtain a K-bit compensation code X cali _ fin and keeps unchanged; in the process of calibrating the gain mismatch errors of the N-bit analog-to-digital converter circuits of all M channels, the K-bit error codes need to be cyclically operated K × Z × M times to obtain M groups of K-bit compensation codes X calii _ fin and keep the M groups of K-bit compensation codes X calii _ fin unchanged, so that the calibration mode of the gain mismatch error calibration circuit for the multi-channel ADC is finished.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (8)
1. A gain mismatch error calibration circuit for a multi-channel ADC, comprising: the device comprises a reference voltage generating circuit, a reference voltage remote driving circuit, M reference voltage adjusting circuits, an N-bit analog-to-digital converter of an M channel, M N-bit output registers, a calibration reference signal generating circuit, an N-bit digital subtraction circuit and a control circuit; each reference voltage adjusting circuit, the N-bit analog-to-digital converter of each channel and each N-bit output register correspond to each other one by one;
the reference voltage generating circuit generates a reference voltage and inputs the reference voltage to the reference voltage remote driving circuit; m paths of output reference voltages of the reference voltage remote driving circuit are respectively connected to reference voltage input ends of M reference voltage adjusting circuits, and an M +1 th output reference voltage Vrinref is connected to a reference voltage input end of a calibration reference signal generating circuit; m control signals output by M control signal output ends of the control circuit are respectively connected with control signal input ends of M reference voltage adjusting circuits, and K-bit compensation codes 1-M output by M K-bit compensation code output ends of the control circuit are respectively connected with compensation code input ends of the M reference voltage adjusting circuits; a reference voltage output end of the reference voltage adjusting circuit is connected with a corresponding N-bit analog-to-digital converter, and a calibration voltage signal output end Vr _ cal of the calibration reference signal generating circuit is connected with the N-bit analog-to-digital converter of the M channel; the N-bit digital code output by the N-bit analog-to-digital converter passes through a corresponding N-bit output register to obtain a quantized code; m +1 groups of digital code input ends of the N-bit digital subtraction circuit are respectively connected to the M N-bit output registers and a reference output quantization code output end Dref of the calibration reference signal generating circuit; the control input end of the calibration reference signal generating circuit is connected to the K bit selection code output port of the control circuit; the K bit quantization code output end of the N bit digital subtraction circuit is connected to the error input end of the control circuit; an output port of a calibration control signal Ctrl _ mode of the control circuit is connected to input ports of calibration control signals of the N-bit digital subtraction circuit and the calibration reference signal generating circuit; the K bit global adjusting code output end of the control circuit is connected with the input end of the reference voltage remote driving circuit;
wherein N and M are any positive integer, and K is a positive integer not greater than N.
2. The gain mismatch error calibration circuit for a multi-channel ADC of claim 1, wherein said gain mismatch error calibration circuit for a multi-channel ADC comprises a calibration mode and a compensation mode;
when the multi-channel ADC enters a calibration mode, the gain mismatch error calibration circuit for the multi-channel ADC sequentially performs gain mismatch error calibration on N-bit analog-to-digital converters of M channels to sequentially generate M groups of K-bit compensation codes; when entering the compensation mode, the M groups of K-bit compensation codes are kept unchanged, the gain mismatch error calibration circuit for the multi-channel ADC simultaneously performs gain mismatch error compensation on the N-bit digital-to-analog converter of the M channels, and the calibration reference signal generation circuit and the N-bit digital subtraction circuit are turned off to reduce power consumption.
3. The gain mismatch error calibration circuit for a multi-channel ADC of claim 1, wherein said reference voltage remote drive circuit comprises: a reference voltage programming adjustment circuit and M +1 voltage remote driving circuits; the output end of the reference voltage programming adjusting circuit is simultaneously connected with M +1 voltage remote driving circuits; the output voltage of the reference voltage programming adjustment circuit is controlled by the K-bit global adjustment code.
4. The gain mismatch error calibration circuit for a multi-channel ADC of claim 1, wherein said calibration reference signal generation circuit comprises: a programmable calibration voltage generating circuit and a reference output quantization code generating circuit;
the reference voltage input end of the programmable calibration voltage generation circuit is connected to the M +1 th output reference voltage Vrinref of the reference voltage remote drive circuit, and the programmable calibration voltage generation circuit outputs calibration reference voltage under the control of the K bit selection code; the reference output quantization code generation circuit outputs a reference output quantization code under the control of the K-bit selection code.
5. The gain mismatch error calibration circuit for a multi-channel ADC of claim 4, wherein said reference output quantization code generation circuit operates only in a calibration mode, comprising a ROM lookup table, a ROM module, and a reference quantization code output circuit, all controlled by a Ctrl _ mode signal; the K bit selection code enters a ROM lookup table to obtain a corresponding address to be sent to a ROM module, the ROM module outputs reference quantization code data stored in a memory unit corresponding to the corresponding address to a reference quantization code output circuit, and the reference quantization code output circuit outputs a reference output quantization code.
6. The gain mismatch error calibration circuit for a multi-channel ADC of claim 1, wherein said control circuit comprises: the circuit comprises a core control circuit, a selection code generating circuit, an adjusting code generating circuit, an arithmetic circuit, a K-bit register group, a compensation code output register 1-a compensation code output register M and a channel selection circuit;
the input end of the core control circuit is connected with a calibration starting signal, the first output end of the core control circuit is connected with the control input end of the channel selection circuit, the second output end of the core control circuit is connected with the control input end of the operation circuit, the third output end of the core control circuit is connected with the control input end of the selection code generation circuit, the fourth output end of the core control circuit is connected with the control input end of the adjustment code generation circuit, the fifth output end of the core control circuit is connected with the control input end of the K-bit register group, and M calibration control signals Ctrl 1-Ctrl M generated by the sixth-to-M + 5-th output ends of the core control circuit are respectively connected with the compensation code output register 1-compensation code output register M; the data input end of the arithmetic circuit receives the data sent by the output end of the K-bit register group and generates a K-bit error code according to a control instruction of the core control circuit; the data input ends of the compensation code output register 1 to the compensation code output register M are all connected to the K-bit error code output end of the operational circuit, and the output ends of the compensation code output register 1 to the compensation code output register M are respectively connected to the 1 st to M th data input ends of the channel selection circuit; the channel selection circuit outputs K-bit compensation codes 1-M according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the adjusting code generating circuit generates a K-bit global adjusting code according to a control instruction of the core control circuit; and the data input end of the K-bit register group receives the K-bit quantization code sent by the output end of the N-bit digital subtraction circuit, and sends the data stored in the internal register of the K-bit register group to the arithmetic circuit according to the control instruction of the core control circuit.
7. The gain mismatch error calibration circuit for multi-channel ADC of claim 6, wherein said calibration control signals Ctrl 1-Ctrl M are valid for only one signal at any time in calibration mode; in the process of calibrating the N-bit analog-to-digital converter of the M channel, the channel selection circuit opens the output of the compensation code output register corresponding to the N-bit analog-to-digital converter for calibration, and closes the outputs of the other compensation code output registers.
8. The gain mismatch error calibration circuit for a multi-channel ADC of claim 6, wherein said arithmetic circuit uses a binary successive approximation algorithm to generate K-bit error codes, only 1 bit of the K-bit error codes being changed for each operation; the final output of the K-bit error code which is kept unchanged needs K times of cyclic operation to be determined.
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| CN112532242A (en) * | 2020-12-18 | 2021-03-19 | 中国电子科技集团公司第四十七研究所 | Dynamic calibration method and device for ADC reference voltage |
| CN113098513A (en) * | 2021-03-31 | 2021-07-09 | 中国科学院半导体研究所 | Multichannel ADC trimming calibration system and method |
| CN114296017A (en) * | 2021-11-26 | 2022-04-08 | 上海东软医疗科技有限公司 | Magnetic resonance receiving apparatus, magnetic resonance signal processing method, and magnetic resonance device |
| CN114153786B (en) * | 2021-11-26 | 2023-08-04 | 山东云海国创云计算装备产业创新中心有限公司 | Server and SOC (system on chip) system thereof |
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