CN108809306B

CN108809306B - Multi-channel high-precision ADC circuit with mismatch error self-calibration function

Info

Publication number: CN108809306B
Application number: CN201810585152.0A
Authority: CN
Inventors: 陈珍海; 魏敬和; 何宁业; 薛颜; 于宗光; 桂江华; 周昱
Original assignee: CETC 58 Research Institute
Current assignee: CETC 58 Research Institute
Priority date: 2018-06-08
Filing date: 2018-06-08
Publication date: 2021-08-31
Anticipated expiration: 2038-06-08
Also published as: CN108809306A

Abstract

The invention provides a multi-channel high-precision ADC circuit with a mismatch error self-calibration function, and belongs to the technical field of integrated circuits. The multi-channel high-precision ADC circuit with the mismatch error self-calibration function comprises a gain error compensation circuit, a clock phase error compensation circuit, an M-channel N-bit analog-to-digital converter, a gain error quantization circuit, a clock phase error quantization circuit and a control circuit. The multichannel high-precision ADC circuit with the mismatch error self-calibration function can automatically compromise and select the calibration precision according to the system precision and the hardware overhead, and has the characteristic of low power consumption.

Description

Multi-channel high-precision ADC circuit with mismatch error self-calibration function

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a multi-channel high-precision ADC circuit with a mismatch error self-calibration function.

Background

A pipeline ADC (analog-to-digital converter) with 14-bit precision and sampling rate of more than 100MSPS is always the main choice of various intermediate frequency sampling systems, and is therefore widely applied to electronic application systems such as multi-carrier broadband wireless communication and radar reception. In order to reduce cost and improve reliability, various electronic systems have increasingly high demands for low power consumption and miniaturization, and the requirements for power consumption and area of ADC circuits used in the electronic systems are increasingly strict. In order to improve the integration level of the pipeline ADC, a single chip integrated multi-channel ADC circuit is usually used to reduce the space occupied by the board-level system design. In order to realize multi-channel integration of the pipeline ADC circuit, the core circuit of the single-channel pipeline ADC used in the circuit has some special requirements: firstly, the ADC kernel must have the characteristics of low power consumption and small area, otherwise, the power consumption and reliability problems caused by multi-channel integration can greatly limit the application of a board-level system; secondly, the ADC core must use as few output ports as possible, otherwise, the packaging problem caused by integration and the wiring problem of the high-speed signal line of the board-level system both cause great limitations.

In addition, when the multi-channel ADCs are integrated on the same chip, the mismatch of device parameters between different chip areas causes the mismatch error of synchronous clock and gain between the multi-channel ADCs. Particularly for high-speed and high-precision ADCs, the influence caused by mismatch of clock and gain errors among ADCs of different channels is very obvious, and the mismatch error has larger influence on system performances such as radar, multi-channel wireless communication and the like. Therefore, it is very practical to design a circuit capable of self-calibrating various mismatch errors among the multi-channel ADCs.

Disclosure of Invention

The invention aims to provide a multi-channel high-precision ADC circuit with a mismatch error self-calibration function, so as to solve the problem of mismatch of clock and gain errors generated by the conventional high-precision ADC.

In order to solve the technical problem, the invention provides a multi-channel high-precision ADC circuit with a mismatch error self-calibration function, which comprises a gain error compensation circuit, a clock phase error compensation circuit, an N-bit analog-to-digital converter of an M channel, a gain error quantization circuit, a clock phase error quantization circuit and a control circuit, wherein the gain error compensation circuit is connected with the clock phase error quantization circuit; the N-bit analog-to-digital converter of the M channel comprises an N-bit analog-to-digital converter 1, an N-bit analog-to-digital converter 2, an N-bit analog-to-digital converter M;

wherein, M reference voltage output ports Vrc1, Vrc2, the right-going, Vrc M of the gain error compensation circuit are respectively connected to the reference voltage input ports of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2, the right-going, and the N-bit analog-to-digital converter M, and the M +1 reference voltage output port Vrinref of the gain error compensation circuit is connected to the reference voltage input port of the gain error quantization circuit; the M clock output ports CKc1, CKc2,. and CKc M of the clock phase error compensation circuit are respectively connected to the clock input ports of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2,. and the N-bit analog-to-digital converter M;

digital quantization code output ends D1, D2, and D D M of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2, the right-to-say and the N-bit analog-to-digital converter M are respectively connected with M digital quantization code input ends of the gain error quantization circuit, a calibration reference signal Vr _ cal of the gain error quantization circuit is output to analog signal input ends of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2, the right-to-say and the N-bit analog-to-digital converter M, and a K-bit quantization code _ G of the gain error quantization circuit is output to a K-bit quantization code _ G input end of the;

the M +1 error clock output ports CKout1, CKout2,. the.. the CKout M and CKinref of the clock phase error compensation circuit are connected with the M +1 clock input ports of the clock phase error quantization circuit, and the K bit quantization code _ CK of the clock phase error quantization circuit is output to the K bit quantization code _ CK input end of the control circuit;

the M K-bit delay code output ends of the control circuit are respectively connected with the M K-bit delay code input ends of the clock phase error compensation circuit, the M CK _ Ctrl control signal output ends of the control circuit are respectively connected with the M CK _ Ctrl control signal input ends of the clock phase error compensation circuit, the K-bit selection code _ CK output end and the Ctrl _ mode _ CK output end of the control circuit are respectively connected with the K-bit selection code _ CK input end and the Ctrl _ mode _ CK input end of the clock phase error quantization circuit, the M K-bit compensation code output ends of the control circuit are respectively connected with the M K-bit compensation code input ends of the gain error compensation circuit, the M G-Ctrl control signal output ends of the control circuit are respectively connected with the M G-Ctrl control signal input ends of the gain error compensation circuit, and the K-bit global adjustment code output end of the control circuit is connected with the K-bit global adjustment code input end of the gain error compensation circuit, the K bit selection code _ G output end and the Ctrl _ mode _ G output end of the control circuit are respectively connected with the K bit selection code _ G input end and the Ctrl _ mode _ G input end of the gain error quantization circuit;

wherein N, M and K are both any positive integer.

Optionally, the multi-channel high-precision ADC circuit with the mismatch error self-calibration function includes a calibration mode and a compensation mode, and the compensation mode can be entered only after the calibration mode is finished;

when entering a calibration mode, the multichannel high-precision ADC circuit with mismatch error calibration firstly sequentially performs phase mismatch error calibration on N-bit analog-to-digital converters of M channels to generate M groups of K-bit delay codes; after phase mismatch error calibration is finished, the multichannel high-precision ADC circuit with mismatch error calibration sequentially carries out gain mismatch error calibration on N-bit analog-to-digital converters of M channels to generate M groups of K-bit compensation codes;

when the multi-channel high-precision analog-to-digital converter enters a compensation mode, M groups of K-bit delay codes and M groups of K-bit compensation codes are kept unchanged, the multi-channel high-precision ADC circuit with mismatch error calibration simultaneously carries out phase and gain mismatch error compensation on the N-bit digital-to-analog converter of the M channels, and the gain error quantization circuit and the clock phase error quantization circuit are both closed to reduce power consumption.

Optionally, the clock phase error compensation circuit includes: the clock receiving circuit, the clock duty ratio stabilizing circuit, the clock driving circuit, the M delay circuits, the M multiphase clock generating circuits and the M clock equivalent delay circuits are in one-to-one correspondence;

the clock receiving circuit, the clock duty ratio stabilizing circuit and the clock driving circuit are sequentially connected, and an input clock enters the input end of the clock driving circuit after passing through the clock receiving circuit and the clock receiving circuit; the M output clocks CKin1, CKin 2.. times and CKin M of the clock driving circuit are respectively output to the input ends of the M delay circuits, and the M +1 th output clock CKinref of the clock driving circuit is output to the clock phase error quantization circuit; the control signal input ends of the M delay circuits are respectively connected with M CK _ Ctrl control signal output ends of the control circuit, the delay code input ends of the delay circuits are respectively connected with M K-bit delay code output ends of the control circuit, and the clock output ends of the delay circuits are simultaneously connected with the clock input ends of the multiphase clock generation circuit and the clock equivalent delay circuit corresponding to the delay circuits; the multiphase output clocks CKc1, CKc2,. and CKc M of each multiphase clock generation circuit respectively enter the N-bit analog-to-digital converter of the M channels; the clock output terminals CKout1, CKout2,. and CKout M of each clock equivalent delay circuit are respectively connected to the M clock input terminals of the clock phase error quantization circuit.

Optionally, the clock equivalent delay circuit includes: the device comprises a multi-phase clock circuit equivalent delay unit, a sample-and-hold circuit equivalent delay unit, a multi-stage sub-stage circuit equivalent delay unit and a digital calibration circuit equivalent delay unit; the multi-stage sub-stage circuit equivalent delay unit comprises a 1 st stage sub-stage circuit equivalent delay unit, a 2 nd stage sub-stage circuit equivalent delay unit, an R < th > stage sub-stage circuit equivalent delay unit;

the multiphase clock circuit equivalent delay unit, the sample and hold circuit equivalent delay unit, the 1 st-stage sub-stage circuit equivalent delay unit, the 2 nd-stage sub-stage circuit equivalent delay unit, the R-stage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit are sequentially connected; the clock output end of the delay circuit is connected to the clock input end of the corresponding multi-phase clock circuit equivalent delay unit, and a clock is output after sequentially passing through the multi-phase clock circuit equivalent delay unit, the sample and hold circuit equivalent delay unit, the 1 st-stage sub-stage circuit equivalent delay unit, the 2 nd-stage sub-stage circuit equivalent delay unit, the 1 st-stage sub-stage circuit equivalent delay unit, the R-stage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit;

when the clock equivalent delay circuit enters a calibration mode, the multi-phase clock circuit equivalent delay unit, the sample-and-hold circuit equivalent delay unit, the multi-stage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit work normally; when the clock equivalent delay circuit enters a compensation mode, the multiphase clock circuit equivalent delay unit, the sample-and-hold circuit equivalent delay unit, the multistage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit are closed;

wherein R is a positive integer.

Optionally, the clock phase error quantization circuit includes: the circuit comprises a reference clock generating circuit, a phase discriminator, a loop filter and a K-bit analog-to-digital converter circuit;

the M +1 clock input ends of the phase detector are respectively connected to the M clock output ends CKout1, CKout2, CKout M and the clock output end CKref of the reference clock generating circuit; the control input end of the reference clock generating circuit is connected with the K bit selection code _ CK output end of the control circuit; the phase error signal output end Vp of the phase discriminator is connected to the input end of the loop filter; the output voltage Vi of the loop filter is input to the voltage input end of the K-bit analog-to-digital converter; the K bit quantization code _ CK generated by the K bit analog-to-digital converter is output to a K bit quantization code _ CK input port of the control circuit; an output port of a calibration control signal Ctrl _ mode _ CK of the control circuit is simultaneously connected to input ports of calibration control signals of the phase detector, the loop filter, and the K-bit analog-to-digital converter.

Optionally, the gain error compensation circuit includes: the device comprises a reference voltage generating circuit, a reference voltage remote driving circuit and M reference voltage adjusting circuits;

wherein the reference voltage generation circuit outputs a reference voltage to the reference voltage remote driving circuit; m reference voltage output ends of the reference voltage remote driving circuit are respectively connected with reference voltage input ends of M reference voltage adjusting circuits, and an M +1 th reference voltage output port Vrinref is connected with a reference voltage input end of the gain error quantization circuit; the control signal input end of each reference voltage adjusting circuit is respectively connected with M G _ Ctrl control signal output ends of the control circuit, the compensation code input end of each reference voltage adjusting circuit is respectively connected with M K-bit compensation code output ends of the control circuit, and the reference voltage output ends Vrc1, Vrc2, Vrc M of each reference voltage adjusting circuit are respectively output to an N-bit analog-to-digital converter of an M channel.

Optionally, the gain error quantization circuit includes a calibration reference signal generation circuit and an N-bit digital subtraction circuit; digital quantization code output ends D1, D2,. and D M of the N-bit analog-to-digital converter of the M channels are respectively connected with M groups of digital code input ends of the N-bit digital subtraction circuit, and the M +1 group of digital code input ends of the N-bit digital subtraction circuit are connected with an output quantization code output end Dref of the calibration reference signal generating circuit; the control input end of the calibration reference signal generating circuit is connected to the K bit selection code _ G output port of the control circuit; the K bit quantization code _ G output end of the N bit digital subtraction circuit is connected to the K bit quantization code _ G input port of the control circuit; and an output port of a calibration control signal Ctrl _ mode _ G of the control circuit is connected with the input ports of the N-bit digital subtraction circuit and the calibration control signal of the calibration reference signal generating circuit.

Optionally, the control circuit includes: the circuit comprises a core control circuit, a selection code generating circuit, an adjusting code generating circuit, an arithmetic circuit, a K-bit register group _ G, K-bit register group _ CK, a compensation code output register 1-a compensation code output register M, a delay code output register 1-a delay code output register M and a channel selection circuit;

the input end of the core control circuit is connected with a calibration start signal, the first output end of the core control circuit is connected to the control input end of the channel selection circuit, the second output end of the core control circuit is connected to the control input end of the arithmetic circuit, the third output end of the core control circuit is connected to the control input end of the selection code generation circuit, the fourth output end of the core control circuit is connected to the control input end of the adjustment code generation circuit, the fifth output end of the core control circuit is connected to the control input end of the K-bit register group _ CK, the sixth output end of the core control circuit is connected to the control input end of the K-bit register group _ G, M calibration control signals G _ Ctrl 1-G _ Ctrl M are generated at the seventh output end to the M +6 output end, and M calibration control signals CK _ Ctrl 1-CK _ Ctrl M are generated at the M +7 output end to the (2M + 6) output end; the data input end of the arithmetic circuit receives the data sent by the K-bit register group _ CK output end and the K-bit register group _ G output end, and generates a K-bit error code according to a control instruction of the core control circuit, the K-bit error code is simultaneously transmitted to the data input ends of the compensation code output register 1-compensation code output register M and the delay code output register 1-delay code output register M, the control signal input ends of the compensation code output register 1-compensation code output register M are respectively connected with M calibration control signals G _ Ctrl 1-G _ Ctrl M, the control signal input ends of the delay code output register 1-delay code output register M are respectively connected with M calibration control signals CK _ Ct 1-CK _ Ctrl M, the output ends of the compensation code output register 1-compensation code output register M are respectively connected with the 1 st to M data input ends of the channel selection circuit, the output ends of the delay code output register 1 to the delay code output register M are respectively connected with the M +1 th to 2M data input ends of the channel selection circuit; the channel selection circuit outputs a K-bit compensation code or a K-bit delay code according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the adjusting code generating circuit generates a K-bit global adjusting code according to a control instruction of the core control circuit; the data input end of the K-bit register group _ CK receives the K-bit quantization code _ CK sent by the clock phase error quantization circuit, and sends data stored in an internal register of the K-bit register group _ CK to the arithmetic circuit according to a control instruction of the core control circuit; and the data input end of the K-bit register group _ G receives the K-bit quantization code _ G sent by the gain error quantization circuit and sends the data stored in the internal register of the gain error quantization circuit to the arithmetic circuit according to the control instruction of the core control circuit.

Optionally, when the gain mismatch error calibration is performed on the N-bit analog-to-digital converter of the M channel, the channel selection circuit opens the output of the compensation code output register corresponding to the N-bit analog-to-digital converter performing the gain mismatch error calibration, and closes the outputs of the other compensation code output registers; when the N-bit analog-to-digital converter of the M channel is subjected to clock phase mismatch error calibration, the channel selection circuit opens the output of the delay code output register corresponding to the N-bit analog-to-digital converter which is subjected to clock phase mismatch error calibration, and closes the outputs of the other delay code output registers.

Optionally, when the operation circuit generates the K-bit error code by using a binary successive approximation algorithm, only 1 bit of the K-bit error code is changed in each operation.

The invention provides a multi-channel high-precision ADC circuit with a mismatch error self-calibration function, which comprises a gain error compensation circuit, a clock phase error compensation circuit, an M-channel N-bit analog-to-digital converter, a gain error quantization circuit, a clock phase error quantization circuit and a control circuit. The multichannel high-precision ADC circuit with the mismatch error self-calibration function can automatically compromise and select the calibration precision according to the system precision and the hardware overhead, and has the characteristic of low power consumption.

Drawings

FIG. 1 is a schematic diagram of a multi-channel high-precision ADC circuit with mismatch error self-calibration function;

FIG. 2 is a schematic diagram of a clock phase error compensation circuit;

FIG. 3 is a schematic diagram of a clock phase error quantization circuit;

FIG. 4 is a schematic diagram of a clock driving circuit;

FIG. 5 is a schematic diagram of a multiphase clock generation circuit;

FIG. 6 is a schematic diagram of a delay circuit;

FIG. 7 is a schematic diagram of a clock equivalent delay circuit;

FIG. 8 is a schematic diagram of a reference clock generating circuit;

FIG. 9 is a schematic diagram of a gain error compensation circuit;

FIG. 10 is a schematic diagram of a gain error quantization circuit;

FIG. 11 is a schematic diagram of a reference voltage remote driving circuit;

FIG. 12 is a schematic diagram of a reference voltage program adjust circuit;

FIG. 13 is a schematic diagram of a calibration reference signal generating circuit;

fig. 14 is a schematic diagram of a reference output quantization code generation circuit;

fig. 15 is a schematic configuration diagram of the control circuit.

Detailed Description

The following describes a multi-channel high-precision ADC circuit with mismatch error self-calibration function according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a multi-channel high-precision ADC circuit with a mismatch error self-calibration function, which is shown in figure 1. The multi-channel high-precision ADC circuit with the mismatch error self-calibration function comprises a gain error compensation circuit, a clock phase error compensation circuit, an M-channel N-bit analog-to-digital converter, a gain error quantization circuit, a clock phase error quantization circuit and a control circuit. The N-bit analog-to-digital converter of the M channel includes an N-bit analog-to-digital converter 1, an N-bit analog-to-digital converter 2, an N-bit analog-to-digital converter M.

Wherein, M reference voltage output ports Vrc1, Vrc2,. and Vrc M of the gain error compensation circuit are respectively connected to the reference voltage input ports of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2,. and the N-bit analog-to-digital converter M; in addition, an M +1 th reference voltage output port Vrinref of the gain error compensation circuit is connected to a reference voltage input port of the gain error quantization circuit; the M clock output ports CKc1, CKc2,. and CKc M of the clock phase error compensation circuit are connected to the clock input ports of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2,. and the N-bit analog-to-digital converter M, respectively. Digital quantization code output ends D1, D2, a.once and D M of the N-bit analog-to-

digital converters

1, 2, a.once and M-bit analog-to-digital converters M are respectively connected with M digital quantization code input ends D1, D2, a.once and D M of the gain error quantization circuit, a calibration reference signal Vr _ cal of the gain error quantization circuit is output to analog signal input ends of the N-bit analog-to-

digital converters

1, 2, a.once and M-bit analog-to-digital converters M, and a K-bit quantization code _ G of the gain error quantization circuit is output to a K-bit quantization code _ G input end of the control circuit. M +1 error clock output ports CKout1, CKout2,. once, CKout M and CKinref of the clock phase error compensation circuit are connected to M +1 clock input ports of the clock phase error quantization circuit, and a K-bit quantization code _ CK of the clock phase error quantization circuit is output to a K-bit quantization code _ CK input terminal of the control circuit. M K-bit delay code output ends K-bit delay codes 1-M of the control circuit are respectively connected to M K-bit delay code input ends K-bit delay codes 1-M of the clock phase error compensation circuit, M CK _ Ctrl control signal output ends CK _ Ctrl 1-M of the control circuit are respectively connected to M CK _ Ctrl control signal input ends CK _ Ctrl 1-M of the clock phase error compensation circuit, K-bit selection code _ CK output ends and Ctrl _ mode _ CK output ends of the control circuit are respectively connected to K-bit selection code _ CK input ends and Ctrl _ mode _ CK input ends of the clock phase error quantization circuit, M K-bit compensation code output ends K-bit compensation codes 1-M of the control circuit are respectively connected to M K-bit compensation code input ends K-bit compensation codes 1-M of the gain error compensation circuit, and M G _ Ctrl control signal output ends G _ Ctrl 1-M of the control circuit are respectively connected to the gain error compensation circuit M G _ Ctrl control signal input ends G _ Ctrl 1-M of the circuit, a K-bit global adjustment code output end of the control circuit is connected to a K-bit global adjustment code input end of the gain error compensation circuit, and a K-bit selection code _ G output end and a Ctrl _ mode _ G output end of the control circuit are respectively connected to a K-bit selection code _ G input end and a Ctrl _ mode _ G input end of the gain error quantization circuit. Wherein N, M and K are both any positive integer.

Specifically, the multichannel high-precision ADC circuit with the mismatch error self-calibration function comprises two working modes, namely a calibration mode and a compensation mode, and the compensation mode can be entered only after the calibration mode is finished. When entering a calibration mode, the multichannel high-precision ADC circuit with mismatch error calibration firstly sequentially performs phase mismatch error calibration on N-bit analog-to-digital converters of M channels to generate M groups of K-bit delay codes; after phase mismatch error calibration is finished, the multichannel high-precision ADC circuit with mismatch error calibration sequentially carries out gain mismatch error calibration on N-bit analog-to-digital converters of M channels to generate M groups of K-bit compensation codes; when the multi-channel high-precision analog-to-digital converter enters a compensation mode, M groups of K-bit delay codes and M groups of K-bit compensation codes are kept unchanged, the multi-channel high-precision ADC circuit with mismatch error calibration simultaneously carries out phase and gain mismatch error compensation on the N-bit digital-to-analog converter of the M channels, and the gain error quantization circuit and the clock phase error quantization circuit are both closed to reduce power consumption.

The working principle of the multi-channel high-precision ADC circuit with the mismatch error self-calibration function is as follows: when the calibration mode is started, the control circuit firstly controls the clock phase error quantization circuit to enter the calibration mode through a Ctrl _ mode _ CK signal, and simultaneously outputs a K-bit selection code _ CK to the clock phase error quantization circuit; the multichannel high-precision ADC circuit with mismatch error calibration starts to calibrate the phase mismatch error of the N-bit analog-to-digital converter of the M channels; the control circuit then outputs the first calibration control signal CK _ Ctrl1 to the clock phase error compensation circuit, and starts the phase mismatch error calibration of the N-bit adc circuit 1.

Specifically, fig. 2 is a schematic diagram of a clock phase error compensation circuit. The clock phase error compensation circuit includes: the clock receiving circuit, the clock duty cycle stabilizing circuit, the clock driving circuit, M delay circuits, M multiphase clock generating circuits and M clock equivalent delay circuits, wherein each delay circuit, each multiphase clock generating circuit and each clock equivalent delay circuit correspond to one another: the delay circuit 1, the multiphase clock generation circuit 1 correspond to the clock equivalent delay circuit 1, the delay circuit 2, the multiphase clock generation circuit 2 correspond to the clock equivalent delay circuit 2. The clock receiving circuit, the clock duty ratio stabilizing circuit and the clock driving circuit are sequentially connected, and an input clock enters the input end of the clock driving circuit after passing through the clock receiving circuit and the clock receiving circuit; the M output clocks CKin1, CKin2,. and CKin M of the clock driving circuit are respectively connected to the input ends of the M delay circuits: the output clock CKin1 is connected to the input of the delay circuit 1, the output clock CKin2 is connected to the input of the delay circuit 2. The M +1 th output clock CKinref of the clock driving circuit is output to the clock phase error quantization circuit. The control signal input end of each delay circuit is respectively connected with the control signal CK _ Ctrl 1-M output by the control signal output end of the control circuit: the control signal input terminal of the delay circuit 1 is connected to the control signal CK _ Ctrl1, the control signal input terminal of the delay circuit 2 is connected to the control signal CK _ Ctrl 2. The delay code input end of each delay circuit is respectively connected with K-bit delay codes 1-M output by the delay code output end of the control circuit: the delay code input end of the delay circuit 1 is connected with the K-bit delay code 1, the delay code input end of the delay circuit 2 is connected with the K-bit delay code 2. The clock output end of each delay circuit is simultaneously connected to the clock input ends of the multi-phase clock generation circuit and the clock equivalent delay circuit corresponding to the delay circuits: the clock output end of the delay circuit 1 is connected to the multiphase clock generation circuit 1 and the clock equivalent delay circuit 1 at the same time, the clock output end of the delay circuit 2 is connected to the multiphase clock generation circuit 2 and the clock equivalent delay circuit 2 at the same time, and the clock output end of the delay circuit M is connected to the multiphase clock generation circuit M and the clock equivalent delay circuit M at the same time. The multiphase output clocks CKc1, CKc2,. and CKc M of each multiphase clock generation circuit respectively enter the N-bit analog-to-digital converter of M channels: multiphase output clock CKc1 enters N-bit adc 1 and multiphase output clock CKc2 enters N-bit adc 2. The clock output terminals CKout1, CKout2,. and CKout M of each clock equivalent delay circuit are respectively connected to the M clock input terminals of the clock phase error quantization circuit.

Fig. 3 is a schematic structural diagram of the clock phase error quantization circuit. The clock phase error quantization circuit includes: the circuit comprises a reference clock generating circuit, a phase discriminator, a loop filter and a K-bit analog-to-digital converter circuit. Wherein M +1 clock input terminals of the phase detector are respectively connected to the M clock output ports CKout1, CKout2,. and CKout M and the clock output terminal CKref of the reference clock generating circuit; the control input end of the reference clock generating circuit is connected to the K bit selection code _ CK output end of the control circuit; the phase error signal output end Vp of the phase discriminator is connected to the input end of the loop filter; the output voltage Vi of the loop filter is input to the voltage input end of the K-bit analog-to-digital converter; the K bit quantization code _ CK of the K bit analog-to-digital converter is output to a K bit quantization code _ CK input port of the control circuit; an output port of a calibration control signal Ctrl _ mode _ CK of the control circuit is simultaneously connected to input ports of calibration control signals of the phase detector, the loop filter, and the K-bit analog-to-digital converter.

Fig. 4 is an implementation of a clock driving circuit. The clock driving circuit comprises a multi-channel clock generating and pre-driving circuit and M +1 clock remote driving circuits, wherein the M +1 clock remote driving circuits are respectively as follows: a clock remote drive circuit 1, a clock remote drive circuit 2, a clock remote drive circuit M and a clock remote drive circuit ref. The clock duty ratio stabilizing circuit outputs a clock to be input into the multi-channel clock generating and pre-driving circuit, generates M +1 paths of clocks and obtains M +1 paths of output clocks through M +1 clock remote driving circuits. Wherein, M clocks CKin1, CKin 2.,. CKin M are respectively connected to M delay circuits: clock CKin1 is connected to an input of delay circuit 1, clock CKin2 is connected to an input of delay circuit 2. The (M +1) th clock CKinref is output to the reference clock generation circuit. The multi-channel clock generation and pre-driving circuit can be realized by coupling an RS trigger and an inverter. The clock remote driving circuit is realized by adopting an inverter driving chain.

The clock phase calibration circuit for the multi-channel ADC can be used for an M-channel synchronous sampling ADC and can also be used for an M-channel time-interleaved ADC. When the multi-channel clock generating and pre-driving circuit is used for the M-channel synchronous sampling ADC, M +1 paths of clocks generated by the multi-channel clock generating and pre-driving circuit are clock signals with the same phase. When the multi-channel clock generating and pre-driving circuit is used for an M-channel time-interleaved ADC, M paths of clocks CKin 1-CKin M generated by the multi-channel clock generating and pre-driving circuit are clock signals with equal interval phase difference, and the phase difference is 360 degrees/M; the M +1 th clock CKinref is the same as one of the M clocks CKin 1-CKin M, and when the clock phase calibration circuit for the multi-channel ADC is used for phase mismatch error calibration of the N-bit analog-to-digital converter circuit X, the phases of CKinref and CKinX are the same.

For a pipelined ADC, a sub-stage circuit needs a two-phase clock to control the operating state of the circuit in order to complete sampling and holding of an analog input signal. FIG. 5 is a block diagram of an implementation of the multiphase clock generation circuit of the present invention. Wherein CKin is a reference clock signal input externally, and phi 1 and phi 2 are two-phase non-overlapping signals output by the circuit. Meanwhile, in the pipeline module, in order to eliminate the nonlinear effects such as the channel charge injection effect and the clock feedthrough effect of the switching tube, an auxiliary clock signal is required to be added, and Φ 1 'and Φ 2' are auxiliary clock signals designed to eliminate the nonlinearity. The clock circuit is generated by an RS trigger, and the non-overlapping interval time is controlled by the delay of two inverters. The auxiliary clock circuit is generated under the action of the AND circuit after the non-overlapping clock signal is delayed with the signal and the two inverters, the rising edges of the two clock signals can be aligned through the AND circuit, and the delay time of the auxiliary clock and the non-overlapping clock signal is determined by the delay size of the inverters. When two are introduced, the two auxiliary clocks Φ 1 'and Φ 2' are turned off before the respective corresponding original clock signals Φ 1 and Φ 2 are turned off, respectively. The multiphase clock generation circuit shown in fig. 5 can be used to generate a simple two-phase non-overlapping clock, and a 4-phase non-overlapping clock can also be generated by expanding the flip-flops and the feedback loop. However, to generate a clock with more phase complexity, a higher stability clock signal with higher phase complexity is generated by a Delay Locked Loop (DLL).

Fig. 6 is a schematic diagram of a delay circuit structure. The delay circuit comprises a delay unit selection decoding circuit and a delay unit selection decoding circuit 2^K-1 digitally controlled delay elements. 2^KThe-1 numerical control delay unit is a numerical control delay unit 1, a numerical control delay unit 2, a^K-1. The K bit delay code input by the control circuit enters the delay unit selection decoding circuit to generate 2^K-1 time-delayed switch control signal: s1, S2., S2^K-1，2^K-1 delay switch control signals respectively controlling 2^K-1 delay time of the digitally controlled delay cells;CKin is connected to a clock input end of the numerical control delay unit 1, a clock output end of the numerical control delay unit 1 is connected to a clock input end of the numerical control delay unit 2, and the numerical control delay unit 2^KThe clock output of-1 is CK. 2 is described^K-1 delay division of digitally controlled delay elements 2^KBesides the control of the-1 time delay switch control signal, the calibration control signal CK _ Ctrl is also used for controlling the time delay switch. When the delay circuit enters a calibration mode, 2^K-1 delay slave of digitally controlled delay unit 2^K-1 time delay switch control signal control; when the delay circuit enters the compensation mode, 2^K-1 time delay of the numerical control time delay unit is kept unchanged and is not influenced by 2^K-1 time delay switch control signal control.

Specifically, fig. 7 is a schematic structural diagram of the clock equivalent delay circuit. The clock equivalent delay circuit includes: the device comprises a multi-phase clock circuit equivalent delay unit, a sample-and-hold circuit equivalent delay unit, a multi-stage sub-stage circuit equivalent delay unit and a digital calibration circuit equivalent delay unit; the multi-stage sub-stage circuit equivalent delay unit comprises a 1 st stage sub-stage circuit equivalent delay unit, a 2 nd stage sub-stage circuit equivalent delay unit, an R < th > stage sub-stage circuit equivalent delay unit. The multiphase clock circuit equivalent delay unit, the sample and hold circuit equivalent delay unit, the 1 st-stage sub-stage circuit equivalent delay unit, the 2 nd-stage sub-stage circuit equivalent delay unit, the R-stage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit are sequentially connected; the clock output end of the delay circuit is connected to the clock input end of the corresponding multi-phase clock circuit equivalent delay unit, and the clock is output after sequentially passing through the multi-phase clock circuit equivalent delay unit, the sample and hold circuit equivalent delay unit, the 1 st-stage sub-stage circuit equivalent delay unit, the 2 nd-stage sub-stage circuit equivalent delay unit, the R-stage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit. When the clock equivalent delay circuit enters a calibration mode, the multi-phase clock circuit equivalent delay unit, the sample-and-hold circuit equivalent delay unit, the multi-stage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit work normally; when the clock equivalent delay circuit enters a compensation mode, the multiphase clock circuit equivalent delay unit, the sample-and-hold circuit equivalent delay unit, the multistage sub-stage circuit equivalent delay unit and the digital calibration circuit equivalent delay unit are closed; wherein R is a positive integer.

Fig. 8 is a block diagram of the reference clock generating circuit. The reference clock generating circuit includes: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit. The programmable frequency adjusting circuit and the programmable duty ratio adjusting circuit are both controlled by a K-bit selection code _ CK. Under the control of the K-bit selection code _ CK, the input clock with fixed frequency and fixed duty ratio passes through the programmable frequency adjusting circuit and the programmable duty ratio adjusting circuit in sequence, and then the reference clock Ckrref with different frequency and duty ratio can be obtained.

The structure of the gain error compensation circuit is shown in fig. 9. The gain error compensation circuit includes: the circuit comprises a reference voltage generating circuit, a reference voltage remote driving circuit and M reference voltage adjusting circuits. The M reference voltage adjusting circuits are a reference voltage adjusting circuit 1, a reference voltage adjusting circuit 2, and a reference voltage adjusting circuit M, respectively. Wherein, the reference voltage generating circuit generates a reference voltage to be transmitted to the reference voltage remote driving circuit; under the control of a K-bit global regulation code, M reference voltage output ends of the reference voltage remote driving circuit output M reference voltages Vrin1, Vrin2,. and Vrin M to reference voltage input ends of M reference voltage regulation circuits respectively: the reference voltage Vrin1 is supplied to the reference voltage regulator circuit 1, the reference voltage Vrin2 is supplied to the reference voltage regulator circuit 2. The M +1 th reference voltage output port Vrinref outputs a reference voltage to a reference voltage input terminal of the gain error quantization circuit. The control signal input end of each reference voltage adjusting circuit is respectively connected with the control signal G _ Ctrl 1-M output by the control signal output end of the control circuit: a control signal input end of the reference voltage adjusting circuit 1 is connected to a control signal G _ Ctrl1, a control signal input end of the reference voltage adjusting circuit 2 is connected to a control signal G _ Ctrl2, a. The compensation code input end of each reference voltage adjusting circuit is respectively connected to K-bit compensation codes 1-M output by the compensation code output end of the control circuit: the compensation code input end of the reference voltage adjusting circuit 1 inputs a K-bit compensation code 1, the compensation code input end of the reference voltage adjusting circuit 2 inputs a K-bit compensation code 2. The reference voltage output terminals Vrc1, Vrc2, · and Vrc M of the reference voltage adjusting circuits are respectively output to the N-bit analog-to-digital converters of the M channels: a reference voltage output terminal Vrc1 of the reference voltage adjusting circuit 1 is connected to the N-bit analog-to-digital converter 1, a reference voltage output terminal Vrc2 of the reference voltage adjusting circuit 2 is connected to the N-bit analog-to-digital converter 2.

Fig. 10 is a schematic diagram of a gain error quantization circuit. The gain error quantization circuit includes a calibration reference signal generation circuit and an N-bit digital subtraction circuit. The digital quantization code output ends D1, D2,. and D M of the N-bit analog-to-digital converter of the M channels are connected to the M groups of digital code input ends of the N-bit digital subtraction circuit, and the M +1 group of digital code input ends of the N-bit digital subtraction circuit are connected to the output quantization code output end Dref of the calibration reference signal generating circuit. The control input end of the calibration reference signal generating circuit is connected to the K bit selection code _ G output port of the control circuit; the calibration reference signal Vr _ cal generated by the calibration reference signal generation circuit is simultaneously connected to the analog signal input terminal of the N-bit analog-to-digital converter of the M channels. The K bit quantization code _ G output end of the N bit digital subtraction circuit is connected to the K bit quantization code _ G input port of the control circuit; an output port of the calibration control signal Ctrl _ mode _ G of the control circuit is connected to the calibration control signal input ports of the N-bit digital subtraction circuit and the calibration reference signal generation circuit.

Fig. 11 is an implementation of a reference voltage remote drive circuit. The reference voltage remote driving circuit comprises a reference voltage programming adjustment circuit and M +1 voltage remote driving circuits. M +1 electricityThe voltage remote driving circuit is a voltage remote driving circuit 1, a voltage remote driving circuit 2, a voltage remote driving circuit M and a voltage remote driving circuit ref. And after entering the reference voltage programming regulation circuit, the band-gap reference voltage is simultaneously output to M +1 voltage remote driving circuits. The output voltage of the reference voltage programming adjusting circuit is controlled by the K-bit global adjusting code, and the control circuit adjusts the reference voltage used by all ADC channels by adjusting the K-bit global adjusting code. Fig. 12 shows a specific implementation of the reference voltage programming regulator circuit, which is configured as a digital controlled LDO circuit. When the control signal is set to 0, the PMOS tube M31 is conducted, and the reference voltage V is generated by the negative feedback action of the operational amplifier_REFUnder the control of regulating NMOS transistor M30, obtaining an initial voltage output V by resistance voltage division_R(0)Meanwhile, the current type K-bit DAC generates a regulation current Ic to the ground, and the regulation current Ic flows through the endmost resistor R32 to the ground, so that a voltage amount Δ V ═ Ic × R32 is superimposed on the resistor R32, and a voltage V output to the reference signal output circuit_Rout＝V_R(0)(+) Δ V. According to the resistance voltage-dividing relation, outputting a reference voltage signal V_RoutChanges will occur accordingly. Therefore, the purpose of changing the output reference voltage can be realized by only controlling the K-bit global adjusting code. In the embodiment of the present invention, all the reference voltage adjusting circuits adopt the circuit structure shown in fig. 12. For the implementation of the M +1 voltage remote driving circuits, a voltage follower can be adopted.

Fig. 13 is a block diagram of the calibration reference signal generating circuit. The calibration reference signal generation circuit includes: a programmable calibration voltage generating circuit and a reference output quantization code generating circuit. The reference voltage input end of the programmable calibration voltage generation circuit is connected to the reference voltage Vrinref output by the voltage remote driving circuit, and the programmable calibration voltage generation circuit outputs a calibration reference voltage Vr _ cal under the control of a K bit selection code; the reference output quantization code generation circuit outputs a reference output quantization code Dref under the control of the K-bit selection code. The programmable calibration voltage generation circuit can be realized by adopting the circuit structure shown in fig. 12. FIG. 14 is a block diagram of a circuit for generating a reference output quantization code according to the present invention. The reference output quantization code generation circuit includes: the ROM lookup table, the ROM and the reference quantization code output circuit module are all controlled by Ctrl _ mode signals, and the reference output quantization code generation circuit only works in a calibration mode. Inputting K bit selection codes into a ROM lookup table to obtain corresponding addresses to a ROM module, outputting reference quantized code data stored in a memory unit corresponding to the corresponding addresses to a reference quantized code output circuit by the ROM module, and driving the reference quantized code data Dref to be output by the reference quantized code output circuit.

Fig. 15 is a block diagram of the control circuit. The control circuit includes: the circuit comprises a core control circuit, a selection code generating circuit, an adjusting code generating circuit, an arithmetic circuit, a K-bit register group _ G, K-bit register group _ CK, a compensation code output register 1-compensation code output register M, a delay code output register 1-delay code output register M and a channel selection circuit. The input end of the core control circuit is connected with a calibration start signal, the first output end of the core control circuit is connected to the control input end of the channel selection circuit, the second output end of the core control circuit is connected to the control input end of the arithmetic circuit, the third output end of the core control circuit is connected to the control input end of the selection code generation circuit, the fourth output end of the core control circuit is connected to the control input end of the adjustment code generation circuit, the fifth output end of the core control circuit is connected to the control input end of the K-bit register group _ CK, the sixth output end of the core control circuit is connected to the control input end of the K-bit register group _ G, M calibration control signals G _ Ctrl 1-G _ Ctrl M are generated at the seventh output end to the M +6 output end, and M calibration control signals CK _ Ctrl 1-CK _ Ctrl M are generated at the M +7 output end to the (2M + 6) output end; the data input end of the arithmetic circuit receives data sent by the K-bit register group _ CK output end and the K-bit register group _ G output end, and generates a K-bit error code according to a control instruction of the core control circuit, the K-bit error code is simultaneously transmitted to the data input ends of the compensation code output register 1-compensation code output register M and the delay code output register 1-delay code output register M, and the control signal input ends of the compensation code output register 1-compensation code output register M are respectively connected to the M calibration control signals G _ Ctrl 1-G _ Ctrl, and the control signal input ends of the delay code output register 1-delay code output register M are respectively connected to the M calibration control signals CK _ ct 1-CK _ Ctrl, please refer to fig. 15 specifically. The output ends of the compensation code output register 1 to the compensation code output register M are respectively connected to the 1 st to Mth data input ends of the channel selection circuit, and the output ends of the delay code output register 1 to the delay code output register M are respectively connected to the M +1 st to 2M data input ends of the channel selection circuit. The channel selection circuit outputs a K-bit compensation code or a K-bit delay code according to a control instruction of the core control circuit; the selection code generating circuit generates a K-bit selection code according to a control instruction of the core control circuit; the adjusting code generating circuit generates a K-bit global adjusting code according to a control instruction of the core control circuit; the data input end of the K-bit register group _ CK receives the K-bit quantization code _ CK sent by the clock phase error quantization circuit, and sends data stored in an internal register of the K-bit register group _ CK to the arithmetic circuit according to a control instruction of the core control circuit; and the data input end of the K-bit register group _ G receives the K-bit quantization code _ G sent by the gain error quantization circuit and sends the data stored in the internal register of the gain error quantization circuit to the arithmetic circuit according to the control instruction of the core control circuit.

In the circuit of FIG. 15, the calibration control signals G _ Ctrl 1M and CK _ Ctrl 1M are only one signal active at any time in the calibration mode. In the process of gain mismatch error calibration of the N-bit analog-to-digital converter of the M channel, the channel selection circuit opens the output of a compensation code output register corresponding to the N-bit analog-to-digital converter for gain mismatch error calibration, and closes the outputs of the other compensation code output registers; in the process of calibrating the clock phase mismatch error of the N-bit analog-to-digital converter of the M channel, the channel selection circuit opens the output of the delay code output register corresponding to the N-bit analog-to-digital converter for calibrating the clock phase mismatch error, and closes the outputs of the other delay code output registers.

When the operation circuit adopts a binary successive approximation algorithm to generate the K bit error code X, only 1 bit in the K bit error code X is changed in each operation; in the process of calibrating the gain mismatch error under the Y-type calibration reference voltage, the K-bit error code needs to be circularly operated for K times to generate a K-bit compensation code X cali (K) _ RY once; in the process of calibrating the gain mismatch error of the N-bit analog-to-digital converter circuit X, because the calibration reference voltage in Z needs to be calibrated, the K-bit error code needs to be circularly operated for K X Z times to obtain a K-bit compensation code X cali _ fin and keeps unchanged; in the process of calibrating the gain mismatch errors of the N-bit analog-to-digital converter circuits of all the M channels, the K-bit error codes need to be cyclically operated K × Z × M times to obtain M groups of K-bit compensation codes X calii _ fin and keep the M groups of K-bit compensation codes X calii _ fin unchanged, so that the process of calibrating the gain mismatch errors of the N-bit analog-to-digital converters of the M channels by the high-precision gain mismatch error calibration circuit for the multichannel ADC is finished.

The control circuit generates a first group of K bit delay codes 1cali (1) and a first group of K bit selection codes _ CK; the first group of K bit selection codes _ CK enters the clock phase error quantization circuit and generates a first reference clock CKinref (1), and the first group of K bit delay codes 1cali (1) enters the clock phase error compensation circuit and goes to a first error clock output port CKout 1; the clock phase error quantization circuit obtains a phase error by comparing CKout1 with a first reference clock CKinref (1), and a first group of K bit quantization codes _ CK can be obtained through conversion processing and output to the control circuit; the control circuit receives and obtains a first group of K-bit quantization codes _ CK which are stored in a K-bit register group _ CK inside the control circuit; the control circuit generates a second group of K bit delay codes 1cali (2) by adopting a binary search method according to the first group of K bit quantization codes _ CK.

Next, the second group of K-bit delay codes 1cali (2) enters a clock phase error compensation circuit and obtains a phase delay updated CKout1, and the clock phase error quantization circuit obtains a second group of K-bit quantization codes _ CK by comparing the phase updated CKout1 with the first reference clock CKinref (1); and the control circuit generates a third group of K bit delay codes 1cali (3) by adopting a binary search method according to the second group of K bit quantization codes _ CK.

And sequentially circulating, the clock phase error quantization circuit continuously generates the L-th group of K bit quantization codes _ CK, and the control circuit generates the L + 1-th group of K bit delay codes 1cali (L +1) by adopting a binary search method. When the control circuit generates the kth group of K-bit delay codes 1cali (K), the control circuit keeps the K-bit delay codes 1 unchanged, and ends the error calibration of the N-bit analog-to-digital converter circuit 1.

Then, the control circuit outputs the Xth calibration control signal CK _ CtrLX and the Xth group of K bit selection codes to generate the Xth reference clock CKinref (X), and the phase mismatch error calibration of the N bit analog-to-digital converter circuit X is started. The multichannel high-precision ADC circuit with mismatch error calibration obtains a K-th group of K-bit delay codes X in the same calibration process as the N-bit analog-to-digital converter circuit 1 and keeps the K-th group of K-bit delay codes X unchanged, and the phase mismatch error calibration of the N-bit analog-to-digital converter circuit X is finished. According to the same calibration mode, when the control circuit outputs an Mth calibration control signal CK _ CtrlM to the delay circuit M to obtain a Kth group of K bit delay codes M and keep the K group of K bit delay codes M unchanged, and after the phase mismatch error calibration of the N bit analog-to-digital converter circuit M is finished, the control circuit changes the Ctrl _ mode _ CK signal, and the multichannel high-precision ADC circuit with mismatch error calibration completes the phase mismatch error calibration of the N bit analog-to-digital converter of the M channel.

Then, the control circuit controls the gain error quantization circuit to enter a calibration mode through a Ctrl _ mode _ G signal, and simultaneously outputs a K-bit selection code _ G to the gain error quantization circuit, and the multichannel high-precision ADC circuit with mismatch error calibration starts to carry out gain mismatch error calibration on the N-bit analog-to-digital converter of the M channel; the control circuit outputs a first calibration control signal G _ Ctrl1 to the gain error compensation circuit to start the gain mismatch error calibration of the N-bit analog-to-digital converter circuit 1. The control circuit then generates a first set of K-bit selection codes _ G into the gain error quantization circuit and generates a first calibration reference voltage Vr _ cal (1); the first calibration reference voltage Vr _ cal (1) is used as an analog input signal of the N-bit analog-to-digital converter 1, so that the N-bit analog-to-digital converter 1 performs normal analog-to-digital conversion work, and firstly, gain mismatch error calibration under the 1 st calibration reference voltage is performed; the control circuit continuously generates a first group of K-bit compensation codes 1cali (1), the first group of K-bit compensation codes enters the gain error compensation circuit and obtains a first channel reference voltage Vr1 as a reference voltage of the N-bit analog-to-digital converter 1, and the N-bit analog-to-digital converter 1 obtains a first group of first output quantization codes D1 (1) through analog-to-digital conversion; the gain error quantization circuit processes the first group of first output quantization codes D1 (1) to obtain a first group of K bit quantization codes _ G and outputs the first group of K bit quantization codes _ G to the control circuit; the control circuit stores the received first group of K-bit quantization codes _ G in a K-bit register group _ G inside the control circuit; the control circuit generates a second set of K-bit compensation codes 1cali (2) by binary search according to the first set of K-bit quantization codes _ G.

Next, a second group of K-bit compensation codes 1cali (2) enters the reference voltage adjusting circuit 1 and obtains Vr1 updated by the reference voltage, and the N-bit analog-to-digital converter 1 obtains a second group of first output quantization codes D1 (2) through analog-to-digital conversion; the gain error quantization circuit processes the updated second group of first output quantization codes D1 (2) to obtain a second group of K bit quantization codes _ G and outputs the second group of K bit quantization codes _ G to the control circuit; the control circuit generates a third set of K-bit compensation codes 1cali (3) by binary search according to the second set of K-bit quantization codes _ G.

And circulating in sequence, the gain error quantization circuit can continuously generate the L-th group of K bit quantization codes _ G, and the control circuit can generate the L + 1-th group of K bit compensation codes 1cali (L +1) by adopting a binary search method. When the control circuit generates the kth K-bit compensation code 1cali (K), the control circuit stores the kth K-bit compensation code 1cali (K) into a new register and selects the K-bit compensation code 1cali (K) R1, ending the calibration of the gain mismatch error under the 1 st calibration reference voltage.

The control circuit then generates a Yth group of K bit selection codes _ G; the Y-th group of K bit selection codes _ G enters the gain error quantization circuit and generates a Y-th calibration reference voltage Vr _ cal (Y); a Y calibration reference voltage Vr _ cal (Y) as an analog input signal of the N-bit analog-to-digital converter 1, and performing gain mismatch error calibration under the Y calibration reference voltage; the high-precision gain mismatch error calibration circuit for the multichannel ADC obtains a K-bit compensation code 1cali (K) RY in the same way as the gain mismatch error calibration under the calibration reference voltage of the No. 1, and finishes the gain mismatch error calibration under the calibration reference voltage of the Y type. And sequentially circulating, when the high-precision gain mismatch error calibration circuit for the multichannel ADC obtains the last group of K-bit compensation codes 1cali (K) _ RZ and finishes the gain mismatch error calibration under the Z-th calibration reference voltage, the algorithm circuit in the control circuit operates the obtained Z groups of K-bit compensation codes 1cali (K) _ R1-cali (K) _ RZ to obtain the final K-bit compensation codes 1cali _ fin which is kept unchanged, and the high-precision gain mismatch error calibration circuit for the multichannel ADC finishes the gain mismatch error calibration of the N-bit analog-to-digital converter circuit 1.

Next, the control circuit outputs the xth calibration control signal G _ ctrl X to the gain error compensation circuit, and starts to perform gain mismatch error calibration of the N-bit analog-to-digital converter circuit X. The high-precision gain mismatch error calibration circuit for the multichannel ADC obtains a K-bit compensation code X cali _ fin by adopting the same gain mismatch error calibration process as the N-bit analog-to-digital converter circuit 1 and keeps the K-bit compensation code X cali _ fin unchanged, and the gain mismatch error calibration of the N-bit analog-to-digital converter circuit X is finished. According to the same calibration mode, when the control circuit outputs an Mth calibration control signal G _ CtrlM to the gain error compensation circuit to obtain a K-bit compensation code M cali _ fin which is kept unchanged, and after the gain mismatch error calibration of the N-bit analog-to-digital converter circuit M is finished, the control circuit changes a Ctrl _ mode _ G signal, and the multichannel high-precision ADC circuit with mismatch error calibration completes the gain mismatch error calibration of the N-bit analog-to-digital converter of the M channel; the calibration mode for the high precision gain mismatch error calibration circuit for the multi-channel ADC ends.

In the above description, N and M are both any positive integer, K is a positive integer not greater than N, X is a positive integer not greater than M, L is a positive integer not greater than K, and Z is not greater than 2^K-1 and Y is a positive integer not greater than Z.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims

1. A multi-channel high-precision ADC circuit with a mismatch error self-calibration function is characterized by comprising a gain error compensation circuit, a clock phase error compensation circuit, an N-bit analog-to-digital converter with M channels, a gain error quantization circuit, a clock phase error quantization circuit and a control circuit; the N-bit analog-to-digital converter of the M channel comprises an N-bit analog-to-digital converter 1, an N-bit analog-to-digital converter 2, an N-bit analog-to-digital converter M;

digital quantization code output ends D1, D2, and D D M of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2, the right-to-say and the N-bit analog-to-digital converter M are respectively connected with M digital quantization code input ends of the gain error quantization circuit, a calibration reference signal Vr _ cal of the gain error quantization circuit is output to analog signal input ends of the N-bit analog-to-digital converter 1, the N-bit analog-to-digital converter 2, the right-to-say and the N-bit analog-to-digital converter M, and a K-bit quantization code _ G of the gain error quantization circuit is output to a K-bit quantization code _ G input end of the control circuit;

wherein N, M and K are both any positive integer;

the multichannel high-precision ADC circuit with the mismatch error self-calibration function comprises a calibration mode and a compensation mode, and the compensation mode can be entered only after the calibration mode is finished;

when the multi-channel high-precision analog-to-digital converter enters a compensation mode, M groups of K-bit delay codes and M groups of K-bit compensation codes are kept unchanged, the multi-channel high-precision ADC circuit with mismatch error calibration simultaneously carries out phase and gain mismatch error compensation on the N-bit digital-to-analog converter of the M channels, and the gain error quantization circuit and the clock phase error quantization circuit are both closed to reduce power consumption;

2. The multi-channel high-precision ADC circuit with mismatch error self-calibration function of claim 1, wherein said clock phase error compensation circuit comprises: the clock receiving circuit, the clock duty ratio stabilizing circuit, the clock driving circuit, the M delay circuits, the M multiphase clock generating circuits and the M clock equivalent delay circuits are in one-to-one correspondence;

3. The multi-channel high-precision ADC circuit with mismatch error self-calibration function of claim 2, wherein said clock-equivalent delay circuit comprises: the device comprises a multi-phase clock circuit equivalent delay unit, a sample-and-hold circuit equivalent delay unit, a multi-stage sub-stage circuit equivalent delay unit and a digital calibration circuit equivalent delay unit; the multi-stage sub-stage circuit equivalent delay unit comprises a 1 st stage sub-stage circuit equivalent delay unit, a 2 nd stage sub-stage circuit equivalent delay unit, an R < th > stage sub-stage circuit equivalent delay unit;

wherein R is a positive integer.

4. The multi-channel high-precision ADC circuit with mismatch error self-calibration function of claim 1, wherein said clock phase error quantization circuit comprises: the circuit comprises a reference clock generating circuit, a phase discriminator, a loop filter and a K-bit analog-to-digital converter circuit;

5. The multi-channel high-precision ADC circuit with mismatch error self-calibration function of claim 1, wherein said gain error compensation circuit comprises: the device comprises a reference voltage generating circuit, a reference voltage remote driving circuit and M reference voltage adjusting circuits;

6. The multi-channel high-precision ADC circuit with mismatch error self-calibration function of claim 1, wherein said gain error quantization circuit comprises a calibration reference signal generation circuit and an N-bit digital subtraction circuit; digital quantization code output ends D1, D2,. and D M of the N-bit analog-to-digital converter of the M channels are respectively connected with M groups of digital code input ends of the N-bit digital subtraction circuit, and the M +1 group of digital code input ends of the N-bit digital subtraction circuit are connected with an output quantization code output end Dref of the calibration reference signal generating circuit; the control input end of the calibration reference signal generating circuit is connected to the K bit selection code _ G output port of the control circuit; the K bit quantization code _ G output end of the N bit digital subtraction circuit is connected to the K bit quantization code _ G input port of the control circuit; and an output port of a calibration control signal Ctrl _ mode _ G of the control circuit is connected with the input ports of the N-bit digital subtraction circuit and the calibration control signal of the calibration reference signal generating circuit.

7. The multi-channel high-precision ADC circuit with mismatch error self-calibration function of claim 1, wherein said control circuit comprises: the circuit comprises a core control circuit, a selection code generating circuit, an adjusting code generating circuit, an arithmetic circuit, a K-bit register group _ G, K-bit register group _ CK, a compensation code output register 1-a compensation code output register M, a delay code output register 1-a delay code output register M and a channel selection circuit;

8. The multi-channel high-precision ADC circuit with mismatch error self-calibration function according to claim 7, wherein when performing gain mismatch error calibration on N-bit ADC of M channels, the channel selection circuit turns on the output of the compensation code output register corresponding to the N-bit ADC performing gain mismatch error calibration, and turns off the outputs of the other compensation code output registers; when the N-bit analog-to-digital converter of the M channel is subjected to clock phase mismatch error calibration, the channel selection circuit opens the output of the delay code output register corresponding to the N-bit analog-to-digital converter which is subjected to clock phase mismatch error calibration, and closes the outputs of the other delay code output registers.

9. The multi-channel high-precision ADC circuit with mismatch error self-calibration function according to claim 7, wherein when said operation circuit uses binary successive approximation algorithm to generate K bit error code, only 1 bit of the K bit error code is changed for each operation.