CN106933299B - Low-power consumption DDS circuit with amplitude and phase error auto-correction function - Google Patents

Low-power consumption DDS circuit with amplitude and phase error auto-correction function Download PDF

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CN106933299B
CN106933299B CN201710135908.7A CN201710135908A CN106933299B CN 106933299 B CN106933299 B CN 106933299B CN 201710135908 A CN201710135908 A CN 201710135908A CN 106933299 B CN106933299 B CN 106933299B
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circuit
codes
delay
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output
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CN106933299A (en
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陈珍海
吕海江
周德金
万书芹
鲍婕
宁仁霞
孙剑
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Huangshan University
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Huangshan University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers

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Abstract

The present invention provides a kind of low-power consumption DDS circuit with amplitude and phase error auto-correction function, which includes: charge-domain range error detection amplifying circuit, charge-domain phase error detection amplifying circuit, K charge-domain analog-digital converters, control circuit, ROM module, SRAM module, phase accumulator, the first delay circuit, phase amplitude converter, the second delay circuit, compensation circuit and N current-mode DAC.The low-power consumption DDS circuit with amplitude and phase error auto-correction function can be according to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and has the characteristics that low-power consumption.

Description

Low-power consumption DDS circuit with amplitude and phase error auto-correction function
Technical field
The present invention relates to a kind of error calibration circuits, specifically a kind of to have the function of amplitude and phase error auto-correction Low-power consumption DDS circuit.
Background technique
Direct digital frequency synthesis technology is a kind of signal that required various different frequencies are synthesized by digital means, The technology of analog signal output is converted thereof into finally by digital analog converter.The technology is with its peculiar feature: can compile The advantages that journey, frequency hopping be fast, high resolution, high frequency modulation precision and one of become the major technique in current frequency synthesis technique, extensively It is general to be applied to mobile communication, the communication fields such as military and commercial radar system.
Direct Digital Frequency Synthesizers (DDS) are mainly made of three modules: phase accumulator, phase amplitude converter and Digital analog converter (DAC).Usually there are two input quantities: reference clock fs and frequency control word X for entire DDS system.It is phase-accumulated Device under the control of clock, in the input of each clock pulses, it is cumulative constantly to carry out linear phase to frequency control word.Phase The data of accumulator output are exactly the phase of composite signal, the output frequency i.e. direct digital synthesis technique of phase accumulator The signal frequency of device output.The phase value input phase amplitude converter of interception accumulator output, through operation conversion output and is somebody's turn to do The corresponding digitlization range value of phase value.Digital quantity is transformed into analog quantity by digital analog converter, using low-pass filtering Device is smooth and filters out unwanted sampled signal, output frequency pure sine or cosine signal.
From the working principle of DDS it will be seen that clock non-ideal characteristic, DAC input signal be asynchronous, inside DAC Module timing is asynchronous, in power supply and circuit design the factors such as signal cross-talk that may be present influence, can make that DAC's is defeated There are amplitude and phase errors for signal out.In practical applications, due to the fluctuation of processing technology, variation of working environment etc., also Making DDS amplitude and phase error, there are certain randomnesss, are embodied in the amplitude and phase error of different DDS chips not It is identical to the greatest extent.It is required in the application accurately controlled DDS amplitude and phase error consistency in phased array radar etc., DDS chip Between amplitude and phase error inconsistent the problem of causing DDS chip will be made to be unable to satisfy required precision.Therefore design collection There is very much realistic meaning in the high-precision amplitude and phase error auto-correction circuit in DDS chip.
Summary of the invention
The purpose of the present invention is overcoming the deficiencies in the prior art, provide a kind of with the self-correcting of amplitude and phase error The low-power consumption DDS circuit of quasi- function has been internally integrated high-precision amplitude and phase error auto-correction circuit.
The purpose of the present invention can be achieved through the following technical solutions, and described has amplitude and phase error auto-correction function The low-power consumption DDS circuit of energy, structure include: that charge-domain range error detects amplifying circuit, charge-domain phase error detection is put Big circuit, K charge-domain analog-digital converters, control circuit, ROM module, SRAM module, phase accumulator, the first delay circuit, Phase amplitude converter, the second delay circuit, compensation circuit and N current-mode DAC；
First, second input terminal of charge-domain phase error detection amplifying circuit is connected respectively to the letter of N current-mode DAC Number output difference port, the control signal of charge-domain phase error detection amplifying circuit are connected to the first K of control circuit Option code output port, the differential voltage output end of charge-domain phase error detection amplifying circuit are connected to K charge-domain moduluses The differential voltage input terminal of converter；First, second input terminal of charge-domain range error detection amplifying circuit is connected respectively to N The control signal of the signal output difference port of position current-mode DAC, charge-domain range error detection amplifying circuit is connected to control 2nd K option code output ports of circuit processed, charge-domain range error detect the differential voltage output end connection of amplifying circuit To the differential voltage input terminal of K charge-domain analog-digital converters；The position the K quantization code of K charge-domain analog-digital converters is output to control The error input port of circuit processed；
The ROM control port of control circuit exports control signal to ROM module, and the SRAM control port of control circuit exports Signal is controlled to SRAM module, the first K delay code output ends of control circuit are connected to the second input of the first delay circuit Port, the 2nd K delay code output ends of control circuit are connected to the second input port of the second delay circuit, control circuit Calibration control signal Ctrl output port is connected to charge-domain phase error detection amplifying circuit simultaneously, K charge-domain moduluses turn The calibration of parallel operation, compensation circuit, the first delay circuit and the second delay circuit controls signal Ctrl input port；
First N calibration code output ends of the first input port connection ROM module of the first delay circuit, the first deferred telegram The position the X phase controlling input code of the third input port connection phase accumulator on road, the output port of the first delay circuit is by X Hand over word is output to phase amplitude converter；2nd N calibrations of the first input port connection ROM module of the second delay circuit The N position amplitude of code output end, the third input port connection phase amplitude controller output of the second delay circuit controls input code, N hand over words are output to compensation circuit by the output port of the second delay circuit；The first input port of compensation circuit connects ROM 3rd N calibration code output ends of module, the third input port of compensation circuit connect the position the N conversion of the second delay circuit output N output codes are output to the data input pin of N current-mode DAC by code, the output port of compensation circuit；Wherein, N is positive whole Number, K are the positive integer no more than N.
The low-power consumption DDS circuit with amplitude and phase error auto-correction function, operating mode includes calibrating die Formula and compensation model；And it is introduced into calibration mode in circuit work, enters compensation model afterwards；When entering calibration mode, X Position phase controlling input code, N amplitude control input codes, N output codes, the first K delay codes, the 2nd K delay codes and K Compensation codes are invalid, and the first N calibration codes are input to the first delay circuit, and the 2nd N calibration codes are input to the second delay circuit, 3rd N calibration codes are input to compensation circuit；The charge-domain amplitude detection amplifying circuit first carries out width to N current-mode DAC Degree calibrates for error, then the charge-domain phase-detection amplifying circuit successively to N current-mode DAC and phase amplitude converter into The calibration of row phase error；When entering compensation model, X phase controlling input codes are input to the first delay circuit, N amplitude controls Input code processed is input to the second delay circuit, and N output codes are input to compensation circuit；First N calibration codes, the 2nd N calibrations Code and the 3rd N calibration codes are invalid, and the first K delay codes, the 2nd K delay codes and K compensation codes are effective；The charge-domain width Degree error calibration circuit starts to carry out N current-mode DAC range error compensation, and the charge-domain phase error calibration circuit is same When phase compensation is carried out to N current-mode DAC and phase amplitude converter.
The low-power consumption DDS circuit with amplitude and phase error auto-correction function, to the N current-mode DAC When carrying out range error calibration, the job order of circuit is as follows:
Control circuit controls charge-domain range error by Ctrl signal first and detects amplifying circuit, K charge-domain moduluses Converter and compensation circuit enter calibration mode, while exporting the 2nd K option codes and detecting amplification electricity to charge-domain range error Road；
Then control circuit generates first group of the 2nd K option code, while controlling ROM module and generating first group the 3rd N Calibration code；First group of the 3rd N calibration code enters compensation circuit and obtains N output codes, and N output codes enter N to be calibrated Position current-mode DAC circuit obtains first group of range error difference output electricity corresponding with the 3rd N calibration codes through digital-to-analogue conversion Stream；Charge-domain range error detects amplifying circuit by first group of range error differential output current amount of detection, and handles and obtain First grouping error voltage；K charge-domain analog-digital converters by the first grouping error voltage carry out analog-to-digital conversion, available first group K quantization codes of range error are simultaneously output to control circuit；Reception is obtained K quantization codes of first group of range error and deposited by control circuit Storage completes the range error quantization under a kind of input condition in SRAM module；
And then, control circuit, which can generate second group of the 2nd K option code and control ROM module simultaneously, generates second group the Three N calibration code, second group of the 3rd N calibration code enter compensation circuit and obtain N output codes, and N output codes enter to school The quasi- position N current-mode DAC circuit, obtains second group of range error corresponding with second group of the 3rd N calibration code through digital-to-analogue conversion Differential output current；Charge-domain range error detects amplifying circuit by comparing second group of differential output current and second group of benchmark Its difference is simultaneously amplified available second grouping error voltage by voltage；K charge-domain analog-digital converters are by the second grouping error Voltage carries out analog-to-digital conversion, and available K quantization codes of second group of range error are simultaneously output to control circuit；Control circuit will connect Receipts obtain K quantization codes of second group of range error and are stored in SRAM module, complete the range error under second of input condition Quantization；
It recycles according to this, when control circuit generates the K option codes of L group the 2nd and while controlling ROM module generation L group the Three N calibration code, and obtain K quantization codes of L group range error, and after being stored in SRAM module, inside control circuit Computing circuit to the K quantization codes of L group range error being stored in SRAM module will carry out that K compensation codes are calculated；Control K compensation codes can be output in compensation circuit by circuit processed at this time, and compensation circuit is arranged to compensate for mode, while keeping K Position compensation codes are constant；So far, the calibration to N current-mode DAC range errors is completed；
Each group of output above-mentioned that N current-mode DAC are carried out in range error calibration process, that control circuit generates simultaneously The 3rd N calibration codes to compensation circuit must with the 2nd K option codes for being output to charge-domain range error detection amplifying circuit It must correspond, it may be assumed that the N calibration codes of J group the 3rd must be used cooperatively with the K option codes of J group the 2nd；Wherein, L is little In 2KPositive integer；J is the positive integer no more than L.
The low-power consumption DDS circuit with amplitude and phase error auto-correction function, to the N current-mode DAC When carrying out phase error calibration with phase amplitude converter, the job order of circuit is as follows:
1, phase error calibration is carried out to N current-mode DAC first:
1.1 control circuits by Ctrl signal control charge-domain phase error detection amplifying circuit and the second delay circuit into Enter calibration mode, while exporting the first K option codes and giving charge-domain phase error detection amplifying circuit, starts to N current-modes DAC carries out phase error calibration；
1.2 then control circuit generate first group of the first K option code, while control ROM module generation first group of the 2nd N Position calibration code；First group of the 2nd N calibration code enters the second delay circuit and obtains N hand over words, and N hand over words enter to school It is poor to obtain first group of phase error corresponding with first group of the 2nd N calibration code through digital-to-analogue conversion for quasi- N current-mode DAC circuit Divide output electric current；Charge-domain phase error detection amplifying circuit passes through first group of phase error differential output current amount of detection, and It is handled to obtain first group of phase error voltage；First group of phase error voltage is carried out mould by K charge-domain analog-digital converters Number conversion, available K quantization codes of first group of phase error are simultaneously output to control circuit；Reception is obtained first by control circuit Phase error K quantization code of group is stored in SRAM module, completes the position the N current-mode DAC circuit phase under a kind of input condition Error quantization；
1.3 and then, and control circuit generates second group of the first K option code, while controlling ROM module generation second group the Two N calibration code；Second group of the 2nd N calibration code enters the second delay circuit and obtains N hand over words, and N hand over words enter The position N current-mode DAC circuit to be calibrated obtains second group of phase corresponding with second group of the 2nd N calibration code through digital-to-analogue conversion Error differential output current；Charge-domain phase error detection amplifying circuit passes through second group of phase error differential output current of detection Amount, and handled to obtain second group of phase error voltage；K charge-domain analog-digital converters by second group of phase error voltage into Row analog-to-digital conversion, available K quantization codes of second group of phase error are simultaneously output to control circuit；Control circuit obtains reception K quantization codes of second group of phase error are stored in SRAM module, complete N to be calibrated current-modes under two kinds of input conditions The quantization of DAC circuit phase error；
1.4 recycle according to this, when control circuit generation N calibration codes of L group the 2nd and the K option codes of L group the first, and To K quantization codes of L group phase error, and after being stored in SRAM module, computing circuit inside control circuit will be to depositing The K quantization codes of L group phase error stored up in K bit register group carry out that the 2nd K delay codes are calculated；Control circuit is at this time 2nd K delay codes can be output in the second delay circuit, and the 2nd K delay codes of holding are constant, control circuit is by second Delay circuit is arranged to compensate for mode, completes to calibrate the phase error of N current-mode DAC；
2, later, control circuit enters calibration mode by Ctrl signal the first delay circuit of control, while exporting K choosings It selects code and gives charge-domain phase error detection amplifying circuit, start to carry out phase error calibration to phase amplitude converter；
Control circuit controls ROM module and generates the first N calibration codes, passes through the first delay circuit, charge-domain phase error Detect amplifying circuit and K charge-domain analog-digital converters, using and to N current-mode DAC the identical step of phase error calibration Rapid and method, obtains the first K delay codes and is output in the first delay circuit, while keeping the first K delay codes constant, control First delay circuit is arranged to compensate for mode by circuit processed, completes to calibrate the phase error of phase amplitude converter；At this point, school Quasi-mode terminates；
N current-mode DAC and phase amplitude converter are carried out in phase error calibration process above-mentioned, control circuit is same When each group of the first N calibration codes generating and the 2nd N calibration codes and be output to charge-domain phase error detection amplifying circuit The first K option codes must correspond, it may be assumed that the N calibration codes of J group the first and the 2nd N calibration codes must and J group First K option codes are used cooperatively；Wherein, L is no more than 2KPositive integer, J is positive integer no more than L.
Further, in the low-power consumption DDS circuit with amplitude and phase error auto-correction function, the charge Domain phase error detection amplifying circuit include: current sense resistor, reference clock generation circuit, phase discriminator, loop filter and First charge-domain voltage amplifier circuit；The both ends of current sense resistor are connected respectively to charge-domain phase error detection amplifying circuit The first, second input terminal, and be connected respectively to the first and second input terminals of phase discriminator；Reference clock generation circuit is at K Under the control of option code, generates reference clock and be connected to the third input terminal of phase discriminator；Signal of the phase discriminator to 3 input terminals It carries out further phase bit comparison and obtains phase error signal；Phase error signal filters to obtain voltage letter by loop filter Number Vi；ViAmplify to obtain error signal Vop and Von by the first charge-domain voltage amplifier circuit.
Further, in the low-power consumption DDS circuit with amplitude and phase error auto-correction function, the charge-domain It includes: current sense resistor, reference data generation circuit, the insensitive high-speed switch capacitor of common mode that range error, which detects amplifying circuit, Differential voltage signal sampling network and the second charge-domain voltage amplifier circuit；The both ends of current sense resistor are connected respectively to charge Domain range error detects the first and second input terminals of amplifying circuit, and is connected to the insensitive high-speed switch capacitor differential electrical of common mode Press the first and second input terminals of signal sampling network；Reference data generation circuit generates difference under the control of K option codes Reference voltage output, and it is connected to the third and fourth defeated of the insensitive high-speed switch capacitor differential voltage signal sampling network of common mode Enter end；Switching capacity differential voltage signal sampling network further samples the voltage signal of 4 input terminals, obtains difference Divided voltage signal Vi+ and Vi-；Amplify to obtain error signal Vop and Von by the second charge-domain voltage amplifier circuit.
Further, in the low-power consumption DDS circuit with amplitude and phase error auto-correction function, the position K Charge-domain analog-digital converter includes: the P grades of assembly line grade circuits based on charge-domain signal processing technology, is used for sampling The charge packet arrived carries out various processing and completes analog-to-digital conversion and surplus amplification, and the output digital code of each height grade circuit is defeated Enter to delay SYN register, and the charge packet of each height grade circuit output enters next stage, each height grade circuit repeats The same course of work；P+1 grades and afterbody A-bitFlash analog-digital converter circuit, P grades are transmitted Charge packet be re-converted into voltage signal, and carry out the analog-to-digital conversion work of afterbody, and by the output number of the same level circuit Character code is input to delay SYN register, this grade of circuit only completes analog-to-digital conversion, amplifies without surplus；The synchronous deposit of delay Device is used to carry out delay alignment to the digital code of each sub- pipelining-stage output, and the digital code of alignment is input to digital school Positive module；Digital correction circuit module is used to receive the output digital code of SYN register, received digital code is moved Position is added, to obtain the R bit digital output code of analog-digital converter；Wherein, R is positive integer, and P and A are just whole no more than R Number.
Further, in the low-power consumption DDS circuit with amplitude and phase error auto-correction function, described first prolongs Slow circuit and the second delay circuit are all made of identical delay circuit, and structure includes: N number of delay buffer cell and N number of K delay Register；Wherein, the first K delay time registers~delay time register of n-th K delay code input terminal is all connected to K Postpone code, control signal input is all connected to Ctrl signal；First delay buffer cell~N delay buffer cell prolongs Slow code input terminal is connected respectively to the first K delay time registers~delay time register of n-th K delay code output end, and first Delay buffer cell~N delay buffer cell data output end is connected respectively to the 1st hand over word~N hand over words simultaneously Output, the first delay buffer cell~N delay buffer cell first control signal input terminal are all connected to Ctrln letter Number, the first delay buffer cell~N delay buffer cell second control signal input terminal is all connected to Ctrl signal；Its In, Ctrl and Ctrln are one group of reverse signal.
Further, in the low-power consumption DDS circuit with amplitude and phase error auto-correction function, the compensation electricity It include: delay buffer circuit and K add circuits inside road, and the delay of be delayed buffer circuit and K add circuits is necessary It is equal；Compensation circuit can operate under the control of Ctrl signal is calibrated and compensated mode both of which；
When in the calibration mode, Ctrl signal is effective, and the output of K add circuits will be invalid, and the 3rd N calibration codes are through prolonging When buffer circuit after obtain N output codes and export；
When in the compensation mode, Ctrln signal is effective, and the output of K add circuits will be effective, and N-K hand over words are through prolonging When buffer circuit after obtain N-K output codes and export, K hand over words are added to obtain with K compensation codes by K add circuits K output codes simultaneously export.
Further, in the low-power consumption DDS circuit with amplitude and phase error auto-correction function, the control electricity Road includes: core control circuit, ROM reading circuit, the first delay code generation circuit, the second delay code generation circuit, compensation codes Generation circuit, option code generation circuit, computing circuit, SRAM read/write circuit and K bit register；
The connection relationship of foregoing circuit are as follows: the first output end of core control circuit is connected to the input of ROM reading circuit End, the second output terminal of core control circuit are connected to the control signal of the first delay code generation circuit, core control circuit Third output end be connected to the control signal of the second delay code generation circuit, the 4th output end connection of core control circuit To the control signal of compensation codes generation circuit, the 5th output end of core control circuit is connected to the control input of computing circuit End, the 6th output end of core control circuit are connected to the control signal of option code generation circuit, and the of core control circuit Seven output ends generate calibration control signal Ctrl, the 8th output end of core control circuit be connected to simultaneously K bit register and The control signal of SRAM read/write circuit, the input terminal of core control circuit are connected to calibration starting control signal；ROM reads electricity Road generates ROM address code according to the control instruction of core control circuit；The data input pin of computing circuit receives SRAM read-write electricity The data that road output end is sent, and the first K error codes, the 2nd K errors are generated according to the control instruction of core control circuit Code and the 3rd K error codes；The data input pin of first delay code generation circuit receives what computing circuit data output end was sent First K error codes, and the first K delay codes are generated according to the control instruction of core control circuit；Second delay code generates electricity The data input pin on road receives the 2nd K error codes that computing circuit data output end is sent, and according to core control circuit Control instruction generates the 2nd K delay codes；The data input pin of compensation codes generation circuit receives computing circuit data output end hair K error codes of the 3rd sent, and K compensation codes are generated according to the control instruction of core control circuit；Option code generation circuit root The first K option codes and the 2nd K option codes are generated according to the control instruction of core control circuit；The data of K bit register input End receives the position the K quantization code that the output end of the K charge-domain analog-digital converter is sent, and according to the control of core control circuit The data of storage inside it are sent to SRAM read/write circuit by instruction；SRAM read/write circuit is according to the control of core control circuit Instruction generates SRAM address date code, carries out reading data and write-in to SRAM module.
The invention has the advantages that the designed low-power consumption DDS circuit with amplitude and phase error auto-correction function can According to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and has the characteristics that low-power consumption.By using charge-domain Signal processing technology does not use operational amplifier in terms of error detection process, has the characteristics that low-power consumption；Using charge-domain ADC Error signal is quantified, error compensating method all uses Digital Signal Processing, further realizes power consumption minimum And has the characteristics that low-power consumption.
Detailed description of the invention
Fig. 1 is the low-power consumption DDS circuit block diagram that the present invention has amplitude and phase error auto-correction function.
Fig. 2 is charge-domain phase error detection amplification circuit structure block diagram of the present invention.
Fig. 3 is charge-domain voltage amplifier circuit schematic diagram of the present invention.
Fig. 4 is charge-domain voltage amplifier circuit working waveform figure of the present invention.
Fig. 5 is phase detector circuit structural block diagram of the present invention.
Fig. 6 is reference clock generation circuit structural block diagram of the present invention.
Fig. 7 is that charge-domain range error of the present invention detects amplification circuit structure block diagram.
Fig. 8 is reference data generation circuit structural block diagram of the present invention.
Fig. 9 is charge-domain analog-digital converter circuit block diagram of the present invention.
Figure 10 is charge-domain pipelined sub- grade circuit block diagram of the present invention.
Figure 11 is delay circuit structural block diagram of the present invention.
Figure 12 is compensation circuit structural block diagram of the present invention.
Figure 13 is control circuit block diagram of the present invention.
Specific embodiment
The preferred embodiment of the present invention is described in detail below in conjunction with attached drawing.
Fig. 1 show the low-power consumption DDS circuit block diagram that the present invention has amplitude and phase error auto-correction function.The tool The low-power consumption DDS circuit for having amplitude and phase error auto-correction function includes: charge-domain range error detection amplifying circuit 10, electricity Lotus domain phase error detection amplifying circuit 11, K charge-domain analog-digital converters 12, control circuit 13, ROM module 15, SRAM mould Block 14, phase accumulator 16, the first delay circuit 17, phase amplitude converter 18, the second delay circuit 19, compensation circuit 110 With N current-mode DAC111.
The connection relationship of foregoing circuit are as follows: the first and second input terminals of charge-domain phase error detection amplifying circuit 11 point It is not connected to the signal output difference port (to induction signal Iop and Ion) of N current-mode DAC111, the inspection of charge-domain phase error The control signal for surveying amplifying circuit 11 is connected to the first K option code output ports of control circuit 13, and charge-domain phase is missed The differential voltage output end of difference detection amplifying circuit 11 is connected to the differential voltage input terminal of K charge-domain analog-digital converters 12； First and second input terminals of charge-domain range error detection amplifying circuit 10 are connected respectively to the signal of N current-mode DAC111 The control signal of output difference port, charge-domain range error detection amplifying circuit 10 is connected to the 2nd K of control circuit 13 The differential voltage output end of position option code output port, charge-domain range error detection amplifying circuit 10 is connected to K charge-domains The differential voltage input terminal of analog-digital converter 12；The position the K quantization code of K charge-domain analog-digital converters 12 is output to control circuit 13 Error input port；
The ROM control port of control circuit 13 exports control signal to ROM module 15, the SRAM control terminal of control circuit 13 Mouth exports control signal to SRAM module 14, and the first K delay code output ends of control circuit 13 are connected to the first delay circuit 2nd K delay code output ends of 17 the second input port, control circuit 13 are connected to the second defeated of the second delay circuit 19 The calibration control signal Ctrl output port of inbound port, control circuit 13 is connected to charge-domain phase error detection amplification electricity simultaneously The calibration on road 11, K charge-domain analog-digital converters 12, compensation circuit 110, the first delay circuit 17 and the second delay circuit 19 Control signal Ctrl input port；
First N calibration code output ends of the first input port connection ROM module 15 of the first delay circuit 17, first prolongs The position the X phase controlling input code of the third input port connection phase accumulator 16 of slow circuit 17, the first delay circuit 17 it is defeated X hand over words are output to phase amplitude converter 18 by exit port；The first input port of second delay circuit 19 connects ROM mould 2nd N calibration code output ends of block 15, the third input port connection phase amplitude controller output of the second delay circuit 19 N position amplitude control input code, N hand over words are output to compensation circuit 110 by the output port of the second delay circuit 19；Compensation 3rd N calibration code output ends of the first input port connection ROM module 15 of circuit 110, the third input of compensation circuit 110 Port connects the position the N hand over word of the second delay circuit 19 output, and N output codes are output to N by the output port of compensation circuit 110 The data input pin of position current-mode DAC111.
Low-power consumption DDS circuit of the present invention with amplitude and phase error auto-correction function, including calibration mode and Two kinds of operating modes of compensation model.It is introduced into calibration mode in circuit work, enters compensation model afterwards；Entering calibration mode When, X phase controlling input codes, N amplitudes control input code, N output codes, the first K delay codes, the 2nd K delay codes Invalid with K compensation codes, the first N calibration codes are input to the first delay circuit 17, and the 2nd N calibration codes are input to second and prolong Slow circuit 19, the 3rd N calibration codes are input to compensation circuit 110；The charge-domain range error calibration circuit is first to N electric currents Mould DAC111 carries out range error calibration, and then the charge-domain phase error calibration circuit is successively to N current-mode DAC111 Phase error calibration is carried out with phase amplitude converter 18；When entering compensation model, X phase controlling input codes are input to the One delay circuit 17, N amplitude control input codes are input to the second delay circuit 19, and N output codes are input to compensation circuit 110；First N calibration codes, the 2nd N calibration codes and the 3rd N calibration codes are invalid, the first K delay codes, the 2nd K delays Code and K compensation codes are effective；The charge-domain range error calibration circuit starts to carry out range error to N current-mode DAC111 Compensation, the charge-domain phase error calibration circuit carry out phase to N current-mode DAC111 and phase amplitude converter 18 simultaneously Position compensation.
One, the present invention has the low-power consumption DDS circuit of amplitude and phase error auto-correction function to N current-mode DAC111 Carry out the calibrating principle of range error calibration are as follows:
When calibration mode is opened, control circuit 13 controls the detection amplification of charge-domain range error by Ctrl signal first Circuit 10, K charge-domain analog-digital converters 12 and compensation circuit 110 enter calibration mode, at the same export the 2nd K option codes to Charge-domain range error detects amplifying circuit 10；Then control circuit 13 generates first group of the 2nd K option code, control simultaneously ROM module 15 generates first group of the 3rd N calibration code；First group of the 3rd N calibration code enters compensation circuit 110 and obtains N Output code, N output codes enter the position N current-mode DAC111 circuit to be calibrated, obtain and the 3rd N calibration codes through digital-to-analogue conversion Corresponding first group of range error differential output current signal Iop and Ion；Charge-domain range error detection amplifying circuit 10 passes through Detect Iop-Ion amount, be processed to and with first group of reference voltage Vrefp- caused by internal reference reference generating circuit Vrefn is compared, and its difference is amplified available error voltage Vop-Von；K charge-domain analog-digital converters 12 Error voltage Vop-Von is subjected to analog-to-digital conversion, available K quantization codes of first group of range error are simultaneously output to control circuit 13；Reception is obtained K quantization codes of first group of range error and is stored in SRAM module 14 by control circuit 13, completes a kind of input Under the conditions of range error quantization.
And then, control circuit 13, which can generate second group of the 2nd K option code and control ROM module 15 simultaneously, generates second The 3rd N calibration codes of group, second group of the 3rd N calibration code enter compensation circuit 110 and obtain N output codes, N output codes into Enter the position N current-mode DAC111 circuit to be calibrated, is obtained through digital-to-analogue conversion second group corresponding with second group of the 3rd N calibration code Range error differential output current；Charge-domain range error detect amplifying circuit 10 by comparing second group of differential output current and Its difference is simultaneously amplified available second grouping error voltage Vop-Von by second group of reference voltage；K charge-domain moduluses turn Second grouping error voltage Vop-Von is carried out analog-to-digital conversion by parallel operation 12, and available K quantization codes of second group of range error are simultaneously defeated Control circuit 13 is arrived out；Reception is obtained K quantization codes of second group of range error and is stored in SRAM module 14 by control circuit 13, Complete the range error quantization under second of input condition.
It recycles according to this, generates L when control circuit 13 generates the K option codes of L group the 2nd and controls ROM module 15 simultaneously The 3rd N calibration codes of group, and obtain K quantization codes of L group range error, and after being stored in SRAM module 14, control circuit Computing circuit inside 13 will carry out being calculated K to the K quantization codes of L group range error being stored in SRAM module 14 Compensation codes.
K compensation codes can be output in compensation circuit 110 by control circuit 13 at this time, and compensation circuit 110 is arranged to Compensation model, while keeping K compensation codes constant.The low-power consumption DDS electricity with amplitude and phase error auto-correction function Complete the calibration to N current-mode DAC111 range errors in road.
In above-mentioned calibration process, each group of the generation simultaneously of control circuit 13 is output to the 3rd N schools of compensation circuit 110 Quasi- code and the 2nd K option codes for being output to charge-domain range error detection amplifying circuit 10 must correspond, it may be assumed that J group 3rd N calibration codes must must be used cooperatively with the K option codes of J group the 2nd, wherein L is no more than 2KPositive integer, J For the positive integer no more than L.
Two, the low-power consumption DDS circuit of the present invention with amplitude and phase error auto-correction function is to N current-modes DAC111 and phase amplitude converter 18 carry out the calibrating principle of phase error calibration are as follows:
The low-power consumption DDS circuit with amplitude and phase error auto-correction function is completed to N current-mode DAC111 After the calibration of range error, control circuit 13 controls charge-domain phase error detection amplifying circuit 11 and second by Ctrl signal Delay circuit 19 enters calibration mode, while exporting the first K option codes to charge-domain phase error detection amplifying circuit 11, opens Begin to carry out phase error calibration to N current-mode DAC111.
Then control circuit 13 generates first group of the first K option code, while controlling ROM module 15 and generating first group second N calibration codes；First group of the 2nd N calibration code enters the second delay circuit 19 and obtains N hand over words, and N hand over words enter N current-mode DAC111 circuit to be calibrated obtains first group of phase corresponding with first group of the 2nd N calibration code through digital-to-analogue conversion Error differential output current Iop and Ion；Charge-domain phase error detection amplifying circuit 11 is located by detection Iop-Ion amount It manages and carries out phase-detection with first group of reference clock caused by internal reference clock generation circuit 21, and by its phase difference Value amplifies available error voltage Vop-Von；K charge-domain analog-digital converters 12 carry out error voltage Vop-Von Analog-to-digital conversion, available K quantization codes of first group of phase error are simultaneously output to control circuit 13；Control circuit 13 will receive It is stored in SRAM module 14 to K quantization codes of first group of phase error, completes the position the N current-mode under a kind of input condition DAC111 current phase error quantization.
And then, control circuit 13 generates second group of the first K option code, while controlling ROM module 15 and generating second group 2nd N calibration codes；Second group of the 2nd N calibration code enters the second delay circuit 19 and obtains N hand over words, N hand over words Into the position N current-mode DAC111 circuit to be calibrated, obtained and second group of the 2nd N calibration code corresponding second through digital-to-analogue conversion Group differential output current Iop and Ion；Charge-domain phase error detection amplifying circuit 11 is processed to by detection Iop-Ion amount And phase-detection is carried out with second group of reference clock caused by internal reference clock generation circuit 21, and by its phase difference value Amplify available error voltage Vop-Von；Error voltage Vop-Von is carried out mould by K charge-domain analog-digital converters 12 Number conversion, available K quantization codes of second group of phase error are simultaneously output to control circuit 13；Control circuit 13 obtains reception K quantization codes of second group of phase error are stored in SRAM module 14, complete N to be calibrated current-modes under two kinds of input conditions DAC111 current phase error quantization.
It recycles according to this, when controller generation N calibration codes of L group the 2nd and the K option codes of L group the first, and obtains L Phase error K quantization code of group, and after being stored in SRAM module 14, the computing circuit inside control circuit 13 will be to storage K quantization codes of L group phase error in K bit register group carry out that the 2nd K delay codes are calculated.Control circuit 13 is at this time 2nd K delay codes can be output in the second delay circuit 19, and keep the 2nd K delay codes constant, control circuit 13 will Second delay circuit 19 is arranged to compensate for mode, completes to calibrate the phase error of N current-mode DAC111.
Later, control circuit 13 controls the first delay circuit 17 into calibration mode by Ctrl signal, while exporting K Option code starts to carry out phase error calibration to phase amplitude converter 18 to charge-domain phase error detection amplifying circuit 11. Control circuit 13 controls ROM module 15 and generates the first N calibration codes, is examined by the first delay circuit 17, charge-domain phase error Survey amplifying circuit 11 and K charge-domain analog-digital converters 12, using and to N current-mode DAC111 phase error calibrate it is identical The step of and method, obtain the first K delay codes and be output in the first delay circuit 17, at the same keep the first K delay codes Constant, the first delay circuit 17 is arranged to compensate for mode by control circuit 13, completes to miss the phase of phase amplitude converter 18 Difference calibration.
At this point, the calibration mode of the low-power consumption DDS circuit with amplitude and phase error auto-correction function terminates.
In above-mentioned phase error calibration process, each group of the first N calibration codes and that control circuit 13 generates simultaneously Two N calibration code and the first K option codes for being output to charge-domain phase error detection amplifying circuit 11 must correspond, That is: N calibration codes of J group the first and the 2nd N calibration codes must must be used cooperatively with the K option codes of J group the first.
Low-power consumption DDS circuit of the present invention with amplitude and phase error auto-correction function is in actual use process In, precision, hardware spending size and the prover time length to calibrate for error to DDS amplitude and phase can be different according to selecting K and L value is configured, to meet the calibration accuracy and rate request of different accuracy and speed DDS chip.
Fig. 2 is a kind of implementation of charge-domain phase error detection amplifying circuit 11 of the present invention.The circuit includes: electric current Detection resistance Rd, reference clock generation circuit 21, phase discriminator 22, loop filter 23 and the first charge-domain voltage amplifier circuit 24.The both ends of current sense resistor Rd are connected respectively to the first, second input of charge-domain phase error detection amplifying circuit 11 End, and it is connected to the first, second input terminal Voutp and Voutn of phase discriminator 22；Reference clock generation circuit 21 is selected at K Under the control of code, generates reference clock Clkref and be connected to the third input terminal of phase discriminator 22；Phase discriminator 22 is to 3 input terminals Signal carry out further phase bit comparison and obtain phase error signal Vp, phase error signal Vp is by the filter of loop filter 23 Wave obtains voltage signal Vi；Error signal Vop and Von are obtained by the amplification of the first charge-domain voltage amplifier circuit 24.
Fig. 3 show 24 schematic diagram of the first charge-domain voltage amplifier circuit of the present invention.First charge-domain voltage amplification Circuit 24 includes: the first anode charge-storage node Nip, the first negative terminal charge-storage node Nin, the second anode charge storage section Point Nop and the second negative terminal charge-storage node Non, one be connected to the first and second anode charge-storage node Nip and Nop it Between anode charge transmit control switch 301, one be connected between the first and second negative terminal charge-storage node Nin and Non Negative terminal charge transmission control switch 302, be connected to the first anode charge-storage node Nip anode capacitor 303, be connected to the The anode capacitance programmable capacitor 309 of two anode charge-storage node Nop is connected to the first negative terminal charge-storage node Nin's Negative terminal capacitor 304, is being connected to first just at the negative terminal capacitance programmable capacitor 310 for being connected to the second negative terminal charge-storage node Non It holds the first anode voltage transmission switch 305 of charge-storage node Nip, be connected to the of the first anode charge-storage node Nip Two anode voltage transmission switches 307, the third anode voltage transmission switch 313 for being connected to the second anode charge-storage node Nop It is deposited with being connected to the 4th anode voltage transmission switch 311 of the second anode charge-storage node Nop, being connected to the first negative terminal charge The the second negative terminal electricity for storing up the first negative terminal voltage transmitting switch 306 of node Nin, being connected to the first negative terminal charge-storage node Nin Pressure transmitting switch 308 is connected to the third negative terminal voltage transmitting switch 314 of the second negative terminal charge-storage node Non and is connected to The 4th negative terminal voltage transmitting switch 312 of second negative terminal charge-storage node Non.For the embodiment of the present invention, the first charge-domain Any end connects Vi in two analog voltage inputs of voltage amplifier circuit 24, and other end connects reference signal can be real It is existing.
Fig. 4 is that the working sequence of circuit shown in Fig. 3 controls waveform diagram.Controlling clock Clk and Clkn is opposite in phase Clock, switch control signal Clkr, Clks and Clkt are that phase does not overlap clock.Heretofore described charge transmission control is opened Close can embodiment described in the patent of invention using Patent No. 201010291245.6 realize, the voltage biography Defeated switch can be realized using general metal-oxide-semiconductor or BJT switch.
Fig. 5 show a kind of implementation of 22 circuit of phase discriminator of the present invention.The circuit by signal shaping module and One subtractor sub-module is constituted.Input differential signal Voutp and Voutn progress shaping are obtained input phase by signal shaping module Position, for the reference clock of reference clock output as fixed phase, input phase and fixed phase are carried out phase by subtractor sub-module Subtract, obtains phase error signal Vp.
Fig. 6 show 21 structural block diagram of reference clock generation circuit of the present invention.The reference clock generation circuit 21 It include: a programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit.The programmable frequency adjustment circuit It is controlled by K option codes with the programmable duty cycle adjustment circuit.Under the control of K option codes, frequency and duty ratio Fixed input clock successively passes through after the programmable frequency adjustment circuit and the programmable duty cycle adjustment circuit, i.e., The reference clock Clkref of different frequency and duty ratio can be obtained.
Fig. 7 is a kind of implementation that charge-domain range error of the present invention detects amplifying circuit 10, and the circuit is using complete poor Separation structure is realized.The circuit includes: current sense resistor Rd, reference data generation circuit 71, the insensitive high-speed switch electricity of common mode Tolerance divided voltage signal sampling network 72 and the second charge-domain voltage amplifier circuit 73.
The both ends of current sense resistor Rd are connected respectively to the first and the of charge-domain range error detection amplifying circuit 10 Two input terminals, and it is connected to the first, second input of the insensitive high-speed switch capacitor differential voltage signal sampling network 72 of common mode Hold Voutp and Voutn；Reference data generation circuit 71 generates differential reference voltage output end under the control of K option codes Vrefp and Vrefn, and it is connected to the third and fourth of the insensitive high-speed switch capacitor differential voltage signal sampling network 72 of common mode Input terminal；Switching capacity differential voltage signal sampling network 72 further samples the voltage signal of 4 input terminals, obtains To differential voltage signal Vi+ and Vi-；Error signal Vop and Von are obtained by the amplification of the second charge-domain voltage amplifier circuit 73.
Fig. 8 show reference data generation circuit structural block diagram of the present invention.The reference data generation circuit includes: One resistance string, a switch arrays and an output switch selection circuit.Resistance string is by 2K- 1 equal-sized resistance string Join, both ends are separately connected reference voltage 3 and reference voltage 4, pass through 2K- 1 equal-sized electric resistance partial pressure can obtain To 2KKind voltage；Switch arrays include 2K- 1 voltage-selected switch exports one group under the control of output switch selection circuit Differential reference voltage Vrefp and Vrefn；Output switch selection circuit selects to open 2 switch arrays under the control of K option codes Voltage transmission switch in column.Reference data generation circuit generates one group of differential reference voltage according to any one group of K option code Vrefp and Vrefn.Reference voltage 3 and reference voltage 4 shown in fig. 8 are respectively Vref3 and Vref4 shown in Fig. 1.
As shown in figure 9, the position the K charge-domain analog-digital converter 12 that the present invention designs includes: P grades based on charge-domain signal processing Assembly line grade circuit, afterbody (P+1 grades) A-bitFlash analog-digital converter circuit, the delay SYN register of technology With digital correction circuit module.In addition operating mode control module is also back work mould necessary to analog-digital converter works Block, the module are not identified in figure.In Fig. 9 in charge-domain analog-digital converter circuit adjacent two-stage grade circuit work by The digit k of every grade of circuit of sum of series of the control of two groups of multi-phase clocks, working condition complete complementary, and sub- grade circuit can spirit Adjustment living.Such as 14 analog-digital converters for K=14, totally 13 grades of+1 grade of 2bitFlash of 12 grades of 1.5bit/ grades can be used Structure, can also be using+1 grade of 3bitFlash of+3 grades of 1.5bit/ grades of 4 grades of 2.5bit/ grades totally 8 grades of structure.
The charge-domain analog-digital converter that the present invention designs includes the following contents: P grades based on charge-domain signal processing technology Charge-domain pipelined sub- grade circuit is used to carry out various processing completion analog-to-digital conversions to the charge packet that sampling obtains and surplus is put Greatly, and by the output digital code of each height grade circuit it is input to delay SYN register, and each height grade circuit output Charge packet enters next stage and repeats the above process；Afterbody (P+1 grades) A-bitFlash analog-digital converter circuit, by The P grades of charge packets transmitted are re-converted into voltage signal, and carry out the analog-to-digital conversion work of afterbody, and the same level is electric The output digital code on road is input to delay SYN register, this grade of circuit only completes analog-to-digital conversion, amplifies without surplus；Delay SYN register is used to carry out delay alignment to the digital code of each sub- pipelining-stage output, and the digital code of alignment is inputted To figure adjustment module；Digital correction circuit module is used to receive the output digital code of SYN register, by received number Code carries out shifter-adder, to obtain the R bit digital output code of analog-digital converter.In above description, R is positive integer, and A and P are Positive integer no more than R.
It is charge-domain pipelined sub- grade circuit diagram shown in Figure 10.Circuit by fully differential signal processing channel structure At, entire circuit include: 2 the same level charges transmission control switches, 2 charge-storage nodes, 6 be connected to charge-storage node Charge storage capacitance, C charge comparator, the reference signal selection circuits that C control by comparator output result, 2B+2 is a Voltage transmission switch, wherein B is positive integer.When circuit works normally, prime differential electrical pocket is transmitted by charge control first Switch is transmitted and stored at the same level charge-storage node, the voltage between the comparator node caused to the input of differential electrical pocket Poor variable quantity is compared with reference voltage 3 and reference voltage 4, obtains C quantization output digital code D1~DB of the same level；Number is defeated Code D1~DB will be output to delay SYN register out, while D1~DB will also control the reference signal selection electricity of the same level respectively Road makes them generate the reference signal of a pair of of complementation respectively and controls the same level positive and negative terminal charge plus-minus capacitor bottom plate respectively, to by preceding The differential electrical pocket that grade is transferred to the same level carries out plus-minus processing of corresponding size, obtains the same level differential margin charge packet；Finally, electric The same level differential margin charge packet is completed by the downward Primary Transmit of the same level in road, reference voltage 2 to the same level differential charge memory node into Row resets, and completes the work of charge-domain pipelined sub- one whole clock cycle of grade circuit.Wherein, C is positive integer.
Electricity is based on for (P+1 grades) of afterbody of the charge-domain pipelined analog-digital converter that the present invention designs in Fig. 9 The assembly line grade circuit A-bitFlash analog-digital converter circuit of lotus domain signal processing technology, the sub- grade circuit will only need to dock The charge packet that receives carries out the analog-to-digital conversion work of afterbody, and the same level circuit output digital code is input to delay synchronizes and post Storage, and without surplus processing.4 for removing the reference signal selection circuit in Figure 10 and being controlled by reference signal selection circuit A capacitor.
Figure 11 show delay circuit structural block diagram of the present invention.It include: N number of delay inside the delay circuit Buffer cell and N number of K delay time register, the first delay buffer cell~N delay buffer cell and the first K delay deposits Device~the delay time register of n-th K.First K delay time registers~delay time register of n-th K delay code input terminal is complete Portion is connected to K delay codes, and control signal input is all connected to Ctrl signal；First delay buffer cell~N delay The delay code input terminal of buffer cell is connected respectively to the first K delay time registers~delay time register of n-th K delay code Output end, the first delay buffer cell~N delay buffer cell data output end are connected respectively to the 1st hand over word~the N hand over words simultaneously export, and the first delay buffer cell~N delay buffer cell first control signal input terminal all connects To Ctrln signal, the first delay buffer cell~N delay buffer cell second control signal input terminal is all connected to Ctrl signal.Wherein, Ctrl and Ctrln is reversed clock.
Delay circuit is operable under the control of Ctrl signal is calibrated and compensated mode both of which.In the calibration mode When, Ctrl signal is effective, and the 1st hand over word~N input codes are invalid, input code for N hand over words output without any It influences, the 1st calibration code~N calibration codes obtain the 1st after being delayed buffer circuit 1~delay buffer circuit N respectively and turn Escape~N hand over words simultaneously export, and K delay codes are input into the first K delay time registers~delay of n-th K deposit In device and it is latched and remains unchanged.When in the compensation mode, Ctrln signal is effective, and the 1st hand over word~N input codes have Effect, and obtain the 1st hand over word~N hand over words after being delayed buffer circuit and export, the 1st calibration code~N schools Quasi- code is invalid, and the position the K delay code stored in the first K delay time registers~delay time register of n-th K is input into delay Compensation of delay is carried out in buffer circuit 1~delay buffer circuit N.
First delay circuit 17 of the present invention and the second delay circuit 19 are all made of delay circuit shown in Figure 11.
Figure 12 show 110 structural block diagram of compensation circuit of the present invention.It include that delay is slow inside the compensation circuit 110 Circuit and K add circuits are rushed, and the delay of be delayed buffer circuit and K add circuits must be equal.Compensation circuit 110 exists It is operable under the control of Ctrl signal and is calibrated and compensated mode both of which.When in the calibration mode, Ctrl signal is effective, K The output of position add circuit will be invalid, and the 3rd N calibration codes obtain N output codes and exported after being delayed buffer circuit.It is mending When repaying under mode, Ctrln signal is effective, and the output of K add circuits will be effective, and N-K hand over words are after being delayed buffer circuit It obtains N-K output codes and exports, K hand over words are added to obtain K output codes simultaneously with K compensation codes by K add circuits Output, wherein Ctrl and Ctrln is reversed clock.
Figure 13 show 13 block diagram of control circuit of the present invention.The control circuit 13 include: core control circuit, ROM reading circuit, the first delay code generation circuit, the second delay code generation circuit, compensation codes generation circuit, option code generate electricity Road, computing circuit, SRAM read/write circuit and K bit register.
The connection relationship of the control circuit 13 are as follows: the first output end of core control circuit is connected to ROM reading circuit Input terminal, the second output terminal of core control circuit is connected to the control signal of the first delay code generation circuit, core control The third output end of circuit processed is connected to the control signal of the second delay code generation circuit, the 4th output of core control circuit End is connected to the control signal of compensation codes generation circuit, and the 5th output end of core control circuit is connected to the control of computing circuit Input terminal processed, the 6th output end of core control circuit are connected to the control signal of option code generation circuit, core control electricity 7th output end on road generates calibration control signal Ctrl, and the 8th output end of core control circuit is connected to K deposits simultaneously The control signal of device and SRAM read/write circuit, the input terminal of core control circuit are connected to calibration starting control signal；ROM is read Circuit generates ROM address code according to the control instruction of core control circuit out；The data input pin of computing circuit receives SRAM and reads The data that write circuit output end is sent, and the first K error codes, the 2nd K are generated according to the control instruction of core control circuit Error codes and the 3rd K error codes；The data input pin of first delay code generation circuit receives computing circuit data output end hair K error codes of the first sent, and the first K delay codes are generated according to the control instruction of core control circuit；Second delay code produces The data input pin of raw circuit receives the 2nd K error codes that computing circuit data output end is sent, and controls electricity according to core The control instruction on road generates the 2nd K delay codes；The data input pin of compensation codes generation circuit receives the output of computing circuit data The 3rd K error codes sent are held, and K compensation codes are generated according to the control instruction of core control circuit；Option code generates electricity Road generates the first K option codes and the 2nd K option codes according to the control instruction of core control circuit；The data of K bit register Input terminal receives the position the K quantization code that the output end of the K charge-domain analog-digital converter 12 is sent, and according to core control circuit Control instruction be sent to SRAM read/write circuit for data inside it are stored；SRAM read/write circuit is according to core control circuit Control instruction generate SRAM address date code, reading data and write-in are carried out to SRAM module 14.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (10)

1. the low-power consumption DDS circuit with amplitude and phase error auto-correction function, characterized in that include: that charge-domain amplitude is missed Difference detection amplifying circuit (10), charge-domain phase error detection amplifying circuit (11), K charge-domain analog-digital converters (12), control Circuit (13) processed, ROM module (15), SRAM module (14), phase accumulator (16), the first delay circuit (17), phase amplitude Converter (18), the second delay circuit (19), compensation circuit (110) and N current-mode DAC (111)；
First, second input terminal of charge-domain phase error detection amplifying circuit (11) is connected respectively to N current-mode DAC (111) signal output difference port, the control signal of charge-domain phase error detection amplifying circuit (11) are connected to control First K option code output ports of circuit (13), the differential voltage output of charge-domain phase error detection amplifying circuit (11) End is connected to the differential voltage input terminal of K charge-domain analog-digital converters (12)；Charge-domain range error detects amplifying circuit (10) the first, second input terminal is connected respectively to the signal output difference port of N current-mode DAC (111), charge-domain amplitude The control signal of error-detecting amplifying circuit (10) is connected to the 2nd K option code output ports of control circuit (13), electricity The differential voltage output end of lotus domain range error detection amplifying circuit (10) is connected to the difference of K charge-domain analog-digital converters (12) Component voltage input terminal；The position the K quantization code of K charge-domain analog-digital converters (12) is output to the error input terminal of control circuit (13) Mouthful；
The ROM control port of control circuit (13) exports control signal and gives ROM module (15), the SRAM control of control circuit (13) Port exports control signal and gives SRAM module (14), and the first K delay code output ends of control circuit (13) are connected to first and prolong Second input port of slow circuit (17), the 2nd K delay code output ends of control circuit (13) are connected to the second delay circuit (19) the calibration control signal Ctrl output port of the second input port, control circuit (13) is connected to charge-domain phase simultaneously Error-detecting amplifying circuit (11), K charge-domain analog-digital converters (12), compensation circuit (110), the first delay circuit (17) with And second delay circuit (19) calibration control signal Ctrl input port；
First N calibration code output ends of first input port connection ROM module (15) of the first delay circuit (17), first prolongs The position the X phase controlling input code of third input port connection phase accumulator (16) of slow circuit (17), the first delay circuit (17) X hand over words are output to phase amplitude converter (18) by output port；First input of the second delay circuit (19) Port connects the 2nd N calibration code output ends of ROM module (15), and the third input port of the second delay circuit (19) connects phase The N position amplitude of position amplitude controller output controls input code, and the output port of the second delay circuit (19) exports N hand over words To compensation circuit (110)；3rd N calibration code outputs of first input port connection ROM module (15) of compensation circuit (110) End, the position the N hand over word of third input port connection the second delay circuit (19) output of compensation circuit (110), compensation circuit (110) N output codes are output to the data input pin of N current-mode DAC (111) by output port；Wherein, N is positive integer, K is the positive integer no more than N.
2. as described in claim 1 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that its Operating mode includes calibration mode and compensation model；And it is introduced into calibration mode in circuit work, enters compensation model afterwards； When entering calibration mode, X phase controlling input codes, N amplitudes control input codes, N output codes, the first K delay codes, 2nd K delay codes and K compensation codes are invalid, and the first N calibration codes are input to the first delay circuit (17), the 2nd N schools Quasi- code is input to the second delay circuit (19), and the 3rd N calibration codes are input to compensation circuit (110)；The charge-domain amplitude is missed Difference detection amplifying circuit (10) first carries out range error calibration to N current-mode DAC (111), and then the charge-domain phase is missed Difference detection amplifying circuit (11) successively carries out phase error school to N current-mode DAC (111) and phase amplitude converter (18) It is quasi-；When entering compensation model, X phase controlling input codes are input to the first delay circuit (17), and N amplitudes control input code It is input to the second delay circuit (19), N output codes are input to compensation circuit (110)；First N calibration codes, the 2nd N calibrations Code and the 3rd N calibration codes are invalid, and the first K delay codes, the 2nd K delay codes and K compensation codes are effective；The charge-domain width Degree error calibration circuit starts to carry out N current-mode DAC (111) range error compensation, the charge-domain phase error calibration Circuit carries out phase compensation to N current-mode DAC (111) and phase amplitude converter (18) simultaneously.
3. as claimed in claim 2 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that its When carrying out range error calibration to the N current-mode DAC (111), the job order of circuit is as follows:
Control circuit (13) controls charge-domain range error by Ctrl signal first and detects amplifying circuit (10), K charge-domains Analog-digital converter (12) and compensation circuit (110) enter calibration mode, while exporting the 2nd K option codes and missing to charge-domain amplitude Difference detection amplifying circuit (10)；
Then control circuit (13) generates first group of the 2nd K option code, while controlling ROM module (15) and generating first group of third N calibration codes；First group of the 3rd N calibration code enters compensation circuit (110) and obtains N output codes, N output codes enter to The position N current-mode DAC (111) circuit of calibration, obtains first group of range error corresponding with the 3rd N calibration codes through digital-to-analogue conversion Differential output current；Charge-domain range error detects amplifying circuit (10) and passes through first group of range error differential output current of detection Amount, and handle and obtain the first grouping error voltage；First grouping error voltage is carried out modulus and turned by K charge-domain analog-digital converters (12) It changes, available K quantization codes of first group of range error are simultaneously output to control circuit (13)；Control circuit (13) obtains reception K quantization codes of first group of range error are stored in SRAM module (14), complete the range error quantization under a kind of input condition；
And then, control circuit (13), which can generate second group of the 2nd K option code and control ROM module (15) simultaneously, generates second The 3rd N calibration codes of group, second group of the 3rd N calibration code enter compensation circuit (110) and obtain N output codes, N output codes Into the position N current-mode DAC (111) circuit to be calibrated, corresponding with second group of the 3rd N calibration code is obtained through digital-to-analogue conversion Two groups of range error differential output currents；Charge-domain range error detects amplifying circuit (10) by comparing second group of difference output Its difference is simultaneously amplified available second grouping error voltage by electric current and second group of reference voltage；K charge-domain moduluses turn Second grouping error voltage is carried out analog-to-digital conversion by parallel operation (12), and available K quantization codes of second group of range error are simultaneously output to Control circuit (13)；Reception is obtained K quantization codes of second group of range error and is stored in SRAM module (14) by control circuit (13) In, complete the range error quantization under second of input condition；
It recycles according to this, generates L when control circuit (13) generate the K option codes of L group the 2nd and control ROM module (15) simultaneously The 3rd N calibration codes of group, and obtain K quantization codes of L group range error, and after being stored in SRAM module (14), control electric The internal computing circuit in road (13) will calculate the K quantization codes of L group range error being stored in SRAM module (14) Obtain K compensation codes；K compensation codes can be output in compensation circuit (110) by control circuit (13) at this time, and by compensation circuit (110) it is arranged to compensate for mode, while keeping K compensation codes constant；So far, it completes to miss N current-mode DAC (111) amplitudes The calibration of difference；
Above-mentioned to carry out in range error calibration process to N current-mode DAC (111), control circuit (13) generates each simultaneously Group is output to the 3rd N calibration codes of compensation circuit (110) and is output to charge-domain range error detection amplifying circuit (10) 2nd K option codes must correspond, it may be assumed that the N calibration codes of J group the 3rd must make with the K option code cooperations of J group the 2nd With；Wherein, L is no more than 2KPositive integer；J is the positive integer no more than L.
4. as claimed in claim 2 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that its When carrying out phase error calibration to the N current-mode DAC (111) and phase amplitude converter (18), the job order of circuit It is as follows:
1, phase error calibration is carried out to N current-mode DAC (111) first:
1.1 control circuits (13) pass through Ctrl signal control charge-domain phase error detection amplifying circuit (11) and the second deferred telegram Road (19) enters calibration mode, while exporting the first K option codes to charge-domain phase error detection amplifying circuit (11), starts Phase error calibration is carried out to N current-mode DAC (111)；
1.2 then control circuit (13) generate first group of the first K option code, while control ROM module (15) generation first group 2nd N calibration codes；First group of the 2nd N calibration code enters the second delay circuit (19) and obtains N hand over words, N conversions Code enters N current-mode DAC (111) circuit to be calibrated, obtains corresponding with first group of the 2nd N calibration code the through digital-to-analogue conversion One group of phase error differential output current；Charge-domain phase error detection amplifying circuit (11) passes through first group of phase error of detection Differential output current amount, and handled to obtain first group of phase error voltage；K charge-domain analog-digital converters (12) are by first Group phase error voltage carries out analog-to-digital conversion, and available K quantization codes of first group of phase error are simultaneously output to control circuit (13)；Reception is obtained K quantization codes of first group of phase error and is stored in SRAM module (14) by control circuit (13), completes one The position N current-mode DAC (111) current phase error quantization under kind input condition；
1.3 and then, and control circuit (13) generates second group of the first K option code, while controlling ROM module (15) and generating second The 2nd N calibration codes of group；Second group of the 2nd N calibration code enters the second delay circuit (19) and obtains N hand over words, and N turn Escape enters the position N current-mode DAC (111) circuit to be calibrated, obtains through digital-to-analogue conversion corresponding with second group of the 2nd N calibration code Second group of phase error differential output current；Charge-domain phase error detection amplifying circuit (11) passes through second group of phase of detection Error differential output current amount, and handled to obtain second group of phase error voltage；K charge-domain analog-digital converters (12) will Second group of phase error voltage carries out analog-to-digital conversion, and available K quantization codes of second group of phase error are simultaneously output to control electricity Road (13)；Reception is obtained K quantization codes of second group of phase error and is stored in SRAM module (14) by control circuit (13), is completed N to be calibrated current-mode DAC (111) current phase error quantizations under two kinds of input conditions；
1.4 recycle according to this, when control circuit (13) generation N calibration codes of L group the 2nd and the K option codes of L group the first, and To K quantization codes of L group phase error, and after being stored in SRAM module (14), the internal computing circuit of control circuit (13) The K quantization codes of L group phase error being stored in K bit register group will be carried out that the 2nd K delay codes are calculated；Control 2nd K delay codes can be output in the second delay circuit (19) by circuit (13) at this time, and keep the 2nd K delay codes not Become, the second delay circuit (19) is arranged to compensate for mode by control circuit (13), completes the phase to N current-mode DAC (111) It calibrates for error；
2, later, control circuit (13) enters calibration mode by Ctrl signal control the first delay circuit (17), while exporting K Position option code starts to carry out phase error to phase amplitude converter (18) to charge-domain phase error detection amplifying circuit (11) Calibration；
Control circuit (13) controls ROM module (15) and generates the first N calibration codes, passes through the first delay circuit (17), charge-domain Phase error detection amplifying circuit (11) and K charge-domain analog-digital converters (12), using and to N current-mode DAC (111) Phase error calibrates identical step and method, obtains the first K delay codes and is output in the first delay circuit (17), simultaneously Keep the first K delay codes constant, the first delay circuit (17) is arranged to compensate for mode by control circuit (13), is completed to phase The phase error of amplitude converter (18) is calibrated；At this point, calibration mode terminates；
N current-mode DAC (111) and phase amplitude converter (18) are carried out in phase error calibration process above-mentioned, control Each group of the first N calibration codes and the 2nd N calibration codes and be output to the inspection of charge-domain phase error that circuit (13) generates simultaneously The first K option codes for surveying amplifying circuit (11) must correspond, it may be assumed that the N calibration codes of J group the first and the 2nd N calibrations Code must be used cooperatively with the K option codes of J group the first；Wherein, L is no more than 2KPositive integer, J be just no more than L Integer.
5. as described in claim 1 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that institute The charge-domain phase error detection amplifying circuit (11) stated includes: current sense resistor, reference clock generation circuit (21), phase demodulation Device (22), loop filter (23) and the first charge-domain voltage amplifier circuit (24)；The both ends of current sense resistor are separately connected To the first, second input terminal of charge-domain phase error detection amplifying circuit (11), and it is connected respectively to the of phase discriminator (22) One and second input terminal；Reference clock generation circuit (21) generates reference clock and is connected to mirror under the control of K option codes The third input terminal of phase device (22)；Phase discriminator (22) carries out further phase bit comparison to the signal of 3 input terminals and obtains phase Error signal；Phase error signal obtains voltage signal V by loop filter (23) filteringi；ViBy the first charge-domain voltage Amplifying circuit (24) amplification obtains error signal Vop and Von.
6. as described in claim 1 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that institute State charge-domain range error detection amplifying circuit (10) include: current sense resistor, reference data generation circuit (71), common mode not Sensitive high-speed switch capacitor differential voltage signal sampling network (72) and the second charge-domain voltage amplifier circuit (73)；Current detecting The both ends of resistance are connected respectively to the first and second input terminals of charge-domain range error detection amplifying circuit (10), and are connected to First and second input terminals of the insensitive high-speed switch capacitor differential voltage signal sampling network (72) of common mode；Reference data generates Circuit (71) generates differential reference voltage output under the control of K option codes, and is connected to the insensitive high-speed switch electricity of common mode Third and fourth input terminal of tolerance divided voltage signal sampling network (72)；Switching capacity differential voltage signal sampling network is to 4 The voltage signal of a input terminal is further sampled, and differential voltage signal V is obtainedi+ and Vi-；By the second charge-domain voltage Amplifying circuit (73) amplification obtains error signal Vop and Von.
7. as described in claim 1 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that institute The position the K charge-domain analog-digital converter (12) stated includes: the P grades of assembly line grade circuits based on charge-domain signal processing technology, Analog-to-digital conversions and surplus amplification are completed for carrying out various processing to the obtained charge packet of sampling, and by each height grade circuit Output digital code is input to delay SYN register, and the charge packet of each height grade circuit output enters next stage, each Sub- grade circuit repeats the same course of work；P+1 grades and afterbody A-bit Flash analog-digital converter circuit, will The P grades of charge packets transmitted are re-converted into voltage signal, and carry out the analog-to-digital conversion work of afterbody, and by the same level The output digital code of circuit is input to delay SYN register, this grade of circuit only completes analog-to-digital conversion, amplifies without surplus；Prolong When SYN register, be used to carry out delay alignment to the digital code of each sub- pipelining-stage output, and the digital code of alignment is defeated Enter to figure adjustment module；Digital correction circuit module is used to receive the output digital code of SYN register, by received number Character code carries out shifter-adder, to obtain the R bit digital output code of analog-digital converter；Wherein, R is positive integer, and P and A are little In the positive integer of R.
8. as described in claim 1 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that institute It states the first delay circuit (17) and the second delay circuit (19) is all made of identical delay circuit, structure includes: N number of delay buffering Unit and N number of K delay time register；Wherein, the first K delay time registers~delay time register of n-th K delay code inputs End is all connected to K delay codes, and control signal input is all connected to Ctrl signal；First delay buffer cell~N The delay code input terminal of delay buffer cell is connected respectively to the first K delay time registers~delay time register of n-th K and prolongs Slow code output end, the first delay buffer cell~N delay buffer cell data output end are connected respectively to the 1st hand over word ~the N hand over word simultaneously exports, and the first delay buffer cell~N delay buffer cell first control signal input terminal is whole It is connected to Ctrln signal, the first delay buffer cell~N delay buffer cell second control signal input terminal all connects To Ctrl signal；Wherein, Ctrl and Ctrln is one group of reverse signal.
9. as claimed in claim 8 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that institute Stating inside compensation circuit (110) includes: delay buffer circuit and K add circuits, and be delayed buffer circuit and K additions it is electric The delay on road must be equal；Compensation circuit (110) can operate at two kinds of the mode of being calibrated and compensated under the control of Ctrl signal Mode；
When in the calibration mode, Ctrl signal is effective, and the output of K add circuits will be invalid, and the 3rd N calibration codes are slow through being delayed N output codes are obtained after rushing circuit and are exported；
When in the compensation mode, Ctrln signal is effective, and the output of K add circuits will be effective, and N-K hand over words are slow through being delayed N-K output codes are obtained after rushing circuit and are exported, and K hand over words are added to obtain K with K compensation codes by K add circuits Output code simultaneously exports.
10. as described in claim 1 with the low-power consumption DDS circuit of amplitude and phase error auto-correction function, characterized in that institute Stating control circuit (13) includes: core control circuit, ROM reading circuit, the first delay code generation circuit, the second delay code generation Circuit, compensation codes generation circuit, option code generation circuit, computing circuit, SRAM read/write circuit and K bit register；
The connection relationship of foregoing circuit are as follows: the first output end of core control circuit is connected to the input terminal of ROM reading circuit, core The second output terminal of heart control circuit is connected to the control signal of the first delay code generation circuit, the third of core control circuit Output end is connected to the control signal of the second delay code generation circuit, and the 4th output end of core control circuit is connected to compensation The control signal of code generation circuit, the 5th output end of core control circuit are connected to the control signal of computing circuit, core 6th output end of heart control circuit is connected to the control signal of option code generation circuit, the 7th output of core control circuit End generates calibration control signal Ctrl, and the 8th output end of core control circuit is connected to K bit register and SRAM read-write simultaneously The control signal of circuit, the input terminal of core control circuit are connected to calibration starting control signal；ROM reading circuit is according to core The control instruction of heart control circuit generates ROM address code；The data input pin of computing circuit receives SRAM read/write circuit output end The data of transmission, and the first K error codes, the 2nd K error codes and the 3rd K are generated according to the control instruction of core control circuit Position error codes；The data input pin of first delay code generation circuit receives the first K mistakes that computing circuit data output end is sent Poor code, and the first K delay codes are generated according to the control instruction of core control circuit；The data of second delay code generation circuit are defeated Enter end and receive the 2nd K error codes that computing circuit data output end is sent, and is produced according to the control instruction of core control circuit Raw 2nd K delay codes；The data input pin of compensation codes generation circuit receive that computing circuit data output end sends the 3rd K Error codes, and K compensation codes are generated according to the control instruction of core control circuit；Option code generation circuit controls electricity according to core The control instruction on road generates the first K option codes and the 2nd K option codes；The data input pin of K bit register receives described K The position the K quantization code that the output end of charge-domain analog-digital converter (12) is sent, and will be deposited according to the control instruction of core control circuit The data of storage inside it are sent to SRAM read/write circuit；SRAM read/write circuit is generated according to the control instruction of core control circuit SRAM address date code carries out reading data and write-in to SRAM module (14).
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