CN109462402A - Mixed type pipelined ADC architecture - Google Patents
Mixed type pipelined ADC architecture Download PDFInfo
- Publication number
- CN109462402A CN109462402A CN201811241098.4A CN201811241098A CN109462402A CN 109462402 A CN109462402 A CN 109462402A CN 201811241098 A CN201811241098 A CN 201811241098A CN 109462402 A CN109462402 A CN 109462402A
- Authority
- CN
- China
- Prior art keywords
- time
- domain
- zero
- mdac
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a kind of mixed type pipelined ADC architecture, including 1 tradition, 4 MDAC, 1 zero-crossing comparator, 5 incorporation time domain quantizers, 1 digital calibration blocks；The MDAC output end is connect with zero-crossing comparator, the zero-crossing comparator output end is sequentially connected 5 incorporation time domain quantizers, the output end of 5 incorporation time domain quantizers is connect with the input terminal of digital calibration block respectively, and the digital calibration block output end is bi-directionally connected with MDAC input terminal.1st grade of MDAC(times of multiplier mode converter of the invention) what is inputted is voltage signal, carries out Voltage-time conversion by zero-crossing comparator, so that output is time pulse signal, rear class uses time-domain quantizer.Incorporation time domain quantizer is designed, which is replaced the DAC of time-domain using 1 capacitor DAC, can reduce clock jitter error.
Description
Technical field
The invention belongs to production line analog-digital converter technical field, specially a kind of novel mixed type pipelined ADC architecture.
Background technique
More stringent requirements are proposed for performance of the high speed development of Modern Communication System to ADC.In wireless communications, it usually needs
The ADC of high linearity and high dynamic range is wanted, to provide sufficiently high no clutter dynamic range and signal noise harmonic distortion ratio.
The raising of communication system speed is so that data volume to be treated is continuously increased in the unit time, so that the speed to ADC proposes
Higher requirement.The fast development of PCS Personal Communications System and all kinds of portable consumer electronics products, needs the power consumption of ADC into one
Step reduces.
Pipeline ADC uses surplus amplifier and how sub- grade tandem working mode with high-gain, so having both high-precision
The characteristics of degree and high speed, becomes the hot spot of converter art research.Surplus amplifier in conventional pipeline grade has
The characteristics such as high-gain high linearity can make ADC obtain higher precision and lesser nonlinearity erron.But by amplifier and switch electricity
Hold the traditional surplus amplifier constituted, circuit somewhat complex design difficulty is high, and can generate biggish power consumption.Especially in low power supply electricity
Pressure, surplus amplifier are more difficult to realize the compromise between low-power consumption and high-precision.
Be suggested based on the modulus conversion technique of time-domain in 2008, and this technology for pipeline ADC be then
2014, the advantages of which combines with the structure of conventional pipeline by the converter based on time-domain, absorb two kinds of structures,
The analog-to-digital conversion of high-precision high-speed is realized with lower power consumption.But as a kind of new ADC structure, it is based on time-domain
Pipeline ADC need to solve two critical issues: 1, when realizing the analog-to-digital conversion of degree of precision, the sub- grade of assembly line compared with
It is more, it is not easy to further decrease power consumption.2, the 1st grade of MDAC(times of multiplier mode converter of the pipeline ADC based on time-domain) usually adopt
Surplus amplifier between grade is realized with the high performance amplifier of closed loop, can obtain accurate gain and lesser non-linear mistake
Difference still can generate biggish power consumption in this way.But if being amplified using the lower surplus of the relatively simple open-loop gain of structure
Device, limited open-loop gain and nonlinearity erron can make surplus curve deviate ideal characterisitics, to influence conversion accuracy.
Summary of the invention
Object of the present invention is to propose a kind of novel mixed type pipelined ADC architecture, it will have both time-domain and voltage domain turns
The characteristics of parallel operation and advantage reach the parameter request of high-precision and low-power consumption.
In order to achieve the above object, adopted by the present invention the specific technical proposal is:
A kind of mixed type pipelined ADC architecture, including 1 tradition, 4 MDAC(times of multiplier mode converters), 1 zero-crossing comparator,
5 incorporation time domain quantizers, 1 digital calibration block.Other supplementary modules include voltage and current benchmark, clock module, number
Word output module etc..
The MDAC output end is connect with zero-crossing comparator, when the zero-crossing comparator output end is sequentially connected 5 mixing
Between domain quantizer, the output end of 5 incorporation time domain quantizers connect with the input terminal of digital calibration block respectively, the number
Calibration module output end is bi-directionally connected with MDAC input terminal.
Structure of the invention uses the 1st grade of assembly line MDAC times of multiplier mode converter of voltage domain), rear class uses the time
Domain quantizer.1st grade of MDAC(times of multiplier mode converter) what is inputted is voltage signal, the output of the 1st grade of MDAC passes through zero passage ratio
Carry out Voltage-time conversion compared with device so that the output of the 1st grade of MDAC is time pulse signal, rear class time-domain quantizer when
Between domain work.Wherein, Voltage-time conversion process needs 3 clock phases, and sampling and feedback capacity are discharged simultaneously.Electricity
In pressure-time conversion process, outputT O Be it is linear, do not influenced by amplifier parameter.Rear class is using 5 incorporation time domain amounts
Change device, can reduce clock jitter error, after zero-acrross ing moment, the time margin output of amplification is transferred to next stage.Rear class
Time-domain quantizer the DAC of time-domain is replaced using 1 capacitor DAC, can reduce clock jitter error.
The present invention has rational design, specific practical application and promotional value well.
Detailed description of the invention
Fig. 1 shows the utility model mixed type pipelined ADC architectures.
Fig. 2 indicates the Voltage-time conversion process in the utility model mixed type pipelined ADC architecture.
Fig. 3 indicates the incorporation time domain quantizer in the utility model mixed type pipelined ADC architecture.
Fig. 4 indicates the course of work of the incorporation time domain quantizer in the utility model mixed type pipelined ADC architecture.
Specific embodiment
Specific embodiments of the present invention are described in detail with reference to the accompanying drawing.
A kind of mixed type pipelined ADC architecture, as shown in Figure 1, including 1 tradition, 4 MDAC, 1 zero-crossing comparator, 5
A incorporation time domain quantizer, 1 digital calibration block.Other supplementary modules include voltage and current benchmark, clock module, number
Output module etc..Wherein, MDAC output end is connect with zero-crossing comparator, when zero-crossing comparator output end is sequentially connected 5 mixing
Between domain quantizer, the output end of 5 incorporation time domain quantizers connect with the input terminal of digital calibration block respectively, digital calibration
Module output end is bi-directionally connected with MDAC input terminal.
The sub- grade of conventional pipeline is more, is not easy to further decrease power consumption.This structure by assembly line in addition to the 1st grade after
Grade replaces conventional pipeline grade using the converter grade based on time-domain, can reduce under the premise of not reducing precision
The power consumption of ADC.The structure of design time quantizer can reduce clock jitter error using incorporation time domain quantizer.
After the signal of input mixed production line ADC passes through sampling hold circuit first, the 1st grade of MDAC(times of multiplier is inputted
Mode converter), inputting MDAC is voltage signal.MDAC can amplify the voltage signal of input, then pass through Zero-cross comparator
Device carries out Voltage-time conversion, so that the signal of input rear class is time-domain signal.The signal of input time quantizer 1 is to put
Time-domain signal after big, is analog signals, time quantization device 1 can be AD converted the analog signals of input, can
To generate the output of 2.5 bit digitals, the analog signal of the analog signal and input time quantizer 1 do not converted passes through comparator
Carry out surplus amplification, the input as rear class.The signal of input time quantizer 2 is the time-domain analog quantity after surplus amplification
Signal carries out the course of work same as time quantization device 1 again.The numeral output of each time quantization device, passes through digital school
The digital signal of quasi-mode block output then obtains the whole number signal after total input analog signal conversion.
Fig. 2 is Voltage-time conversion process in this structure.This conversion process needs 3 clock phases, sampling and feedback
Capacitor discharges simultaneously.Because there is no charge on two capacitors, in the case where the linear characteristic of current source is met the requirements,
In zero passage, the output of time-domain is always linear, without considering the non-ideal characteristic of amplifier.The output of time-domain is being discharged
The zero-acrross ing moment of time phase is unrelated with the parameter of amplifier, so in the conversion process of this voltage-vs-time, it is defeated
OutT O Be it is linear, do not influenced by amplifier parameter.In zero passage detection, time domain output signal with amplifier error without
It closes, so 1 nonlinear amplifier of low gain can be used during Voltage-time conversion.
Fig. 3 is incorporation time domain quantizer.The charge subtraction of the quantizer is completed using 1 capacitor DAC.In this structure
The linearity of DAC is only determined by the matching of capacitor, is relatively easy to realize.The time-domains such as the mismatch of time jitter and delay cell
Error can only influence the linearity of sub- TDC, have no influence for the surplus between grade.
Fig. 4 is the course of work of incorporation time domain quantizer.Firstly, all capacitors are reset to reference voltage.?
Charge phase, the electric current charging that capacitor is inputted based on the time.At this moment, sub- TDC quantization time is inputted and is generated corresponding
Hot code output.In next clock phase, the charge (indicating surplus) being stored on capacitor is discharged simultaneously by current source I
Carry out surplus amplification.After zero-acrross ing moment, the time margin input of amplification is transferred to next stage.
It should be pointed out that for the those skilled in the art of the art, without departing from the principle of the present invention,
Several improvement and application can also be made, these are improved and application is also considered as protection scope of the present invention.
Claims (3)
1. a kind of mixed type pipelined ADC architecture, it is characterised in that: including 1 tradition, 4 MDAC, 1 zero-crossing comparator, 5
Incorporation time domain quantizer, 1 digital calibration block；
The MDAC output end is connect with zero-crossing comparator, and the zero-crossing comparator output end is sequentially connected 5 incorporation time domains
The output end of quantizer, 5 incorporation time domain quantizers is connect with the input terminal of digital calibration block respectively, the digital calibration
Module output end is bi-directionally connected with MDAC input terminal.
2. mixed type pipelined ADC architecture according to claim 1, it is characterised in that: carried out in the zero-crossing comparator
Voltage-time conversion process uses 3 clock phases, and sampling and feedback capacity are discharged simultaneously.
3. mixed type pipelined ADC architecture according to claim 1, it is characterised in that: the time-domain quantizer uses 1
A capacitor DAC replaces the DAC of time-domain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811241098.4A CN109462402B (en) | 2018-10-24 | 2018-10-24 | Mixed type assembly line ADC structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811241098.4A CN109462402B (en) | 2018-10-24 | 2018-10-24 | Mixed type assembly line ADC structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109462402A true CN109462402A (en) | 2019-03-12 |
| CN109462402B CN109462402B (en) | 2022-08-16 |
Family
ID=65608272
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811241098.4A Active CN109462402B (en) | 2018-10-24 | 2018-10-24 | Mixed type assembly line ADC structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109462402B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110401447A (en) * | 2019-06-10 | 2019-11-01 | 西安电子科技大学 | A kind of no amplifier MDAC type time-domain ADC structure |
| CN112600559A (en) * | 2020-12-02 | 2021-04-02 | 深圳市国微电子有限公司 | Pipeline analog-to-digital converter and transceiving chip |
| CN113114248A (en) * | 2021-05-11 | 2021-07-13 | 成都信息工程大学 | Self-calibration pipeline ADC |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635937A (en) * | 1993-12-31 | 1997-06-03 | Korea Academy Of Industrial Technology | Pipelined multi-stage analog-to-digital converter |
| US20100039302A1 (en) * | 2008-08-12 | 2010-02-18 | Analog Devices, Inc. | Correlation-based background calibration of pipelined converters with reduced power penalty |
| CN102386921A (en) * | 2011-11-15 | 2012-03-21 | 北京时代民芯科技有限公司 | Mismatch calibration method for streamline ADC (Analog-to-Digital Converter) multi-bit sub DAC (Digital-to0Analog Converter) capacitor |
| US20120146820A1 (en) * | 2010-12-09 | 2012-06-14 | Electronics And Telecommunications Research Institute | Pipelined analog digital convertor |
| CN104283560A (en) * | 2014-10-15 | 2015-01-14 | 朱从益 | Clock skew calibrating circuit of sampling-and-holding-amplifier-free assembly line ADC and control method of clock skew calibrating circuit of sampling-and-holding-amplifier-free assembly line ADC |
| CN104702282A (en) * | 2015-04-03 | 2015-06-10 | 中国电子科技集团公司第十四研究所 | Digital calibration method and circuit for multi-stage multi-bit sub circuit in analog-digital converters |
-
2018
- 2018-10-24 CN CN201811241098.4A patent/CN109462402B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5635937A (en) * | 1993-12-31 | 1997-06-03 | Korea Academy Of Industrial Technology | Pipelined multi-stage analog-to-digital converter |
| US20100039302A1 (en) * | 2008-08-12 | 2010-02-18 | Analog Devices, Inc. | Correlation-based background calibration of pipelined converters with reduced power penalty |
| US20120146820A1 (en) * | 2010-12-09 | 2012-06-14 | Electronics And Telecommunications Research Institute | Pipelined analog digital convertor |
| CN102386921A (en) * | 2011-11-15 | 2012-03-21 | 北京时代民芯科技有限公司 | Mismatch calibration method for streamline ADC (Analog-to-Digital Converter) multi-bit sub DAC (Digital-to0Analog Converter) capacitor |
| CN104283560A (en) * | 2014-10-15 | 2015-01-14 | 朱从益 | Clock skew calibrating circuit of sampling-and-holding-amplifier-free assembly line ADC and control method of clock skew calibrating circuit of sampling-and-holding-amplifier-free assembly line ADC |
| CN104702282A (en) * | 2015-04-03 | 2015-06-10 | 中国电子科技集团公司第十四研究所 | Digital calibration method and circuit for multi-stage multi-bit sub circuit in analog-digital converters |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110401447A (en) * | 2019-06-10 | 2019-11-01 | 西安电子科技大学 | A kind of no amplifier MDAC type time-domain ADC structure |
| CN112600559A (en) * | 2020-12-02 | 2021-04-02 | 深圳市国微电子有限公司 | Pipeline analog-to-digital converter and transceiving chip |
| CN112600559B (en) * | 2020-12-02 | 2024-03-19 | 深圳市国微电子有限公司 | Pipelined analog-to-digital converter and transceiver chip |
| CN113114248A (en) * | 2021-05-11 | 2021-07-13 | 成都信息工程大学 | Self-calibration pipeline ADC |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109462402B (en) | 2022-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107395206B (en) | Successive approximation type digital-to-analog converter with feedback advance setting and corresponding Delta-SigmaADC framework | |
| CN103762982B (en) | Capacitance mismatch fast calibrating circuit of analog-digital converter and calibrating method | |
| CN109787633B (en) | Sigma delta ADC with chopper stabilization suitable for hybrid ADC structure | |
| CN104158545B (en) | A kind of successive approximation register pattern number converter quantified based on voltage controlled oscillator | |
| CN102545901B (en) | Second-order feedforward Sigma-Delta modulator based on successive comparison quantizer | |
| CN109462402A (en) | Mixed type pipelined ADC architecture | |
| CN101277112A (en) | Low-power consumption assembly line a/d converter by sharing operation amplifier | |
| CN108322199B (en) | Dynamic comparison method | |
| CN106953637B (en) | Charge domain amplitude error calibration circuit and DDS circuit adopting same | |
| CN104168025B (en) | A kind of charge type streamline gradual approaching A/D converter | |
| CN109861691A (en) | The analog-digital converter circuit of two-step mixed structure SAR TDC based on delay phase-locked loop | |
| CN104506196A (en) | High-speed high-precision two-step type analog-digital converter | |
| CN104124969A (en) | Pipelined analog-to-digital converter | |
| CN104184478B (en) | Complementary cascade phase inverter and increment Sigma Delta analog to digital conversion circuits | |
| CN110401447A (en) | A kind of no amplifier MDAC type time-domain ADC structure | |
| CN104283566B (en) | For the comparison circuit of analog-digital converter | |
| CN103312334B (en) | Be applicable to the integrator circuit of Sigma-Delta adc circuit | |
| CN101980446B (en) | High-performance low-power consumption pipeline analogue-to-digital converter | |
| CN104702282A (en) | Digital calibration method and circuit for multi-stage multi-bit sub circuit in analog-digital converters | |
| CN104980159A (en) | Charge pump and voltage controlled-oscillator-based oversampling analog-digital converter | |
| CN101471665B (en) | D/A converter circuit employing multistage amplifier part multiplexing technology | |
| CN104682958A (en) | Noise-shaping flash successive approximation register analog-to-digital converter (Noise-Shaping Flash-SAR ADC) | |
| CN104348489B (en) | Feed forward type triangular integration modulator | |
| CN104753533A (en) | Staged shared double-channel assembly line type analog to digital converter | |
| CN103152048B (en) | A kind of Differential Input successive approximation analog digital conversion method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |