CN106933299A - Low-power consumption DDS circuit with amplitude and phase error self-calibration function - Google Patents

Abstract

The present invention provides a low-power DDS circuit with amplitude and phase error self-calibration functions. The DDS circuit includes: a charge domain amplitude error detection amplifier circuit, a charge domain phase error detection amplifier circuit, and a K-bit charge domain analog-to-digital converter , a control circuit, a ROM module, an SRAM module, a phase accumulator, a first delay circuit, a phase amplitude converter, a second delay circuit, a compensation circuit and an N-bit current modulus DAC. The low-power DDS circuit with amplitude and phase error self-calibration function can automatically trade off the calibration precision according to system precision and hardware overhead, and has the characteristics of low power consumption.

Description

Low-power DDS circuit with amplitude and phase error self-calibration function

technical field

The invention relates to an error calibration circuit, in particular to a low-power DDS circuit with amplitude and phase error self-calibration functions.

Background technique

Direct digital frequency synthesis technology is a technology that synthesizes signals of various frequencies required by digital means, and finally converts them into analog signal output through a digital-to-analog converter. This technology has become one of the main technologies in today's frequency synthesis technology due to its unique characteristics: programmable, fast frequency hopping, high resolution, high frequency modulation accuracy, etc. It is widely used in mobile communications, military and commercial radar systems and other communication fields .

A direct digital frequency synthesizer (DDS) is mainly composed of three modules: a phase accumulator, a phase-to-magnitude converter, and a digital-to-analog converter (DAC). The whole DDS system usually has two input quantities: reference clock fs and frequency control word X. Under the control of the clock, the phase accumulator continuously performs linear phase accumulation on the frequency control word when each clock pulse is input. The data output by the phase accumulator is the phase of the synthesized signal, and the output frequency of the phase accumulator is also the signal frequency output by the direct digital frequency synthesizer. The phase value output by the intercepting accumulator is input into the phase-magnitude converter, and the digitized amplitude value corresponding to the phase value is output through operation conversion. The digital quantity is converted into an analog quantity through a digital-to-analog converter, and then the undesired sampling signal is smoothed and filtered out by a low-pass filter, and a sine or cosine signal with a pure frequency is output.

From the working principle of DDS, we can see that the influence of factors such as the non-ideal characteristics of the clock, the asynchronous DAC input signal, the asynchronous timing of the internal modules of the DAC, the possible signal crosstalk in the power supply and circuit design, etc., will cause the output signal of the DAC to exist. magnitude and phase error. In practical applications, due to fluctuations in processing technology and changes in the working environment, there will also be some randomness in the DDS amplitude and phase errors. The specific performance is that the amplitude and phase errors of different DDS chips are not the same. In applications such as phased radar that require precise control of DDS amplitude and phase error consistency, the problems caused by the inconsistency of amplitude and phase errors between DDS chips will make the DDS chips unable to meet the accuracy requirements. Therefore, it is of practical significance to design a self-calibration circuit of high-precision amplitude and phase error integrated in the DDS chip.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, and provide a low-power DDS circuit with amplitude and phase error self-calibration function, which integrates high-precision amplitude and phase error self-calibration circuit inside.

The object of the present invention can be achieved through the following technical solutions, the described low-power DDS circuit with amplitude and phase error self-calibration function, its structure includes: charge domain amplitude error detection amplifier circuit, charge domain phase error detection amplifier circuit, K A bit charge domain analog-to-digital converter, a control circuit, a ROM module, an SRAM module, a phase accumulator, a first delay circuit, a phase amplitude converter, a second delay circuit, a compensation circuit and an N-bit current modulo DAC;

The first and second input ends of the charge domain phase error detection amplifier circuit are respectively connected to the signal output differential port of the N-bit current mode DAC, and the control input end of the charge domain phase error detection amplifier circuit is connected to the first K-bit selector of the control circuit The code output port, the differential voltage output terminal of the charge domain phase error detection amplifier circuit is connected to the differential voltage input terminal of the K-bit charge domain analog-to-digital converter; the first and second input terminals of the charge domain amplitude error detection amplifier circuit are respectively connected to The signal output differential port of the N-bit current mode DAC, the control input end of the charge domain amplitude error detection amplifier circuit is connected to the second K bit selection code output port of the control circuit, and the differential voltage output end of the charge domain amplitude error detection amplifier circuit is connected to The differential voltage input terminal of the K-bit charge domain analog-to-digital converter; the K-bit quantization code of the K-bit charge domain analog-to-digital converter is output to the error input port of the control circuit;

The ROM control port of the control circuit outputs the control signal to the ROM module, the SRAM control port of the control circuit outputs the control signal to the SRAM module, and the first K-bit delay code output end of the control circuit is connected to the second input port of the first delay circuit to control The second K-bit delay code output end of the circuit is connected to the second input port of the second delay circuit, and the calibration control signal Ctrl output port of the control circuit is simultaneously connected to the charge domain phase error detection amplifying circuit, the K-bit charge domain analog-to-digital converter , the calibration control signal Ctrl input port of the compensation circuit, the first delay circuit and the second delay circuit;

The first input port of the first delay circuit is connected to the first N-bit calibration code output end of the ROM module, the third input port of the first delay circuit is connected to the X-bit phase control input code of the phase accumulator, and the output port of the first delay circuit Output the X-bit conversion code to the phase-amplitude converter; the first input port of the second delay circuit is connected to the second N-bit calibration code output end of the ROM module, and the third input port of the second delay circuit is connected to the output terminal of the phase-amplitude controller. N-bit amplitude control input code, the output port of the second delay circuit outputs the N-bit conversion code to the compensation circuit; the first input port of the compensation circuit is connected to the third N-bit calibration code output end of the ROM module, and the third input of the compensation circuit The port is connected to the N-bit conversion code output by the second delay circuit, and the output port of the compensation circuit outputs the N-bit output code to the data input terminal of the N-bit current modulo DAC; wherein, N is a positive integer, and K is a positive integer not greater than N .

Described low power consumption DDS circuit with amplitude and phase error self-calibration function, its mode of operation includes calibration mode and compensation mode; Bit control input code, N-bit amplitude control input code, N-bit output code, first K-bit delay code, second K-bit delay code and K-bit compensation code are all invalid, and the first N-bit calibration code is input to the first delay circuit , the second N-bit calibration code is input to the second delay circuit, and the third N-bit calibration code is input to the compensation circuit; the charge domain amplitude error calibration circuit first performs amplitude error calibration on the N-bit current mode DAC, and then the charge domain The phase error calibration circuit sequentially performs phase error calibration on the N-bit current mode DAC and the phase-amplitude converter; when entering the compensation mode, the X-bit phase control input code is input to the first delay circuit, and the N-bit amplitude control input code is input to the second delay circuit. Delay circuit, the N-bit output code is input to the compensation circuit; the first N-bit calibration code, the second N-bit calibration code and the third N-bit calibration code are invalid, and the first K-bit delay code, the second K-bit delay code and the K-bit The compensation code is valid; the charge domain amplitude error calibration circuit starts to perform amplitude error compensation on the N-bit current mode DAC, and the charge domain phase error calibration circuit simultaneously performs phase compensation on the N-bit current mode DAC and the phase-to-amplitude converter.

The low-power DDS circuit with amplitude and phase error self-calibration function, when it performs amplitude error calibration to the N-bit current mode DAC, the working order of the circuit is as follows:

The control circuit first controls the charge domain amplitude error detection amplifying circuit, the K-bit charge domain analog-to-digital converter and the compensation circuit to enter the calibration mode through the Ctrl signal, and simultaneously outputs the second K-bit selection code to the charge domain amplitude error detection amplifying circuit;

Then the control circuit generates the first group of second K-bit selection codes, and at the same time controls the ROM module to generate the first group of third N-bit calibration codes; the first group of third N-bit calibration codes enters the compensation circuit and obtains N-bit output codes, N-bit The output code enters the N-bit current mode DAC circuit to be calibrated, and the first group of amplitude error differential output current corresponding to the third N-bit calibration code is obtained through digital-to-analog conversion; the charge domain amplitude error detection amplifier circuit detects the first group of amplitude errors Differential output current, and processing to obtain the first set of error voltages; K-bit charge domain analog-to-digital converter performs analog-digital conversion on the first set of error voltages to obtain the first set of amplitude error K-bit quantization codes and output them to the control circuit; The control circuit stores the received first group of amplitude error K-bit quantization codes in the SRAM module, and completes the amplitude error quantization under one input condition;

Next, the control circuit will generate the second group of the second K-bit selection code and at the same time control the ROM module to generate the second group of the third N-bit calibration code, the second group of the third N-bit calibration code enters the compensation circuit and obtains the N-bit output code , the N-bit output code enters the N-bit current mode DAC circuit to be calibrated, and the second group of amplitude error differential output current corresponding to the second group of the third N-bit calibration code is obtained through digital-to-analog conversion; the charge domain amplitude error detection amplifier circuit passes Comparing the second group of differential output currents with the second group of reference voltages and amplifying the difference can obtain the second group of error voltages; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the second group of error voltages to obtain the second group of error voltages The two sets of amplitude error K-bit quantization codes are output to the control circuit; the control circuit stores the received second set of amplitude error K-bit quantization codes in the SRAM module to complete the amplitude error quantization under the second input condition;

In this cycle, when the control circuit generates the second K-bit selection code of the L group and at the same time controls the ROM module to generate the third N-bit calibration code of the L group, and obtains the K-bit quantization code of the L group amplitude error, and stores it in the SRAM module After the middle, the operation circuit inside the control circuit will calculate the K-bit quantization code of the L group amplitude error stored in the SRAM module to obtain the K-bit compensation code; the control circuit will output the K-bit compensation code to the compensation circuit at this time, And set the compensation circuit to the compensation mode, while keeping the K-bit compensation code unchanged; so far, the calibration of the N-bit current mode DAC amplitude error is completed;

In the above calibration process, each group of the third N-bit calibration code output to the compensation circuit simultaneously generated by the control circuit and the second K-bit selection code output to the charge domain amplitude error detection amplifier circuit must correspond one-to-one, that is: The third N-bit calibration code of the group must be used in conjunction with the second K-bit selection code of the J-th group; where, L is a positive integer not greater than ^2K ; J is a positive integer not greater than L.

Described low power consumption DDS circuit with amplitude and phase error self-calibration function, when it carries out phase error calibration to described N-bit current modulus DAC and phase-amplitude converter, the operating sequence of the circuit is as follows:

1. First, perform phase error calibration on the N-bit current mode DAC:

1.1 The control circuit controls the charge domain phase error detection amplifier circuit and the second delay circuit to enter the calibration mode through the Ctrl signal, and at the same time outputs the first K-bit selection code to the charge domain phase error detection amplifier circuit, and starts to perform phase error on the N-bit current mode DAC. calibration;

1.2 Then the control circuit generates the first group of first K-bit selection codes, and at the same time controls the ROM module to generate the first group of second N-bit calibration codes; the first group of second N-bit calibration codes enters the second delay circuit and obtains N-bit conversion codes , the N-bit conversion code enters the N-bit current mode DAC circuit to be calibrated, and the first group of phase error differential output current corresponding to the first group of the second N-bit calibration code is obtained through digital-to-analog conversion; the charge domain phase error detection amplifier circuit passes the detection The first group of phase error differential output currents are processed to obtain the first group of phase error voltages; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the first group of phase error voltages to obtain the first group of phase error K bits The quantization code is output to the control circuit; the control circuit stores the received first group of phase error K-bit quantization codes in the SRAM module, and completes the N-bit current mode DAC circuit phase error quantization under an input condition;

1.3 Immediately afterwards, the control circuit generates a second group of first K-bit selection codes, and at the same time controls the ROM module to generate a second group of second N-bit calibration codes; the second group of second N-bit calibration codes enters the second delay circuit and obtains N-bit The conversion code, the N-bit conversion code enters the N-bit current mode DAC circuit to be calibrated, and the second group of phase error differential output current corresponding to the second group of the second N-bit calibration code is obtained through digital-to-analog conversion; the charge domain phase error detection amplification The circuit detects the second group of phase error differential output currents and processes them to obtain the second group of phase error voltages; the K-bit charge domain analog-to-digital converter performs analog-to-digital conversion on the second group of phase error voltages to obtain the second group of phase errors The error K-bit quantization code is output to the control circuit; the control circuit stores the received second group of phase error K-bit quantization codes in the SRAM module, and completes the phase error quantization of the N-bit current mode DAC circuit to be calibrated under the two input conditions;

1.4 In this way, when the control circuit generates the second N-bit calibration code of the L group and the first K-bit selection code of the L group, and obtains the K-bit quantization code of the L group phase error, and stores it in the SRAM module, the control The arithmetic circuit inside the circuit will calculate the K-bit quantization code of the L group phase error stored in the K-bit register group to obtain the second K-bit delay code; the control circuit will output the second K-bit delay code to the second In the delay circuit, and keeping the second K-bit delay code unchanged, the control circuit sets the second delay circuit to a compensation mode to complete the phase error calibration of the N-bit current mode DAC;

2. After that, the control circuit controls the first delay circuit to enter the calibration mode through the Ctrl signal, and at the same time outputs the K-bit selection code to the charge domain phase error detection amplifier circuit, and starts to perform phase error calibration on the phase amplitude converter;

The control circuit controls the ROM module to generate the first N-bit calibration code, through the first delay circuit, the charge domain phase error detection amplifier circuit and the K-bit charge domain analog-to-digital converter, the same phase error calibration as the N-bit current mode DAC is used. Steps and methods, obtain the first K-bit delay code and output it to the first delay circuit, while keeping the first K-bit delay code unchanged, the control circuit sets the first delay circuit to compensation mode, and completes the phase-to-magnitude converter Phase error calibration; at this point, the calibration mode ends;

In the above-mentioned phase error calibration process, each group of first N-bit calibration codes and second N-bit calibration codes simultaneously generated by the control circuit must correspond to the first K-bit selection code output to the charge domain phase error detection amplifier circuit. , that is: the first N-digit calibration code and the second N-digit calibration code of the J-th group must be used in conjunction with the first K-bit selection code of the J-th group; where, L is a positive integer not greater than 2 ^K , and J is not greater than A positive integer of L.

Further, in the low-power DDS circuit with amplitude and phase error self-calibration function, the charge domain phase error detection amplifier circuit includes: current detection resistor, reference clock generation circuit, phase detector, loop filter and a first charge domain voltage amplifying circuit; the two ends of the current detection resistor are respectively connected to the first and second input terminals of the charge domain phase error detection amplifying circuit, and are respectively connected to the first and second input terminals of the phase detector; The reference clock generation circuit generates a reference clock under the control of the K-bit selection code and connects it to the third input terminal of the phase detector; the phase detector performs further phase comparison on the signals of the three input terminals to obtain a phase error signal; the phase error signal The voltage signal V _i is obtained through loop filter filtering; V _i is amplified by the first charge domain voltage amplification circuit to obtain error signals Vop and Von.

Further, in the low-power DDS circuit with amplitude and phase error self-calibration function, the charge domain amplitude error detection amplifier circuit includes: current detection resistor, reference reference generation circuit, common mode insensitive high-speed switched capacitor differential voltage A signal sampling network and a second charge domain voltage amplifying circuit; the two ends of the current detection resistor are respectively connected to the first and second input terminals of the charge domain amplitude error detection amplifying circuit, and are connected to the common mode insensitive high-speed switched capacitor differential voltage signal The first and second input ends of the sampling network; the reference reference generation circuit generates a differential reference voltage output under the control of the K-bit selection code, and is connected to the third and the third of the common-mode insensitive high-speed switched capacitor differential voltage signal sampling network Four input terminals; the switched capacitor differential voltage signal sampling network further samples the voltage signals of the four input terminals to obtain differential voltage signals V _i + and V _i -; the error signals Vop and Von are obtained by amplifying the second charge domain voltage amplifier circuit .

Further, in the low-power DDS circuit with amplitude and phase error self-calibration functions, the K-bit charge domain analog-to-digital converter includes: a P-level pipeline sub-level circuit based on charge domain signal processing technology, which uses Perform various processing on the sampled charge packets to complete analog-to-digital conversion and margin amplification, and input the output digital codes of each sub-level circuit to the delay synchronization register, and the output charge packets of each sub-level circuit enter the next The first stage repeats the above process; the P+1 stage is also the last stage A-bit Flash analog-to-digital converter circuit, which reconverts the charge packet transmitted from the P-stage into a voltage signal, and performs the final stage of analog-to-digital converter circuit Conversion work, and input the output digital code of this stage circuit to the delay synchronization register, this stage circuit only completes the analog-to-digital conversion, and does not perform margin amplification; the delay synchronization register is used for digital output of each sub-pipeline stage The code is delayed and aligned, and the aligned digital code is input to the digital correction module; the digital correction circuit module is used to receive the output digital code of the synchronous register, and shift and add the received digital code to obtain the modulus The R-bit digital output code of the converter; wherein, R is a positive integer, and both P and A are positive integers not greater than R.

Further, in the low-power DDS circuit with amplitude and phase error self-calibration functions, the first delay circuit and the second delay circuit all use the same delay circuit, and the structure includes: N delay buffer units and N K-bit delay registers; wherein, the delay code input terminals of the first K-bit delay register to the Nth K-bit delay register are all connected to the K-bit delay code, and the control signal input terminals are all connected to the Ctrl signal; the first delay buffer The delay code input ends of the unit to the Nth delay buffer unit are respectively connected to the delay code output ends of the first K-bit delay register to the Nth K-bit delay register, and the delay code output ends of the first delay buffer unit to the Nth delay buffer unit The data output terminals are respectively connected to the conversion codes of the 1st bit to the Nth bit conversion code and output, and the first control signal input terminals of the first delay buffer unit to the Nth delay buffer unit are all connected to the Ctrln signal, and the first delay The second control signal input terminals of the buffer unit to the Nth delay buffer unit are all connected to the Ctrl signal; wherein, Ctrl and Ctrln are a set of reverse signals.

Further, in the low-power DDS circuit with amplitude and phase error self-calibration functions, the compensation circuit includes: a delay buffer circuit and a K-bit addition circuit, and the delay of the delay buffer circuit and the K-bit addition circuit must be equal; the compensation circuit can work in two modes of calibration and compensation under the control of the Ctrl signal;

When in the calibration mode, the Ctrl signal is valid, the output of the K-bit addition circuit will be invalid, and the third N-bit calibration code will get the N-bit output code after the delay buffer circuit and output it;

In the compensation mode, the Ctrln signal is valid, the output of the K-bit addition circuit will be valid, and the N-K-bit conversion code will be output after the delay buffer circuit to obtain the N-K-bit output code, and the K-bit conversion code and the K-bit compensation code will be added after K-bit addition The circuit is added to obtain the K-bit output code and output it.

Further, in the low-power DDS circuit with amplitude and phase error self-calibration function, the control circuit includes: a core control circuit, a ROM readout circuit, a first delay code generation circuit, a second delay code generation circuit, Compensation code generation circuit, selection code generation circuit, arithmetic circuit, SRAM read and write circuit and K-bit register;

The connection relation of above-mentioned circuit is: the first output end of core control circuit is connected to the input end of ROM readout circuit, the second output end of core control circuit is connected to the control input end of the first delay code generation circuit, the core control circuit's The third output end is connected to the control input end of the second delay code generation circuit, the fourth output end of the core control circuit is connected to the control input end of the compensation code generation circuit, and the fifth output end of the core control circuit is connected to the control of the arithmetic circuit. The input terminal, the sixth output terminal of the core control circuit is connected to the control input terminal of the selection code generation circuit, the seventh output terminal of the core control circuit generates the calibration control signal Ctrl, and the eighth output terminal of the core control circuit is connected to the K-bit register at the same time And the control input terminal of the SRAM read-write circuit, the input terminal of the core control circuit is connected to the calibration start control signal; the ROM readout circuit generates the ROM address code according to the control instruction of the core control circuit; the data input terminal of the arithmetic circuit receives the SRAM read-write circuit The data sent by the output end, and generate the first K-bit error code, the second K-bit error code and the third K-bit error code according to the control instruction of the core control circuit; the data input end of the first delay code generation circuit receives the operation circuit data The first K-bit error code sent by the output terminal, and generates the first K-bit delay code according to the control instruction of the core control circuit; the data input terminal of the second delay code generation circuit receives the second K-bit error code sent by the data output terminal of the operation circuit code, and generate the second K-bit delay code according to the control instruction of the core control circuit; the data input end of the compensation code generation circuit receives the third K-bit error code sent by the data output end of the operation circuit, and generates it according to the control instruction of the core control circuit K-bit compensation code; the selection code generation circuit generates the first K-bit selection code and the second K-bit selection code according to the control instruction of the core control circuit; the data input end of the K-bit register receives the input of the K-bit charge domain analog-to-digital converter The K-bit quantization code sent by the output terminal sends the data stored in it to the SRAM read-write circuit according to the control instruction of the core control circuit; the SRAM read-write circuit generates the SRAM address data code according to the control instruction of the core control circuit, and the SRAM The module performs data reading and writing.

The invention has the advantages that the designed low-power DDS circuit with amplitude and phase error self-calibration function can automatically compromise the calibration precision according to the system precision and hardware cost, and has the characteristics of low power consumption. By adopting the charge domain signal processing technology, no operational amplifier is used in the error detection and processing, which has the characteristics of low power consumption; the charge domain ADC is used to quantify the error signal, and all error compensation methods adopt digital signal processing technology to further minimize power consumption And has the characteristic of low power consumption.

Description of drawings

FIG. 1 is a block diagram of a low-power DDS circuit with amplitude and phase error self-calibration functions of the present invention.

FIG. 2 is a structural block diagram of the phase error detection amplifier circuit in the charge domain according to the present invention.

Fig. 3 is a schematic diagram of the charge domain voltage amplifying circuit of the present invention.

Fig. 4 is a working waveform diagram of the charge domain voltage amplifying circuit of the present invention.

Fig. 5 is a structural block diagram of the phase detector circuit of the present invention.

FIG. 6 is a structural block diagram of the reference clock generating circuit of the present invention.

FIG. 7 is a structural block diagram of the charge domain amplitude error detection amplifier circuit of the present invention.

FIG. 8 is a structural block diagram of the reference reference generation circuit of the present invention.

FIG. 9 is a circuit block diagram of the charge domain analog-to-digital converter of the present invention.

FIG. 10 is a circuit block diagram of a sub-stage of a charge domain pipeline according to the present invention.

Fig. 11 is a structural block diagram of the delay circuit of the present invention.

Fig. 12 is a structural block diagram of the compensation circuit of the present invention.

Fig. 13 is a block diagram of the control circuit of the present invention.

detailed description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 shows the block diagram of the low power consumption DDS circuit with amplitude and phase error self-calibration function of the present invention. The low-power DDS circuit with amplitude and phase error self-calibration function includes: charge domain amplitude error detection amplifier circuit 10, charge domain phase error detection amplifier circuit 11, K-bit charge domain analog-to-digital converter 12, control circuit 13, ROM module 15 , SRAM module 14 , phase accumulator 16 , first delay circuit 17 , phase amplitude converter 18 , second delay circuit 19 , compensation circuit 110 and N-bit current modulus DAC 111 .

The connection relationship of the above-mentioned circuit is: the first and second input ends of the charge domain phase error detection amplifying circuit 11 are respectively connected to the signal output differential ports (corresponding signals Iop and Ion) of the N-bit current mode DAC 111, and the charge domain phase error detection The control input terminal of the amplifying circuit 11 is connected to the first K-bit selection code output port of the control circuit 13, and the differential voltage output terminal of the charge domain phase error detection amplifying circuit 11 is connected to the differential voltage input of the K-bit charge domain analog-to-digital converter 12 end; the first and second input ends of the charge domain amplitude error detection amplifier circuit 10 are respectively connected to the signal output differential port of the N-bit current mode DAC 111, and the control input end of the charge domain amplitude error detection amplifier circuit 10 is connected to the control circuit 13 The second K bit selection code output port of the second K bit, the differential voltage output end of the charge domain amplitude error detection amplifying circuit 10 is connected to the differential voltage input end of the K bit charge domain analog-to-digital converter 12; The K-bit quantization code is output to the error input port of the control circuit 13;

The ROM control port output control signal of control circuit 13 is given to ROM module 15, the SRAM control port output control signal of control circuit 13 is given SRAM module 14, and the first K delay code output end of control circuit 13 is connected to the first delay circuit 17 The second input port, the second K-bit delay code output end of the control circuit 13 is connected to the second input port of the second delay circuit 19, and the calibration control signal Ctrl output port of the control circuit 13 is connected to the charge domain phase error detection amplifier circuit at the same time 11. The input port of the calibration control signal Ctrl of the K-bit charge domain analog-to-digital converter 12, the compensation circuit 110, the first delay circuit 17, and the second delay circuit 19;

The first input port of the first delay circuit 17 is connected to the first N-bit calibration code output end of the ROM module 15, the third input port of the first delay circuit 17 is connected to the X-bit phase control input code of the phase accumulator 16, and the first delay The output port of the circuit 17 outputs the X-bit conversion code to the phase amplitude converter 18; the first input port of the second delay circuit 19 is connected to the second N-bit calibration code output end of the ROM module 15, and the third of the second delay circuit 19 The input port is connected to the N-bit amplitude control input code output by the phase-amplitude controller, and the output port of the second delay circuit 19 outputs the N-bit conversion code to the compensation circuit 110; the first input port of the compensation circuit 110 is connected to the third of the ROM module 15. N-bit calibration code output terminal, the third input port of the compensation circuit 110 is connected to the N-bit conversion code output by the second delay circuit 19, and the output port of the compensation circuit 110 outputs the N-bit output code to the data input of the N-bit current modulus DAC 111 end.

The low-power DDS circuit with amplitude and phase error self-calibration function of the present invention includes two working modes: a calibration mode and a compensation mode. When the circuit is working, enter the calibration mode first, and then enter the compensation mode; when entering the calibration mode, the X-bit phase control input code, the N-bit amplitude control input code, the N-bit output code, the first K-bit delay code, and the second K-bit Both the delay code and the K-bit compensation code are invalid, the first N-bit calibration code is input to the first delay circuit 17, the second N-bit calibration code is input to the second delay circuit 19, and the third N-bit calibration code is input to the compensation circuit 110; The charge domain amplitude error calibration circuit first performs amplitude error calibration on the N-bit current mode DAC 111, and then the charge domain phase error calibration circuit sequentially performs phase error calibration on the N-bit current mode DAC111 and the phase-amplitude converter 18; During the compensation mode, the X-bit phase control input code is input to the first delay circuit 17, the N-bit amplitude control input code is input to the second delay circuit 19, and the N-bit output code is input to the compensation circuit 110; the first N-bit calibration code, the second The two N-bit calibration codes and the third N-bit calibration code are invalid, and the first K-bit delay code, the second K-bit delay code and the K-bit compensation code are valid; the charge domain amplitude error calibration circuit starts to N-bit current modulus DAC 111 To perform amplitude error compensation, the charge domain phase error calibration circuit performs phase compensation on the N-bit current-mode DAC 111 and the phase-to-amplitude converter 18 at the same time.

One, the present invention has the low-power consumption DDS circuit of amplitude and phase error self-calibration function to carry out the calibration principle of amplitude error calibration to N bit current mode DAC111:

When the calibration mode is turned on, the control circuit 13 first controls the charge domain amplitude error detection amplifying circuit 10, the K-bit charge domain analog-to-digital converter 12 and the compensation circuit 110 to enter the calibration mode through the Ctrl signal, and simultaneously outputs the second K-bit selection code to the charge domain. Domain amplitude error detection amplifying circuit 10; Control circuit 13 then produces the first group of second K-bit selection codes, and simultaneously controls ROM module 15 to generate the first group of third N-bit calibration codes; the first group of third N-bit calibration codes enters the compensation The circuit 110 also obtains an N-bit output code, and the N-bit output code enters the N-bit current modulus DAC 111 circuit to be calibrated, and obtains the first group of amplitude error differential output current signals Iop and Iop corresponding to the third N-bit calibration code through digital-to-analog conversion. Ion; the charge domain amplitude error detection amplifier circuit 10 detects the amount of Iop-Ion, processes it and compares it with the first group of reference voltages Vrefp-Vrefn generated by the internal reference generation circuit, and amplifies the difference. The error voltage Vop-Von is obtained; the K-bit charge domain analog-to-digital converter 12 performs analog-to-digital conversion on the error voltage Vop-Von, and the first group of amplitude error K-bit quantization codes can be obtained and output to the control circuit 13; the control circuit 13 will receive The K-bit quantization code of the obtained first group of amplitude errors is stored in the SRAM module 14, and the amplitude error quantization under one input condition is completed.

Next, the control circuit 13 will generate a second group of second K-bit selection codes and simultaneously control the ROM module 15 to generate a second group of third N-bit calibration codes, and the second group of third N-bit calibration codes will enter the compensation circuit 110 and obtain N N-bit output code, the N-bit output code enters the N-bit current mode DAC 111 circuit to be calibrated, and the second group of amplitude error differential output current corresponding to the second group of third N-bit calibration code is obtained through digital-to-analog conversion; the charge domain amplitude error The detection amplifier circuit 10 can obtain the second set of error voltage Vop-Von by comparing the second set of differential output currents with the second set of reference voltages and amplifying the difference; the K-bit charge domain analog-to-digital converter 12 converts the second set of error voltages to The voltage Vop-Von performs analog-to-digital conversion, and the second group of amplitude error K-bit quantization codes can be obtained and output to the control circuit 13; the control circuit 13 stores the received second group of amplitude error K-bit quantization codes in the SRAM module 14 to complete Magnitude error quantization for the second input condition.

According to this cycle, when the control circuit 13 generates the second K-bit selection code of the L group and simultaneously controls the ROM module 15 to generate the third N-bit calibration code of the L group, and obtains the K-bit quantization code of the L group amplitude error, and stores it in After being stored in the SRAM module 14, the arithmetic circuit inside the control circuit 13 will calculate the K-bit quantization codes of the L groups of amplitude errors stored in the SRAM module 14 to obtain a K-bit compensation code.

At this time, the control circuit 13 will output the K-bit compensation code to the compensation circuit 110, and set the compensation circuit 110 to the compensation mode, while keeping the K-bit compensation code unchanged. The low power consumption DDS circuit with amplitude and phase error self-calibration function completes the calibration of the amplitude error of the N-bit current mode DAC 111 .

In the above-mentioned calibration process, each group of the third N-bit calibration code output to the compensation circuit 110 and the second K-bit selection code output to the charge domain amplitude error detection amplifier circuit 10 simultaneously generated by the control circuit 13 must correspond one-to-one, that is, : The third N-bit calibration code of the J-th group must be used in conjunction with the second K-bit selection code of the J-th group, wherein, L is a positive integer not greater than ^2K , and J is a positive integer not greater than L.

Two, the low power consumption DDS circuit with amplitude and phase error self-calibration function of the present invention carries out the calibration principle of phase error calibration to N-bit current mode DAC 111 and phase-amplitude converter 18:

After the low-power DDS circuit with amplitude and phase error self-calibration function completes the calibration of the amplitude error of the N-bit current mode DAC 111, the control circuit 13 controls the charge domain phase error detection amplifier circuit 11 and the second delay circuit through the Ctrl signal 19 to enter the calibration mode, and at the same time output the first K-bit selection code to the charge domain phase error detection amplifier circuit 11, and start to perform phase error calibration on the N-bit current mode DAC 111.

Then the control circuit 13 generates the first group of first K bit selection codes, and simultaneously controls the ROM module 15 to generate the first group of second N bit calibration codes; the second N bit calibration codes of the first group enter the second delay circuit 19 and obtain N bits Conversion code, the N-bit conversion code enters the N-bit current mode DAC 111 circuit to be calibrated, and the first group of phase error differential output currents Iop and Ion corresponding to the first group of second N-bit calibration codes are obtained through digital-to-analog conversion; the charge domain phase The error detection amplifier circuit 11 detects the amount of Iop-Ion, processes it and performs phase detection with the first group of reference clocks generated by the internal reference clock generation circuit 21, and amplifies the phase difference to obtain the error voltage Vop- Von; the K-bit charge domain analog-to-digital converter 12 performs analog-to-digital conversion on the error voltage Vop-Von to obtain the first group of phase error K-bit quantization codes and output them to the control circuit 13; the control circuit 13 will receive the first group of phases The K-bit quantization code of the error is stored in the SRAM module 14 to complete the phase error quantization of the N-bit current mode DAC 111 circuit under an input condition.

Next, the control circuit 13 generates the second group of first K-bit selection codes, and simultaneously controls the ROM module 15 to generate a second group of second N-bit calibration codes; the second group of second N-bit calibration codes enters the second delay circuit 19 and obtains N-bit conversion code, the N-bit conversion code enters the N-bit current mode DAC 111 circuit to be calibrated, and the second group of differential output currents Iop and Ion corresponding to the second group of second N-bit calibration codes are obtained through digital-to-analog conversion; the charge domain The phase error detection amplifier circuit 11 detects the amount of Iop-Ion, processes it and performs phase detection with the second group of reference clocks generated by the internal reference clock generation circuit 21, and amplifies the phase difference to obtain the error voltage Vop -Von; the K-bit charge domain analog-to-digital converter 12 performs analog-to-digital conversion on the error voltage Vop-Von to obtain the second group of phase error K-bit quantization codes and output them to the control circuit 13; the control circuit 13 will receive the second group The K-bit quantization code of the phase error is stored in the SRAM module 14 to complete the phase error quantization of the N-bit current mode DAC 111 circuit to be calibrated under two input conditions.

According to this cycle, when the controller generates the second N-bit calibration code of the L group and the first K-bit selection code of the L group, and obtains the K-bit quantization code of the L group phase error, and stores it in the SRAM module 14, the control The arithmetic circuit inside the circuit 13 will calculate the K-bit quantization codes of the L groups of phase errors stored in the K-bit register group to obtain the second K-bit delay code. The control circuit 13 will output the second K-bit delay code to the second delay circuit 19 at this time, and keep the second K-bit delay code unchanged. The control circuit 13 sets the second delay circuit 19 to the compensation mode, and completes the adjustment of the N Phase Error Calibration of Bit Current Mode DAC 111.

Afterwards, the control circuit 13 controls the first delay circuit 17 to enter the calibration mode through the Ctrl signal, and at the same time outputs a K-bit selection code to the charge-domain phase error detection amplifier circuit 11 to start phase error calibration of the phase-to-amplitude converter 18 . The control circuit 13 controls the ROM module 15 to generate the first N-bit calibration code. Through the first delay circuit 17, the charge domain phase error detection amplifier circuit 11 and the K-bit charge domain analog-to-digital converter 12, the N-bit current mode DAC 111 is adopted and corrected. The same steps and methods of phase error calibration, obtain the first K-bit delay code and output it to the first delay circuit 17, while keeping the first K-bit delay code unchanged, the control circuit 13 sets the first delay circuit 17 to compensate mode, the phase error calibration of the phase-to-amplitude converter 18 is completed.

At this point, the calibration mode of the low-power DDS circuit with amplitude and phase error self-calibration functions ends.

During the above-mentioned phase error calibration process, each group of the first N-bit calibration code and the second N-bit calibration code simultaneously generated by the control circuit 13 and the first K-bit selection code output to the charge domain phase error detection amplifier circuit 11 must be identical One-to-one correspondence, namely: the first N-digit calibration code and the second N-digit calibration code of the J-th group must be used in conjunction with the first K-digit selection code of the J-th group.

In the actual use of the low-power DDS circuit with amplitude and phase error self-calibration function described in the present invention, the accuracy of DDS amplitude and phase error calibration, the size of hardware overhead and the length of calibration time can be selected according to different K and L values Make settings to meet the calibration accuracy and speed requirements of DDS chips with different accuracy and speed.

FIG. 2 is an implementation manner of the charge domain phase error detection amplifier circuit 11 of the present invention. The circuit includes: a current detection resistor Rd, a reference clock generation circuit 21 , a phase detector 22 , a loop filter 23 and a first charge domain voltage amplification circuit 24 . The two ends of the current detection resistor Rd are respectively connected to the first and second input terminals of the charge domain phase error detection amplifier circuit 11, and connected to the first and second input terminals Voutp and Voutn of the phase detector 22; the reference clock generation circuit 21, under the control of the K-bit selection code, the reference clock Clkref is generated and connected to the third input terminal of the phase detector 22; the phase detector 22 performs further phase comparison on the signals of the three input terminals to obtain the phase error signal Vp, the phase error The signal Vp is filtered by the loop filter 23 to obtain the voltage signal V _i ; it is amplified by the first charge domain voltage amplifying circuit 24 to obtain the error signals Vop and Von.

FIG. 3 is a schematic diagram of the first charge domain voltage amplifying circuit 24 of the present invention. The first charge domain voltage amplifying circuit 24 includes: a first positive charge storage node Nip, a first negative charge storage node Nin, a second positive charge storage node Nop and a second negative charge storage node Non, one connected to the A positive-end charge transfer control switch 301 between the first and second positive-end charge storage nodes Nip and Nop, a negative-end charge transfer control switch 302 connected between the first and second negative-end charge storage nodes Nin and Non, The positive terminal capacitor 303 connected to the first positive terminal charge storage node Nip, the positive terminal capacitance programmable capacitor 309 connected to the second positive terminal charge storage node Nop, and the negative terminal capacitor connected to the first negative terminal charge storage node Nin 304, the negative terminal capacity programmable capacitor 310 connected to the second negative terminal charge storage node Non, the first positive terminal voltage transmission switch 305 connected to the first positive terminal charge storage node Nip, connected to the first positive terminal charge storage node The second positive terminal voltage transmission switch 307 of the node Nip, the third positive terminal voltage transmission switch 313 connected to the second positive terminal charge storage node Nop, and the fourth positive terminal voltage transmission switch connected to the second positive terminal charge storage node Nop 311. The first negative terminal voltage transmission switch 306 connected to the first negative terminal charge storage node Nin, the second negative terminal voltage transmission switch 308 connected to the first negative terminal charge storage node Nin, connected to the second negative terminal charge storage node The third negative terminal voltage transmission switch 314 of the node Non and the fourth negative terminal voltage transmission switch 312 connected to the second negative terminal charge storage node Non. For the embodiment of the present invention, any one of the two analog voltage input terminals of the first charge domain voltage amplifying circuit 24 is connected to Vi, and the other terminal is connected to a reference signal.

FIG. 4 is a schematic diagram of working sequence control waveforms of the circuit shown in FIG. 3 . The control clocks Clk and Clkn are clocks with opposite phases, and the switch control signals Clkr, Clks and Clkt are clocks with non-overlapping phases. The charge transmission control switch described in the present invention can be realized by the implementation method described in the invention patent with the patent number of 201010291245.6, and the voltage transmission switch can be realized by a general MOS transistor or a BJT switch.

FIG. 5 shows an implementation of the phase detector 22 circuit of the present invention. The circuit consists of a signal shaping block and a subtractor sub-block. The signal shaping module shapes the input differential signals Voutp and Voutn to obtain the input phase, the reference clock output by the reference clock is used as the reference phase, and the subtractor sub-module subtracts the input phase from the reference phase to obtain the phase error signal Vp.

FIG. 6 is a structural block diagram of the reference clock generating circuit 21 of the present invention. The reference clock generation circuit 21 includes: a programmable frequency adjustment circuit and a programmable duty ratio adjustment circuit. Both the programmable frequency adjustment circuit and the programmable duty cycle adjustment circuit are controlled by a K-bit selection code. Under the control of the K-bit selection code, after the input clock with fixed frequency and duty ratio passes through the programmable frequency adjustment circuit and the programmable duty ratio adjustment circuit successively, the reference clocks with different frequencies and duty ratios can be obtained Clock Clkref.

FIG. 7 is an implementation manner of the charge domain amplitude error detection amplifier circuit 10 of the present invention, which is implemented by a fully differential structure. The circuit includes: a current detection resistor Rd, a reference generation circuit 71 , a common mode insensitive high-speed switched capacitor differential voltage signal sampling network 72 and a second charge domain voltage amplification circuit 73 .

The two ends of the current detection resistor Rd are respectively connected to the first and second input terminals of the charge domain amplitude error detection amplifier circuit 10, and connected to the first and second inputs of the common-mode insensitive high-speed switched capacitor differential voltage signal sampling network 72 terminals Voutp and Voutn; the reference reference generation circuit 71 generates differential reference voltage output terminals Vrefp and Vrefn under the control of the K-bit selection code, and is connected to the third and the third of the common-mode insensitive high-speed switched capacitor differential voltage signal sampling network 72 Four input terminals; the switched capacitor differential voltage signal sampling network 72 further samples the voltage signals of the four input terminals to obtain differential voltage signals V _i + and V _i −; amplified by the second charge domain voltage amplifier circuit 73 to obtain an error signal Vop and Von.

FIG. 8 is a structural block diagram of the reference reference generation circuit of the present invention. The reference generation circuit includes: a resistor string, a switch array and an output switch selection circuit. The resistor string is composed of 2 ^K -1 resistors of equal size connected in series, and its two ends are respectively connected to the reference voltage 3 and the reference voltage 4, and 2 ^K voltages can be obtained by dividing the voltage by 2 ^K -1 resistors of equal size; the switch array It contains 2 ^K -1 voltage selection switches, which output a set of differential reference voltages Vrefp and Vrefn under the control of the output switch selection circuit; the output switch selection circuit selects to open the two switches in the array under the control of the K-bit selection code. Voltage transfer switch. The reference reference generation circuit generates a set of differential reference voltages Vrefp and Vrefn according to any set of K-bit selection codes. Reference voltage 3 and reference voltage 4 shown in FIG. 8 are Vref3 and Vref4 shown in FIG. 1 , respectively.

As shown in Figure 9, the K-bit charge domain analog-to-digital converter 12 designed by the present invention includes: P-level pipeline sub-level circuits based on charge domain signal processing technology, the last level (P+1 level) A-bit Flash module Digital converter circuit, delay synchronous register and digital correction circuit module. In addition, the working mode control module is also an auxiliary working module necessary for the operation of the analog-to-digital converter, which is not marked in the figure. In the charge domain analog-to-digital converter circuit in Figure 9, the work of two adjacent sub-level circuits is controlled by two sets of multi-phase clocks, the working states are completely complementary, and the number of sub-level circuits and the number of bits k of each level circuit are the same Can be adjusted flexibly. For example, for a 14-bit analog-to-digital converter with K=14, a structure of 12 levels of 1.5bit/level + 1 level of 2bit Flash with a total of 13 levels can be used, or 4 levels of 2.5bit/level + 3 levels of 1.5bit/level + 1 A total of 8 levels of 3bit Flash structure.

The charge domain analog-to-digital converter designed by the present invention includes the following contents: P-level charge domain pipeline sub-level circuit based on charge domain signal processing technology, which is used to perform various processes on the sampled charge packets to complete analog-to-digital conversion and margin Amplify, and input the output digital code of each sub-level circuit to the delay synchronous register, and the charge packet output by each sub-level circuit enters the next level to repeat the above process; the last level (P+1 level) A- Bit Flash analog-to-digital converter circuit, which reconverts the charge packet transmitted by the P-level into a voltage signal, and performs the last-level analog-to-digital conversion work, and inputs the output digital code of the current-level circuit to the delay synchronization register , the circuit at this stage only completes the analog-to-digital conversion without margin amplification; the delay synchronization register is used to delay align the digital codes output by each sub-pipeline stage, and input the aligned digital codes to the digital correction module ; A digital correction circuit module, which is used to receive the output digital code of the synchronous register, and shift and add the received digital code to obtain the R-bit digital output code of the analog-to-digital converter. In the above description, R is a positive integer, and both A and P are positive integers not greater than R.

Figure 10 shows the schematic diagram of the sub-stage circuit of the charge domain pipeline. The circuit is composed of a fully differential signal processing channel. The whole circuit includes: 2 current-stage charge transfer control switches, 2 charge storage nodes, 6 charge storage capacitors connected to the charge storage nodes, C charge comparators, and C receivers The reference signal selection circuit controlled by the output result of the comparator, 2B+2 voltage transmission switches, where B is a positive integer. When the circuit is working normally, the front-stage differential charge packet is first transmitted through the charge transmission control switch and stored in the charge storage node of the current stage. Voltage 4 is compared to obtain the C-bit quantized output digital codes D1~DB of this stage; the digital output codes D1~DB will be output to the delay synchronization register, and at the same time D1~DB will also control the reference signal selection circuit of the stage respectively, so that They respectively generate a pair of complementary reference signals to respectively control the charge addition and subtraction capacitor bottom plate of the positive and negative terminals of the current stage, and perform corresponding addition and subtraction processing on the differential charge packets transmitted from the previous stage to the current stage to obtain the differential residual charge packets of the current stage ; Finally, the circuit completes the transmission of the differential residual charge packet of the current stage from the current stage to the next stage, the reference voltage 2 resets the differential charge storage node of the current stage, and completes the work of a complete clock cycle of the sub-stage circuit of the charge domain pipeline. Among them, C is a positive integer.

For the last stage (P+1 stage) of the charge domain pipeline analog-to-digital converter designed by the present invention in Fig. 9, the pipeline sub-level circuit A-bit Flash analog-to-digital converter circuit based on the charge domain signal processing technology, the sub-level The circuit only needs to perform the final analog-to-digital conversion on the received charge packet, and input the output digital code of this stage circuit to the delay synchronous register without margin processing. Just remove the reference signal selection circuit in Figure 10 and the 4 capacitors controlled by the reference signal selection circuit.

FIG. 11 is a structural block diagram of the delay circuit adopted in the present invention. The delay circuit includes: N delay buffer units and N K-bit delay registers, first to Nth delay buffer units and first K-bit delay registers to Nth K-bit delay registers. The delay code input terminals of the first K-bit delay register to the Nth K-bit delay register are all connected to the K-bit delay code, and the control signal input terminals are all connected to the Ctrl signal; the first delay buffer unit to the Nth delay buffer unit The delay code input terminals of the delay codes are respectively connected to the delay code output terminals of the first K-bit delay register to the N-th K-bit delay register, and the data output terminals of the first delay buffer unit to the N-th delay buffer unit are respectively connected to the first The first control signal input terminals of the first delay buffer unit to the Nth delay buffer unit are all connected to the Ctrln signal, and the first delay buffer unit to the Nth delay buffer unit The second control signal input terminals of the unit are all connected to the Ctrl signal. Among them, Ctrl and Ctrln are reverse clocks.

The delay circuit can work in two modes of calibration and compensation under the control of the Ctrl signal. In the calibration mode, the Ctrl signal is valid, the 1st to Nth input code is invalid, and the input code has no effect on the output of the Nth conversion code, and the 1st to Nth calibration codes are respectively delayed. After the time buffer circuit 1 ~ delay buffer circuit N, the first to Nth conversion codes are obtained and output, and the K-bit delay code is input into the first K-bit delay register to the N-th K-bit delay register and is Latch remains unchanged. In the compensation mode, the Ctrln signal is valid, the conversion code of the 1st digit to the input code of the Nth digit is valid, and the conversion code of the 1st digit to the Nth digit is obtained and output after the delay buffer circuit, and the calibration code of the first digit The ~N-th calibration code is invalid, and the K-bit delay codes stored in the first K-bit delay register to the N-th K-bit delay register are input to the delay buffer circuit 1 to the delay buffer circuit N for delay compensation.

Both the first delay circuit 17 and the second delay circuit 19 described in the present invention adopt the delay circuit shown in FIG. 11 .

FIG. 12 is a structural block diagram of the compensation circuit 110 of the present invention. The compensation circuit 110 includes a delay buffer circuit and a K-bit addition circuit inside, and the delays of the delay buffer circuit and the K-bit addition circuit must be equal. The compensation circuit 110 can work in two modes of calibration and compensation under the control of the Ctrl signal. When in the calibration mode, the Ctrl signal is valid, the output of the K-bit addition circuit will be invalid, and the third N-bit calibration code is passed through the delay buffer circuit to obtain an N-bit output code and output it. In the compensation mode, the Ctrln signal is valid, the output of the K-bit addition circuit will be valid, and the N-K-bit conversion code will be output after the delay buffer circuit to obtain the N-K-bit output code, and the K-bit conversion code and the K-bit compensation code will be added after K-bit addition The circuit adds K-bit output codes and outputs them, where Ctrl and Ctrln are reverse clocks.

FIG. 13 is a block diagram of the control circuit 13 of the present invention. Described control circuit 13 comprises: core control circuit, ROM readout circuit, the first delay code generation circuit, the second delay code generation circuit, compensation code generation circuit, selection code generation circuit, operation circuit, SRAM read-write circuit and K bit register.

The connection relationship of the control circuit 13 is: the first output end of the core control circuit is connected to the input end of the ROM readout circuit, the second output end of the core control circuit is connected to the control input end of the first delay code generation circuit, the core The third output end of the control circuit is connected to the control input end of the second delay code generation circuit, the fourth output end of the core control circuit is connected to the control input end of the compensation code generation circuit, and the fifth output end of the core control circuit is connected to the operation The control input end of the circuit, the sixth output end of the core control circuit is connected to the control input end of the selection code generation circuit, the seventh output end of the core control circuit generates a calibration control signal Ctrl, and the eighth output end of the core control circuit is connected to the The K-bit register and the control input terminal of the SRAM read and write circuit, the input terminal of the core control circuit are connected to the calibration start control signal; the ROM readout circuit generates the ROM address code according to the control command of the core control circuit; the data input terminal of the arithmetic circuit receives the SRAM Read and write the data sent by the output of the circuit, and generate the first K-bit error code, the second K-bit error code and the third K-bit error code according to the control instructions of the core control circuit; the data input terminal of the first delay code generation circuit receives The first K-bit error code sent by the data output end of the arithmetic circuit, and generates the first K-bit delay code according to the control instruction of the core control circuit; the data input end of the second delay code generation circuit receives the second error code sent by the data output end of the arithmetic circuit K-bit error code, and generate the second K-bit delay code according to the control instruction of the core control circuit; the data input end of the compensation code generation circuit receives the third K-bit error code sent by the data output end of the operation circuit, and generates the second K-bit error code according to the core control circuit. The control command generates a K-bit compensation code; the selection code generation circuit generates the first K-bit selection code and the second K-bit selection code according to the control command of the core control circuit; the data input terminal of the K-bit register receives the K-bit charge domain modulus The K-bit quantization code sent by the output end of the converter 12, and the data stored in it is sent to the SRAM read-write circuit according to the control instruction of the core control circuit; the SRAM read-write circuit generates the SRAM address data according to the control instruction of the core control circuit code to read and write data to the SRAM module 14.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection of the present invention. within range.

Claims (10)

1. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function, it is characterized in that, including：Charge-domain amplitude is missed Difference detection amplifying circuit (10), charge-domain phase error detection amplifying circuit (11), K charge-domain analog-digital converter (12), control Circuit (13) processed, ROM module (15), SRAM module (14), phase accumulator (16), the first delay circuit (17), phase amplitude Converter (18), the second delay circuit (19), compensation circuit (110) and N current-mode DAC (111)；

First, second input of charge-domain phase error detection amplifying circuit (11) is connected respectively to N current-mode DAC (111) signal output difference port, the control signal of charge-domain phase error detection amplifying circuit (11) is connected to control First K option code output port of circuit (13), the differential voltage output of charge-domain phase error detection amplifying circuit (11) End is connected to the K differential voltage input of charge-domain analog-digital converter (12)；Charge-domain range error detects amplifying circuit (10) first, second input is connected respectively to the N signal output difference port of current-mode DAC (111), charge-domain amplitude The control signal of error-detecting amplifying circuit (10) is connected to the 2nd K option code output port of control circuit (13), electricity The differential voltage output end in lotus domain range error detection amplifying circuit (10) is connected to the K difference of charge-domain analog-digital converter (12) Component voltage input；Error input of the K K quantization code output of charge-domain analog-digital converter (12) to control circuit (13) Mouthful；

The ROM control ports output control signal of control circuit (13) gives ROM module (15), the SRAM controls of control circuit (13) Port output control signal gives SRAM module (14), and a K delay code output end of control circuit (13) is connected to first and prolongs Second input port of slow circuit (17), the 2nd K delay code output end of control circuit (13) is connected to the second delay circuit (19) the second input port, the calibration control signal Ctrl output ports of control circuit (13) are connected to charge-domain phase simultaneously Error-detecting amplifying circuit (11), K charge-domain analog-digital converter (12), compensation circuit (110), the first delay circuit (17) with And second delay circuit (19) calibration control signal Ctrl input ports；

First N calibration code output end of first input port connection ROM module (15) of the first delay circuit (17), first prolongs X phase controlling input code of the 3rd input port connection phase accumulator (16) of slow circuit (17), the first delay circuit (17) X hand over word output is arrived phase amplitude converter (18) by output port；First input of the second delay circuit (19) 2nd N calibration code output end of port connection ROM module (15), the 3rd input port connection phase of the second delay circuit (19) The N amplitude control input code of position amplitude controller output, the output port of the second delay circuit (19) exports N hand over word To compensation circuit (110)；3rd N calibration code output of first input port connection ROM module (15) of compensation circuit (110) End, the 3rd input port of compensation circuit (110) connects N hand over word of the second delay circuit (19) output, compensation circuit (110) N output code output is arrived the N data input pin of current-mode DAC (111) by output port；Wherein, N is positive integer, K is the no more than positive integer of N.

2. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, its Mode of operation includes calibration mode and compensation model；And calibration mode is introduced into when circuit works, afterwards into compensation model； When calibration mode is entered, X phase controlling input code, N amplitude control input yard, N output code, K delay code, 2nd K delay code and K compensation codes are invalid, and a N calibration code is input to the first delay circuit (17), the 2nd N school Quasi- code is input to the second delay circuit (19), and the 3rd N calibration code is input to compensation circuit (110)；The charge-domain amplitude is missed Difference calibration circuit first carries out range error calibration to N current-mode DAC (111), then the charge-domain phase error calibration electricity Road carries out phase error calibration to N current-mode DAC (111) and phase amplitude converter (18) successively；Entering compensation model When, X phase controlling input code is input to the first delay circuit (17), and N amplitude control input code is input to the second deferred telegram Road (19), N output code is input to compensation circuit (110)；First N calibration code, the 2nd N calibration code and the 3rd N calibration Code it is invalid, the first K postpone code, the 2nd K delay code and K compensation codes it is effective；The charge-domain range error calibrates circuit Start to carry out N current-mode DAC (111) range error compensation, the charge-domain phase error calibration circuit is simultaneously to N electricity Stream mould DAC (111) and phase amplitude converter (18) carry out phase compensation.

3. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 2, it is characterized in that, its When range error calibration is carried out to the N current-mode DAC (111), the job order of circuit is as follows：

Control circuit (13) controls charge-domain range error to detect amplifying circuit (10), K charge-domain first by Ctrl signals Analog-digital converter (12) and compensation circuit (110) enter calibration mode, while export the 2nd K option code being missed to charge-domain amplitude Difference detection amplifying circuit (10)；

Then control circuit (13) produces first group of the 2nd K option code, while controlling ROM module (15) to produce first group the 3rd N calibration code；First group of the 3rd N calibration code enters compensation circuit (110) and obtains N output code, and N output code enters to be treated N current-mode DAC (111) circuit of calibration, first group of range error corresponding with the 3rd N calibration code is obtained through digital-to-analogue conversion Differential output current；Charge-domain range error detects amplifying circuit (10) by detecting first group of range error differential output current Amount, and treatment obtains the first grouping error voltage；First grouping error voltage is carried out modulus and turned by K charge-domain analog-digital converter (12) Change, first group of range error K quantization code can be obtained and exported to control circuit (13)；Control circuit (13) obtains reception In SRAM module (14), the range error completed under a kind of input condition quantifies for first group of range error K quantization code storage；

And then, control circuit (13) can produce second group of the 2nd K option code and control ROM module (15) to produce second simultaneously The 3rd N calibration code of group, second group of the 3rd N calibration code enters compensation circuit (110) and obtains N output code, N output code Into N current-mode DAC (111) circuit to be calibrated, obtained and second group of the 3rd N calibration code corresponding through digital-to-analogue conversion Two groups of range error differential output currents；Charge-domain range error detects amplifying circuit (10) by comparing second group of difference output Simultaneously be amplified for its difference can obtain the second grouping error voltage by electric current and second group of reference voltage；K charge-domain modulus turns Second grouping error voltage is carried out analog-to-digital conversion by parallel operation (12), can obtain second group of range error K quantization code and output is arrived Control circuit (13)；Reception is obtained second group of range error K quantization code storage in SRAM module (14) by control circuit (13) In, the range error completed under second input condition quantifies；

Circulate according to this, when control circuit (13) produces the K option code of L groups the 2nd and controls ROM module (15) to produce L simultaneously After the 3rd N calibration code of group, and obtains K quantization code of L group range errors, and storage is in the SRAM module (14), control electric The internal computing circuit in road (13) will be calculated the K quantization code of L group range errors stored in SRAM module (14) Obtain K compensation codes；Control circuit (13) can be now arrived in compensation circuit (110) output of K compensation codes, and by compensation circuit (110) pattern is arranged to compensate for, while keeping K compensation codes constant；So far, complete to miss N current-mode DAC (111) amplitude Poor calibration；

In above-mentioned calibration process, control circuit (13) is while each group of output for producing is to the 3rd N school of compensation circuit (110) Quasi- code and output must be corresponded to the 2nd K option code of charge-domain range error detection amplifying circuit (10), i.e.,：J The 3rd N calibration code of group must be used cooperatively with the K option code of J groups the 2nd；Wherein, L is no more than 2^KPositive integer；J is The no more than positive integer of L.

4. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 2, it is characterized in that, its When phase error calibration is carried out to the N current-mode DAC (111) and phase amplitude converter (18), the job order of circuit It is as follows：

1st, phase error calibration is carried out to N current-mode DAC (111) first：

1.1 controls circuit (13) control charge-domain phase error detection amplifying circuit (11) and the second deferred telegram by Ctrl signals Road (19) enters calibration mode, while exporting a K option code to charge-domain phase error detection amplifying circuit (11), starts Phase error calibration is carried out to N current-mode DAC (111)；

Then 1.2 control circuit (13) to produce first group of the first K option code, while controlling ROM module (15) to produce first group 2nd N calibration code；First group of the 2nd N calibration code enters the second delay circuit (19) and obtains N hand over word, N conversion Code enters N current-mode DAC (111) circuit to be calibrated, and corresponding with first group of the 2nd N calibration code the is obtained through digital-to-analogue conversion One group of phase error differential output current；Charge-domain phase error detection amplifying circuit (11) is by detecting first group of phase error Differential output current amount, and process and obtain first group of phase error voltage；K charge-domain analog-digital converter (12) is by first Group phase error voltage carries out analog-to-digital conversion, can obtain first group of phase error K quantization code and export to control circuit (13)；Reception is obtained first group of phase error K quantization code storage in SRAM module (14) by control circuit (13), completes one Plant N current-mode DAC (111) current phase error quantization under input condition；

1.3 and then, and control circuit (13) produces second group of the first K option code, while controlling ROM module (15) to produce second The 2nd N calibration code of group；Second group of the 2nd N calibration code enters the second delay circuit (19) and obtains N hand over word, and N turns Escape enters N current-mode DAC (111) circuit to be calibrated, obtains corresponding with second group of the 2nd N calibration code through digital-to-analogue conversion Second group of phase error differential output current；Charge-domain phase error detection amplifying circuit (11) is by detecting second group of phase Error differential output current amount, and process and obtain second group of phase error voltage；K charge-domain analog-digital converter (12) will Second group of phase error voltage carries out analog-to-digital conversion, can obtain second group of phase error K quantization code and export to control electricity Road (13)；Reception is obtained second group of phase error K quantization code storage in SRAM module (14) by control circuit (13), is completed N to be calibrated current-mode DAC (111) current phase error quantization under two kinds of input conditions；

1.4 circulate according to this, when control circuit (13) produces the N calibration code of L groups the 2nd and the K option code of L groups the, and obtain To K quantization code of L group phase errors, and after storing in SRAM module (14), the internal computing circuit of control circuit (13) Will the K quantization code of L group phase errors that stored in K bit register groups be carried out being calculated the 2nd K delay code；Control Circuit (13) can be now exported in the second delay circuit (19) the 2nd K delay code, and keeps the 2nd K delay code not Become, the second delay circuit (19) is arranged to compensate for pattern by control circuit (13), complete to the N phase of current-mode DAC (111) Calibrate for error；

2nd, afterwards, control circuit (13) controls the first delay circuit (17) to enter calibration mode by Ctrl signals, while exporting K Position option code starts to carry out phase error to phase amplitude converter (18) to charge-domain phase error detection amplifying circuit (11) Calibration；

Control circuit (13) controls ROM module (15) to produce a N calibration code, by the first delay circuit (17), charge-domain Phase error detection amplifying circuit (11) and K charge-domain analog-digital converter (12), using and to N current-mode DAC (111) Phase error calibrates identical step and method, obtains a K delay code and exports in the first delay circuit (17), while Keep a K delay code constant, control circuit (13) that the first delay circuit (17) is arranged to compensate for into pattern, complete to phase The phase error calibration of amplitude converter (18)；Now, calibration mode terminates；

In above-mentioned phase error calibration process, control circuit (13) is while an each group of N calibration code and the 2nd N of generation Position calibration code and output must be corresponded to a K option code of charge-domain phase error detection amplifying circuit (11), i.e.,： The N calibration code of J groups the first and the 2nd N calibration code must be used cooperatively with the K option code of J groups the；Wherein, L is No more than 2^KPositive integer, J is the no more than positive integer of L.

5. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute Charge-domain phase error detection amplifying circuit (11) stated includes：Current sense resistor, reference clock produce circuit (21), phase demodulation Device (22), loop filter (23) and the first charge-domain voltage amplifier circuit (24)；The two ends of current sense resistor connect respectively To first, second input of charge-domain phase error detection amplifying circuit (11), and it is connected respectively to the of phase discriminator (22) One and second input；Reference clock produces circuit (21) under the K control of option code, produces reference clock and is connected to mirror 3rd input of phase device (22)；Phase discriminator (22) carries out further phase bit comparison and obtains phase to 3 signals of input Error signal；Phase error signal obtains voltage signal V by loop filter (23) filtering_i；V_iBy the first charge-domain voltage Amplifying circuit (24) amplification obtains error signal Vop and Von.

6. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute State charge-domain range error and detect that amplifying circuit (10) includes：Current sense resistor, reference data produce circuit (71), common mode not Sensitive speed-sensitive switch electric capacity differential voltage signal sampling network (72) and the second charge-domain voltage amplifier circuit (73)；Current detecting The two ends of resistance are connected respectively to the first and second inputs of charge-domain range error detection amplifying circuit (10), and are connected to First and second inputs of the insensitive speed-sensitive switch electric capacity differential voltage signal sampling network (72) of common mode；Reference data is produced Circuit (71) produces differential reference voltage output, and be connected to the insensitive speed-sensitive switch electricity of common mode under the K control of option code Third and fourth input of tolerance divided voltage signal sampling network (72)；Switching capacity differential voltage signal sampling network is to 4 The voltage signal of individual input is further sampled, and obtains differential voltage signal V_i+ and V_i-；By the second charge-domain voltage Amplifying circuit (73) amplification obtains error signal Vop and Von.

7. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute The K charge-domain analog-digital converter (12) stated includes：The P grades of sub- level circuit of streamline based on charge-domain signal processing technology, its For being carried out to the charge packet that obtains of sampling, various treatment complete analog-to-digital conversions and surplus is amplified, and by each height level circuit Output digital code is input to time delay SYN register, and the charge packet of each height level circuit output repeats above-mentioned into next stage Process；P+1 grades, be also afterbody A-bit Flash analog-digital converter circuits, its charge packet for transmitting P grades Voltage signal is re-converted into, and carries out the analog-to-digital conversion work of afterbody, and this grade of output digital code of circuit is input into To time delay SYN register, this grade of circuit only completes analog-to-digital conversion, does not carry out surplus amplification；Time delay SYN register, it is used for Line delay alignment is entered to the digital code that each sub- pipelining-stage is exported, and the digital code of alignment is input to figure adjustment module；Number The digital code of reception is carried out shifter-adder by word correcting circuit module, its output digital code for being used to receive SYN register, with Obtain the R bit digital output codes of analog-digital converter；Wherein, R is positive integer, and P and A is the no more than positive integer of R.

8. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute The first delay circuit (17) and the second delay circuit (19) are stated using identical delay circuit, structure includes：N number of time delay buffering Unit and N number of K delay time register；Wherein, the delay code of a K delay time register~n-th K delay time register is input into End is all connected to K delay code, and control signal input is all connected to Ctrl signals；First time delay buffer cell~the N The delay code input of time delay buffer cell is connected respectively to prolonging for the delay time register of K delay time register~n-th K Slow code output end, the data output end of the first time delay buffer cell~the N time delay buffer cells is connected respectively to the 1st hand over word ~the N hand over word is simultaneously exported, the first control signal input whole of the first time delay buffer cell~the N time delay buffer cells Ctrln signals are connected to, the second control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected To Ctrl signals；Wherein, Ctrl and Ctrln is one group of reverse signal.

9. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 8, it is characterized in that, institute State includes inside compensation circuit (110)：Time delay buffer circuit and K add circuit, and time delay buffer circuit and K addition electricity The time delay on road must be equal；Compensation circuit (110) can operate at two kinds of the pattern of being calibrated and compensated under the control of Ctrl signals Pattern；

When in the calibration mode, effectively, the K output of add circuit will be invalid for Ctrl signals, and the 3rd N calibration code is slow through time delay Rush after circuit and obtain N output code and export；

When in the compensation mode, effectively, the K output of add circuit will be effective, and N-K hand over word is slow through time delay for Ctrln signals Rush after circuit and obtain N-K output code and export, K hand over word is added by K add circuit with K compensation codes and obtains K Output code is simultaneously exported.

10. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute Stating control circuit (13) includes：Core control circuit, ROM reading circuits, first postpone code and produce circuit, second to postpone code generation Circuit, compensation codes produce circuit, option code to produce circuit, computing circuit, SRAM read/write circuits and K bit registers；

The annexation of foregoing circuit is：First output end of core control circuit is connected to the input of ROM reading circuits, core Second output end of heart control circuit is connected to the control signal that the first delay code produces circuit, the 3rd of core control circuit the Output end is connected to the control signal that the second delay code produces circuit, and the 4th output end of core control circuit is connected to compensation Code produces the control signal of circuit, the 5th output end of core control circuit to be connected to the control signal of computing circuit, core 6th output end of heart control circuit is connected to the control signal that option code produces circuit, the 7th output of core control circuit End produces the 8th output end of calibration control signal Ctrl, core control circuit to be connected to K bit registers and SRAM read-writes simultaneously The control signal of circuit, the input of core control circuit is connected to calibration and starts control signal；ROM reading circuits are according to core The control instruction of heart control circuit produces ROM address codes；The data input pin of computing circuit receives SRAM read/write circuit output ends The data of transmission, and K error codes, the 2nd K error codes and the 3rd K is produced according to the control instruction of core control circuit Position error codes；First postpone that code produces that the data input pin of circuit receives that computing circuit data output end sends the first K miss Difference code, and a K delay code is produced according to the control instruction of core control circuit；Second postpones code produces the data of circuit defeated Enter end and receive the 2nd K error codes that computing circuit data output end sends, and produced according to the control instruction of core control circuit Raw 2nd K delay code；Compensation codes produce that the data input pin of circuit receives that computing circuit data output end sends the 3rd K Error codes, and K compensation codes are produced according to the control instruction of core control circuit；Option code produces circuit to control electricity according to core The control instruction on road produces a K option code and the 2nd K option code；The data input pin of K bit registers receives described K The K quantization code that the output end of charge-domain analog-digital converter (12) sends, and will be deposited according to the control instruction of core control circuit Data is activation inside Chu Qi gives SRAM read/write circuits；SRAM read/write circuits are produced according to the control instruction of core control circuit SRAM address dates code, digital independent and write-in are carried out to SRAM module (14).