CN106933299A - Low-power consumption DDS circuit with amplitude and phase error self-calibration function - Google Patents

Low-power consumption DDS circuit with amplitude and phase error self-calibration function Download PDF

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CN106933299A
CN106933299A CN201710135908.7A CN201710135908A CN106933299A CN 106933299 A CN106933299 A CN 106933299A CN 201710135908 A CN201710135908 A CN 201710135908A CN 106933299 A CN106933299 A CN 106933299A
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circuit
code
calibration
charge
output
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CN106933299B (en
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陈珍海
吕海江
周德金
万书芹
鲍婕
宁仁霞
孙剑
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Huangshan University
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Huangshan University
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/02—Digital function generators
    • G06F1/022—Waveform generators, i.e. devices for generating periodical functions of time, e.g. direct digital synthesizers

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Abstract

The invention provides a kind of low-power consumption DDS circuit with amplitude and phase error self-calibration function, the DDS circuit includes：Charge-domain range error detection amplifying circuit, charge-domain phase error detection amplifying circuit, K charge-domain analog-digital converter, control circuit, ROM module, SRAM module, phase accumulator, the first delay circuit, phase amplitude converter, the second delay circuit, compensation circuit and N current-mode DAC.The low-power consumption DDS circuit with amplitude and phase error self-calibration function can be according to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and with low-power consumption feature.

Description

Low-power consumption DDS circuit with amplitude and phase error self-calibration function
Technical field
It is specifically a kind of that there is amplitude and phase error self-calibration function the present invention relates to a kind of error calibration circuit Low-power consumption DDS circuit.
Background technology
Direct digital frequency synthesis technology is a kind of signal for synthesizing required various different frequencies by digital means, The technology of analog signal output is converted thereof into finally by digital analog converter.The technology with its it is peculiar the characteristics of：Can compile Journey, frequency hopping are fast, high resolution, frequency modulation high precision the advantages of and turn into one of major technique in current frequency synthesis technique, extensively It is general to be applied to the communication fields such as mobile communication, military and commercial radar system.
Direct Digital Frequency Synthesizers (DDS) are mainly made up of three modules：Phase accumulator, phase amplitude converter and Digital analog converter (DAC).Whole DDS systems generally have two input quantities：Reference clock fs and frequency control word X.It is phase-accumulated Device, when each clock pulses is input into, linear phase is constantly carried out to frequency control word and added up under the control of clock.Phase The data of accumulator output are exactly the phase of composite signal, the output frequency i.e. direct digital synthesis technique of phase accumulator The signal frequency of device output.The phase value input phase amplitude converter of accumulator output is intercepted, is exported and is somebody's turn to do through computing conversion The corresponding digitlization range value of phase value.Digital quantity is transformed into by analog quantity by digital analog converter, then by LPF Device is smoothed and filters unwanted sampled signal, output frequency pure sine or cosine signal.
From the operation principle of DDS it will be seen that clock non-ideal characteristic, DAC input signals be asynchronous, inside DAC Module sequential is asynchronous, in power supply and circuit design the factor such as signal cross-talk that may be present influence, can cause that DAC's is defeated Go out signal and there is amplitude and phase error.In actual applications, due to fluctuation, the change of working environment etc. of processing technology, also DDS amplitudes and phase error can be made to there is certain randomness, be embodied in the amplitude and phase error of different DDS chips not It is identical to the greatest extent.In the requirement such as phased array radar carries out the application of precise control to DDS amplitudes and phase error uniformity, DDS chips Between amplitude and phase error it is inconsistent caused by problem will cause that DDS chips cannot meet required precision.Therefore design collects There is very much realistic meaning into the high accuracy amplitude and phase error self-calibration circuit in DDS chips.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided one kind has amplitude and phase error self-correcting The low-power consumption DDS circuit of quasi- function, it has been internally integrated high-precision amplitude and phase error self-calibration circuit.
The purpose of the present invention can be achieved through the following technical solutions, described with amplitude and phase error self calibration work( The low-power consumption DDS circuit of energy, its structure includes：Charge-domain range error detection amplifying circuit, charge-domain phase error detection are put Big circuit, K charge-domain analog-digital converter, control circuit, ROM module, SRAM module, phase accumulator, the first delay circuit, Phase amplitude converter, the second delay circuit, compensation circuit and N current-mode DAC；
First, second input of charge-domain phase error detection amplifying circuit is connected respectively to the N letter of current-mode DAC Number output difference port, the control signal of charge-domain phase error detection amplifying circuit is connected to a K of control circuit Option code output port, the differential voltage output end of charge-domain phase error detection amplifying circuit is connected to K charge-domain modulus The differential voltage input of converter；First, second input of charge-domain range error detection amplifying circuit is connected respectively to N The signal output difference port of position current-mode DAC, the control signal of charge-domain range error detection amplifying circuit is connected to control 2nd K option code output port of circuit processed, the differential voltage output end connection of charge-domain range error detection amplifying circuit To the K differential voltage input of charge-domain analog-digital converter；Control is arrived in the K K of charge-domain analog-digital converter quantization code output The error input port of circuit processed；
Control the ROM control ports output control signal of circuit to ROM module, control the SRAM control ports output of circuit Control signal is connected to the second of the first delay circuit and is input into SRAM module, a K delay code output end of control circuit Port, control circuit the 2nd K postpone code output end and be connected to the second input port of the second delay circuit, control circuit Calibration control signal Ctrl output ports are connected to charge-domain phase error detection amplifying circuit, K charge-domain modulus and turn simultaneously The calibration control signal Ctrl input ports of parallel operation, compensation circuit, the first delay circuit and the second delay circuit；
The first input port of the first delay circuit connects a N calibration code output end of ROM module, the first deferred telegram 3rd input port on road connects X phase controlling input code of phase accumulator, and the output port of the first delay circuit is by X Phase amplitude converter is arrived in hand over word output；2nd N calibration of the first input port connection ROM module of the second delay circuit Code output end, the N amplitude control input code of the 3rd input port connection phase amplitude controller output of the second delay circuit, N hand over word output is arrived compensation circuit by the output port of the second delay circuit；The first input port connection ROM of compensation circuit 3rd N calibration code output end of module, the 3rd input port of compensation circuit connects N conversion of the second delay circuit output N output code output is arrived the N data input pin of current-mode DAC by code, the output port of compensation circuit；Wherein, N is just whole Number, K is the no more than positive integer of N.
The low-power consumption DDS circuit with amplitude and phase error self-calibration function, its mode of operation includes calibrating die Formula and compensation model；And calibration mode is introduced into when circuit works, afterwards into compensation model；When calibration mode is entered, X Position phase controlling input code, N amplitude control input code, N output code, K delay code, the 2nd K delay code and K Compensation codes are invalid, and a N calibration code is input to the first delay circuit, and the 2nd N calibration code is input to the second delay circuit, 3rd N calibration code is input to compensation circuit；The charge-domain range error calibration circuit first carries out width to N current-mode DAC Degree calibrates for error, and then the charge-domain phase error calibration circuit enters to N current-mode DAC and phase amplitude converter successively Line phase calibrates for error；When compensation model is entered, X phase controlling input code is input to the first delay circuit, N amplitude control Input code processed is input to the second delay circuit, and N output code is input to compensation circuit；First N calibration code, the 2nd N calibration Code and the 3rd N calibration code it is invalid, the first K delay code, the 2nd K delay code and K compensation codes it is effective；The charge-domain width Degree error calibration circuit starts to carry out N current-mode DAC range error compensation, and the charge-domain phase error calibration circuit is same When phase compensation is carried out to N current-mode DAC and phase amplitude converter.
The low-power consumption DDS circuit with amplitude and phase error self-calibration function, it is to the N current-mode DAC When carrying out range error calibration, the job order of circuit is as follows：
Control circuit controls charge-domain range error to detect amplifying circuit, K charge-domain modulus first by Ctrl signals Converter and compensation circuit enter calibration mode, while export the 2nd K option code amplifies electricity to the detection of charge-domain range error Road；
Then control circuit produces first group of the 2nd K option code, while controlling ROM module to produce first group the 3rd N Calibration code；First group of the 3rd N calibration code is into compensation circuit and obtains N output code, and N output code enters N to be calibrated Position current-mode DAC-circuit, obtains first group of range error difference output corresponding with the 3rd N calibration code electric through digital-to-analogue conversion Stream；Charge-domain range error detection amplifying circuit is by detecting first group of range error differential output current amount, and treatment is obtained First grouping error voltage；First grouping error voltage is carried out analog-to-digital conversion by K charge-domain analog-digital converter, can obtain first group Range error K quantization code is simultaneously exported to control circuit；Reception is obtained first group of range error K quantization code and deposited by control circuit In SRAM module, the range error completed under a kind of input condition quantifies for storage；
And then, control circuit can produce second group of the 2nd K option code and control ROM module generation second group the simultaneously Three N calibration code, second group of the 3rd N calibration code is into compensation circuit and obtains N output code, and N output code enters treats school N accurate current-mode DAC-circuit, second group of range error corresponding with second group of the 3rd N calibration code is obtained through digital-to-analogue conversion Differential output current；Charge-domain range error detects amplifying circuit by comparing second group of differential output current and second group of benchmark Simultaneously be amplified for its difference can obtain the second grouping error voltage by voltage；K charge-domain analog-digital converter is by the second grouping error Voltage carries out analog-to-digital conversion, can obtain second group of range error K quantization code and export to control circuit；Control circuit will connect Receipts obtain second group of range error K quantization code storage in SRAM module, complete the range error under second input condition Quantify；
Circulate according to this, when control circuit produces the K option code of L groups the 2nd and simultaneously control ROM module generation L groups the Three N calibration code, and obtain K quantization code of L group range errors, and after storing in SRAM module, inside control circuit Computing circuit will carry out being calculated K compensation codes to the K quantization code of L group range errors stored in SRAM module；Control Circuit processed can be now exported in compensation circuit K compensation codes, and compensation circuit is arranged to compensate for into pattern, while keeping K Position compensation codes are constant；So far, complete to the N calibration of current-mode DAC range errors；
In above-mentioned calibration process, the 3rd N calibration code of each group of output that control circuit is produced simultaneously to compensation circuit Must be corresponded to the 2nd K option code of charge-domain range error detection amplifying circuit with output, i.e.,：J groups the 3rd N Calibration code must be used cooperatively with the K option code of J groups the 2nd；Wherein, L is no more than 2KPositive integer；J is no more than L Positive integer.
The low-power consumption DDS circuit with amplitude and phase error self-calibration function, it is to the N current-mode DAC When carrying out phase error calibration with phase amplitude converter, the job order of circuit is as follows：
1st, phase error calibration is carried out to N current-mode DAC first：
1.1 control circuits control charge-domain phase error detection amplifying circuit and the second delay circuit to enter by Ctrl signals Enter calibration mode, while exporting a K option code gives charge-domain phase error detection amplifying circuit, start to N current-mode DAC carries out phase error calibration；
Then 1.2 control circuit to produce first group of the first K option code, while controlling ROM module to produce first group of the 2nd N Position calibration code；First group of the 2nd N calibration code is into the second delay circuit and obtains N hand over word, and N hand over word enters treats school Quasi- N current-mode DAC-circuit, obtains first group of phase error corresponding with first group of the 2nd N calibration code poor through digital-to-analogue conversion Divide output current；Charge-domain phase error detection amplifying circuit passes through first group of phase error differential output current amount of detection, and Process and obtain first group of phase error voltage；First group of phase error voltage is carried out mould by K charge-domain analog-digital converter Number conversion, can obtain first group of phase error K quantization code and export to control circuit；Reception is obtained first by control circuit The K quantization code storage of group phase error completes N current-mode DAC-circuit phase under a kind of input condition in SRAM module Error quantization；
1.3 and then, and control circuit produces second group of the first K option code, while controlling ROM module generation second group the Two N calibration code；Second group of the 2nd N calibration code is into the second delay circuit and obtains N hand over word, and N hand over word enters N current-mode DAC-circuit to be calibrated, second group of phase corresponding with second group of the 2nd N calibration code is obtained through digital-to-analogue conversion Error differential output current；Charge-domain phase error detection amplifying circuit is by detecting second group of phase error differential output current Amount, and process and obtain second group of phase error voltage；K charge-domain analog-digital converter enters second group of phase error voltage Row analog-to-digital conversion, can obtain second group of phase error K quantization code and export to control circuit；Control circuit obtains reception Second group of phase error K quantization code storage completes N to be calibrated current-mode under two kinds of input conditions in SRAM module DAC-circuit phase error quantifies；
1.4 circulate according to this, when control circuit produces the N calibration code of L groups the 2nd and the K option code of L groups the, and obtain To K quantization code of L group phase errors, and after storing in SRAM module, the computing circuit inside control circuit will be to depositing Storing up the K quantization code of L group phase errors in K bit register groups carries out being calculated the 2nd K delay code；Control circuit is now Meeting exports in the second delay circuit the 2nd K delay code, and keeps the 2nd K delay code constant, controls circuit by second Delay circuit is arranged to compensate for pattern, completes to the N phase error calibration of current-mode DAC；
2nd, afterwards, control circuit controls the first delay circuit to enter calibration mode by Ctrl signals, while K choosing of output Select code and give charge-domain phase error detection amplifying circuit, start to carry out phase error calibration to phase amplitude converter；
Control circuit control ROM module produces a N calibration code, by the first delay circuit, charge-domain phase error Detection amplifying circuit and K charge-domain analog-digital converter, using and to the N phase error calibration identical step of current-mode DAC Rapid and method, obtains a K delay code and exports in the first delay circuit, while keep a K delay code constant, control First delay circuit is arranged to compensate for pattern by circuit processed, completes the phase error calibration to phase amplitude converter；Now, school Quasi-mode terminates；
In above-mentioned phase error calibration process, an each group of N calibration code and the 2nd N that control circuit is produced simultaneously Position calibration code and output must be corresponded to a K option code of charge-domain phase error detection amplifying circuit, i.e.,：J The first N calibration code of group and the 2nd N calibration code must be used cooperatively with the K option code of J groups the；Wherein, L is little In 2KPositive integer, J is the no more than positive integer of L.
Further, in the low-power consumption DDS circuit with amplitude and phase error self-calibration function, described electric charge Domain phase error detection amplifying circuit includes：Current sense resistor, reference clock produce circuit, phase discriminator, loop filter and First charge-domain voltage amplifier circuit；The two ends of current sense resistor are connected respectively to charge-domain phase error detection amplifying circuit First, second input, and be connected respectively to the first and second inputs of phase discriminator；Reference clock produces circuit at K Under the control of option code, produce reference clock and be connected to the 3rd input of phase discriminator；Phase discriminator is to 3 signals of input Carry out further phase bit comparison and obtain phase error signal；Phase error signal obtains voltage by loop filter filtering to be believed Number Vi；ViAmplify by the first charge-domain voltage amplifier circuit and obtain error signal Vop and Von.
Further, in the low-power consumption DDS circuit with amplitude and phase error self-calibration function, the charge-domain Range error detection amplifying circuit includes：Current sense resistor, reference data produce circuit, the insensitive speed-sensitive switch electric capacity of common mode Differential voltage signal sampling network and the second charge-domain voltage amplifier circuit；The two ends of current sense resistor are connected respectively to electric charge Domain range error detects the first and second inputs of amplifying circuit, and is connected to the insensitive speed-sensitive switch electric capacity differential electrical of common mode Press the first and second inputs of signal sampling network；Reference data produces circuit under the K control of option code, produces difference Reference voltage is exported, and is connected to the third and fourth defeated of the insensitive speed-sensitive switch electric capacity differential voltage signal sampling network of common mode Enter end；Switching capacity differential voltage signal sampling network is further sampled to the voltage signal of 4 inputs, poor Divided voltage signal Vi+ and Vi-；Amplify by the second charge-domain voltage amplifier circuit and obtain error signal Vop and Von.
Further, in the low-power consumption DDS circuit with amplitude and phase error self-calibration function, described K Charge-domain analog-digital converter includes：The P grades of sub- level circuit of streamline based on charge-domain signal processing technology, it is used for sampling To charge packet carry out various treatment and complete analog-to-digital conversions and surplus amplifying, it is and the output digital code of each height level circuit is defeated Enter to time delay SYN register, and the charge packet of each height level circuit output enters next stage repetition said process；P+1 Level, is also afterbody A-bit Flash analog-digital converter circuits, and be re-converted into for the charge packet that P grades transmits by it Voltage signal, and the analog-to-digital conversion work of afterbody is carried out, and the output digital code of this grade of circuit is input to time delay synchronization Register, this grade of circuit only completes analog-to-digital conversion, does not carry out surplus amplification；Time delay SYN register, it is used for each subflow The digital code of water level output enters line delay alignment, and the digital code of alignment is input into figure adjustment module；Digital correction circuit The digital code of reception is carried out shifter-adder by module, its output digital code for being used to receive SYN register, is turned with obtaining modulus The R bit digital output codes of parallel operation；Wherein, R is positive integer, and P and A is the no more than positive integer of R.
Further, in the low-power consumption DDS circuit with amplitude and phase error self-calibration function, described first prolongs Slow circuit and the second delay circuit use identical delay circuit, and structure includes：N number of time delay buffer cell and N number of K delay Register；Wherein, the delay code input of a K delay time register~n-th K delay time register is all connected to K Postpone code, control signal input is all connected to Ctrl signals；The first time delay buffer cell~the N time delay buffer cell prolong Slow code input is connected respectively to the delay yard output end of the delay time register of K delay time register~n-th K, first The data output end of time delay buffer cell~the N time delay buffer cells is connected respectively to the 1st hand over word~the N hand over word simultaneously Output, the first control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected to Ctrln letters Number, the second control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected to Ctrl signals；Its In, Ctrl and Ctrln is one group of reverse signal.
Further, in the low-power consumption DDS circuit with amplitude and phase error self-calibration function, the compensation electricity Road inside includes：Time delay buffer circuit and K add circuit, and the time delay of time delay buffer circuit and K add circuit is necessary It is equal；Compensation circuit can operate under the control of Ctrl signals and be calibrated and compensated for pattern both of which；
When in the calibration mode, effectively, the K output of add circuit will be invalid, and the 3rd N calibration code is through prolonging for Ctrl signals When buffer circuit after obtain N output code and export；
When in the compensation mode, effectively, the K output of add circuit will be effective, and N-K hand over word is through prolonging for Ctrln signals When buffer circuit after obtain N-K output code and export, K hand over word is added by K add circuit with K compensation codes and obtains K output code is simultaneously exported.
Further, in the low-power consumption DDS circuit with amplitude and phase error self-calibration function, the control electricity Road includes：Core control circuit, ROM reading circuits, first postpone code and produce circuit, second to postpone code generation circuit, compensation codes Circuit, option code is produced to produce circuit, computing circuit, SRAM read/write circuits and K bit registers；
The annexation of foregoing circuit is：First output end of core control circuit is connected to the input of ROM reading circuits End, the second output end of core control circuit is connected to the control signal that the first delay code produces circuit, core control circuit The 3rd output end be connected to the second delay code produce circuit control signal, core control circuit the 4th output end connection The control signal of circuit, the 5th output end of core control circuit is produced to be connected to the control input of computing circuit to compensation codes End, the 6th output end of core control circuit is connected to the control signal that option code produces circuit, and the of core control circuit Seven output ends produce calibration control signal Ctrl, the 8th output end of core control circuit be connected to simultaneously K bit registers and The control signal of SRAM read/write circuits, the input of core control circuit is connected to calibration and starts control signal；ROM reads electricity Road produces ROM address codes according to the control instruction of core control circuit；The data input pin of computing circuit receives SRAM read-write electricity The data that road output end sends, and K error codes, a 2nd K error is produced according to the control instruction of core control circuit Code and the 3rd K error codes；First postpones code produces the data input pin of circuit to receive what computing circuit data output end sent First K error codes, and a K delay code is produced according to the control instruction of core control circuit；Second postpones code produces electricity The data input pin on road receives the 2nd K error codes that computing circuit data output end sends, and according to core control circuit Control instruction produces the 2nd K delay code；Compensation codes produce the data input pin of circuit to receive computing circuit data output end hair K error codes of the 3rd for sending, and K compensation codes are produced according to the control instruction of core control circuit；Option code produces circuit root A K option code and the 2nd K option code are produced according to the control instruction of core control circuit；The data input of K bit registers End receives the K quantization code that the output end of the K charge-domain analog-digital converter sends, and according to the control of core control circuit Instruction will be stored in its internal data is activation and give SRAM read/write circuits；Control of the SRAM read/write circuits according to core control circuit Instruction produces SRAM address dates code, and digital independent and write-in are carried out to SRAM module.
It is an advantage of the invention that：The designed low-power consumption DDS circuit with amplitude and phase error self-calibration function can According to system accuracy and the automatic compromise selection calibration accuracy of hardware spending, and with low-power consumption feature.By using charge-domain Signal processing technology, does not use operational amplifier in terms of error detection process, with low-power consumption feature；Using charge-domain ADC Error signal is quantified, error compensating method all uses Digital Signal Processing, further realize that power consumption is minimized And with low-power consumption feature.
Brief description of the drawings
Fig. 1 is low-power consumption DDS circuit block diagram of the present invention with amplitude and phase error self-calibration function.
Fig. 2 is charge-domain phase error detection amplification circuit structure block diagram of the present invention.
Fig. 3 is charge-domain voltage amplifier circuit schematic diagram of the present invention.
Fig. 4 is charge-domain voltage amplifier circuit working waveform figure of the present invention.
Fig. 5 is phase detector circuit structured flowchart of the present invention.
Fig. 6 is that reference clock of the present invention produces circuit structure block diagram.
Fig. 7 is that charge-domain range error of the present invention detects amplification circuit structure block diagram.
Fig. 8 is that reference data of the present invention produces circuit structure block diagram.
Fig. 9 is charge-domain analog-digital converter circuit block diagram of the present invention.
Figure 10 is charge-domain pipelined sub- level circuit block diagram of the present invention.
Figure 11 is delay circuit structured flowchart of the present invention.
Figure 12 is compensation circuit structured flowchart of the present invention.
Figure 13 is control circuit block diagram of the present invention.
Specific embodiment
The preferred embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
Fig. 1 show low-power consumption DDS circuit block diagram of the present invention with amplitude and phase error self-calibration function.The tool Having amplitude and the low-power consumption DDS circuit of phase error self-calibration function includes：Charge-domain range error detection amplifying circuit 10, electricity Lotus domain phase error detection amplifying circuit 11, K charge-domain analog-digital converter 12, control circuit 13, ROM module 15, SRAM moulds Block 14, phase accumulator 16, the first delay circuit 17, phase amplitude converter 18, the second delay circuit 19, compensation circuit 110 With N current-mode DAC 111.
The annexation of foregoing circuit is：First and second inputs of charge-domain phase error detection amplifying circuit 11 point The N signal output difference port of current-mode DAC 111 (to induction signal Iop and Ion), the inspection of charge-domain phase error are not connected to The control signal for surveying amplifying circuit 11 is connected to a K option code output port of control circuit 13, and charge-domain phase is missed The differential voltage output end of difference detection amplifying circuit 11 is connected to the K differential voltage input of charge-domain analog-digital converter 12； First and second inputs of charge-domain range error detection amplifying circuit 10 are connected respectively to the N letter of current-mode DAC 111 Number output difference port, the control signal of charge-domain range error detection amplifying circuit 10 is connected to the second of control circuit 13 K option code output port, the differential voltage output end of charge-domain range error detection amplifying circuit 10 is connected to K charge-domain The differential voltage input of analog-digital converter 12；Control circuit 13 is arrived in the K K of charge-domain analog-digital converter 12 quantization code output Error input port；
Control the ROM control ports output control signal of circuit 13 to ROM module 15, control the SRAM control ends of circuit 13 Mouth output control signal is connected to the first delay circuit to SRAM module 14, a K delay code output end of control circuit 13 17 the second input port, the 2nd K delay code output end of control circuit 13 is connected to the second defeated of the second delay circuit 19 Inbound port, controls the calibration control signal Ctrl output ports of circuit 13 to be connected to charge-domain phase error detection simultaneously and amplifies electricity The calibration of road 11, K charge-domain analog-digital converter 12, compensation circuit 110, the first delay circuit 17 and the second delay circuit 19 Control signal Ctrl input ports；
The first input port of the first delay circuit 17 connects a N calibration code output end of ROM module 15, and first prolongs 3rd input port of slow circuit 17 connects X phase controlling input code of phase accumulator 16, the first delay circuit 17 it is defeated X hand over word output is arrived phase amplitude converter 18 by exit port；The first input port connection ROM moulds of the second delay circuit 19 2nd N calibration code output end of block 15, the 3rd input port connection phase amplitude controller output of the second delay circuit 19 N amplitude control input code, N hand over word output arrived compensation circuit 110 by the output port of the second delay circuit 19；Compensation The first input port of circuit 110 connects the 3rd N calibration code output end of ROM module 15, the 3rd input of compensation circuit 110 N output code output is arrived N by N hand over word of the port connection output of the second delay circuit 19, the output port of compensation circuit 110 The data input pin of position current-mode DAC 111.
Low-power consumption DDS circuit with amplitude and phase error self-calibration function of the present invention, including calibration mode and Two kinds of mode of operations of compensation model.Calibration mode is introduced into when circuit works, afterwards into compensation model；Entering calibration mode When, X phase controlling input code, N amplitude control input code, N output code, K delay code, a 2nd K delay code Invalid with K compensation codes, a N calibration code is input to the first delay circuit 17, and the 2nd N calibration code is input to second and prolongs Slow circuit 19, the 3rd N calibration code is input to compensation circuit 110；The charge-domain range error calibrates circuit first to N electric current Mould DAC 111 carries out range error calibration, and then the charge-domain phase error calibrates circuit successively to N current-mode DAC 111 and phase amplitude converter 18 carry out phase error calibration；When compensation model is entered, X phase controlling input code input To the first delay circuit 17, N amplitude control input code is input to the second delay circuit 19, and it is electric that N output code is input to compensation Road 110；First N calibration code, the 2nd N calibration code and the 3rd N calibration code are invalid, the first K postpone code, the 2nd K prolong Slow code and K compensation codes are effective；The charge-domain range error calibration circuit starts to enter line amplitude to N current-mode DAC 111 Error compensation, the charge-domain phase error calibration circuit enters to N current-mode DAC 111 and phase amplitude converter 18 simultaneously Line phase is compensated.
First, low-power consumption DDS circuit of the present invention with amplitude and phase error self-calibration function is to N current-mode DAC 111 calibrating principles for carrying out range error calibration are：
When calibration mode is opened, control circuit 13 controls charge-domain range error to detect amplification first by Ctrl signals Circuit 10, K charge-domain analog-digital converter 12 and compensation circuit 110 enter calibration mode, at the same export the 2nd K option code to Charge-domain range error detects amplifying circuit 10；First group of the 2nd K option code of control circuit 13 and then generation, while control ROM module 15 produces first group of the 3rd N calibration code；First group of the 3rd N calibration code is into compensation circuit 110 and obtains N Output code, N output code enters the N circuit of current-mode DAC 111 to be calibrated, is obtained and the 3rd N calibration through digital-to-analogue conversion Code corresponding first group of range error differential output current signal Iop and Ion；Charge-domain range error detection amplifying circuit 10 leads to Cross detection Iop-Ion amount, be processed to and with first group of reference voltage produced by internal reference reference generating circuit Vrefp-Vrefn is compared, and its difference is amplified can obtain error voltage Vop-Von；K charge-domain modulus turns Error voltage Vop-Von is carried out analog-to-digital conversion by parallel operation 12, can be obtained first group of range error K quantization code and be exported to control Circuit processed 13；Reception is obtained first group of range error K quantization code storage in SRAM module 14 by control circuit 13, completes one The range error planted under input condition quantifies.
And then, control circuit 13 can produce second group of the 2nd K option code and control ROM module 15 to produce second simultaneously The 3rd N calibration code of group, second group of the 3rd N calibration code is into compensation circuit 110 and obtains N output code, and N output code enters Enter the N circuit of current-mode DAC 111 to be calibrated, obtained and second group of the 3rd N calibration code corresponding second through digital-to-analogue conversion Group range error differential output current；Charge-domain range error detects amplifying circuit 10 by comparing second group of differential output current Being amplified with second group of reference voltage and by its difference can obtain the second grouping error voltage Vop-Von；K charge-domain modulus Second grouping error voltage Vop-Von is carried out analog-to-digital conversion by converter 12, can obtain second group of range error K quantization code simultaneously Export control circuit 13；Reception is obtained second group of range error K quantization code storage in SRAM module 14 by control circuit 13 In, the range error completed under second input condition quantifies.
Circulate according to this, when control circuit 13 produces the K option code of L groups the 2nd and controls ROM module 15 to produce L simultaneously After the 3rd N calibration code of group, and obtains K quantization code of L group range errors, and storage is in the SRAM module 14, control circuit Computing circuit inside 13 will carry out being calculated K to the K quantization code of L group range errors stored in SRAM module 14 Compensation codes.
Control circuit 13 can be now exported in compensation circuit 110 K compensation codes, and compensation circuit 110 is arranged to Compensation model, while keeping K compensation codes constant.The low-power consumption DDS electricity with amplitude and phase error self-calibration function Road is completed to the N calibration of the range errors of current-mode DAC 111.
In above-mentioned calibration process, each group of output that control circuit 13 is produced simultaneously to the 3rd N school of compensation circuit 110 Quasi- code and output must be corresponded to the 2nd K option code of charge-domain range error detection amplifying circuit 10, i.e.,：J groups 3rd N calibration code must must be used cooperatively with the K option code of J groups the 2nd, wherein, L is no more than 2KPositive integer, J To be not more than the positive integer of L.
2nd, the low-power consumption DDS circuit with amplitude and phase error self-calibration function of the present invention is to N current-mode The calibrating principle that DAC 111 and phase amplitude converter 18 carry out phase error calibration is：
The low-power consumption DDS circuit with amplitude and phase error self-calibration function is completed to N current-mode DAC 111 After the calibration of range error, control circuit 13 controls charge-domain phase error detection amplifying circuit 11 and second by Ctrl signals Delay circuit 19 enters calibration mode, while exporting a K option code to charge-domain phase error detection amplifying circuit 11, opens Beginning carries out phase error calibration to N current-mode DAC 111.
Then control circuit 13 produces first group of the first K option code, while controlling ROM module 15 to produce first group second N calibration code；First group of the 2nd N calibration code is into the second delay circuit 19 and obtains N hand over word, and N hand over word enters N current-mode DAC 111 circuits to be calibrated, first group of phase corresponding with first group of the 2nd N calibration code is obtained through digital-to-analogue conversion Position error differential output current Iop and Ion；Charge-domain phase error detection amplifying circuit 11 is measured by detecting Iop-Ion, by it Process and produce first group of reference clock produced by circuit 21 to carry out phase-detection with internal reference clock, and by its phase Difference is amplified can obtain error voltage Vop-Von；K charge-domain analog-digital converter 12 enters error voltage Vop-Von Row analog-to-digital conversion, can obtain first group of phase error K quantization code and export to control circuit 13；Control circuit 13 will be received First group of phase error K quantization code storage is obtained in SRAM module 14, N current-mode under a kind of input condition is completed The current phase error quantizations of DAC 111.
And then, control circuit 13 produces second group of the first K option code, while controlling ROM module 15 to produce second group 2nd N calibration code；Second group of the 2nd N calibration code is into the second delay circuit 19 and obtains N hand over word, N hand over word Into the N circuit of current-mode DAC 111 to be calibrated, obtained and second group of the 2nd N calibration code corresponding through digital-to-analogue conversion Two groups of differential output currents Iop and Ion；Charge-domain phase error detection amplifying circuit 11 is measured by detecting Iop-Ion, is located Manage and produce second group of reference clock produced by circuit 21 to carry out phase-detection with internal reference clock, and by its phase difference Value is amplified can obtain error voltage Vop-Von；K charge-domain analog-digital converter 12 carries out error voltage Vop-Von Analog-to-digital conversion, can obtain second group of phase error K quantization code and export to control circuit 13；Control circuit 13 will be received To second group of phase error K quantization code storage in SRAM module 14, N to be calibrated electric current under two kinds of input conditions is completed The current phase error quantizations of mould DAC 111.
Circulate according to this, when controller produces the N calibration code of L groups the 2nd and the K option code of L groups the, and obtain L Group K quantization code of phase error, and after storing in the SRAM module 14, the computing circuit inside control circuit 13 will be to storing K quantization code of L group phase errors in K bit register groups carries out being calculated the 2nd K delay code.Control circuit 13 is now Can by the 2nd K postpone code output in the second delay circuit 19, and keep the 2nd K to postpone code constant, control circuit 13 by Second delay circuit 19 is arranged to compensate for pattern, completes to the N phase error calibration of current-mode DAC 111.
Afterwards, control circuit 13 controls the first delay circuit 17 to enter calibration mode by Ctrl signals, while output K Option code starts to carry out phase error calibration to phase amplitude converter 18 to charge-domain phase error detection amplifying circuit 11. The control control ROM module 15 of circuit 13 produces a N calibration code, is examined by the first delay circuit 17, charge-domain phase error Amplifying circuit 11 and K charge-domain analog-digital converter 12 are surveyed, using and to the N phase error calibration phase of current-mode DAC 111 Same step and method, obtains a K delay code and exports in the first delay circuit 17, while keeping a K delay Code is constant, and the first delay circuit 17 is arranged to compensate for pattern by control circuit 13, completes the phase to phase amplitude converter 18 Calibrate for error.
Now, the calibration mode of the low-power consumption DDS circuit with amplitude and phase error self-calibration function terminates.
In above-mentioned phase error calibration process, each group of N calibration code and that control circuit 13 is produced simultaneously Two N calibration code and output must be corresponded to a K option code of charge-domain phase error detection amplifying circuit 11, I.e.：The N calibration code of J groups the first and the 2nd N calibration code must must be used cooperatively with the K option code of J groups the.
Low-power consumption DDS circuit with amplitude and phase error self-calibration function of the present invention is in actually used process In, can be different according to selection with the precision, hardware spending size that phase error is calibrated with prover time length to DDS amplitudes K and L values are configured, to meet the calibration accuracy and rate request of different accuracy and speed DDS chips.
Fig. 2 is a kind of implementation of charge-domain phase error detection amplifying circuit 11 of the present invention.The circuit includes：Electric current Detection resistance Rd, reference clock produce circuit 21, phase discriminator 22, the charge-domain voltage amplifier circuit of loop filter 23 and first 24.The two ends of current sense resistor Rd are connected respectively to first, second input of charge-domain phase error detection amplifying circuit 11 End, and it is connected to first, second input Voutp and Voutn of phase discriminator 22；Reference clock produces circuit 21 in K selection Under the control of code, produce reference clock Clkref and be connected to the 3rd input of phase discriminator 22；3 inputs of phase discriminator 22 pair Signal carry out further phase bit comparison and obtain phase error signal Vp, phase error signal Vp is filtered by loop filter 23 Ripple obtains voltage signal Vi；Amplify by the first charge-domain voltage amplifier circuit 24 and obtain error signal Vop and Von.
Fig. 3 show the schematic diagram of the first charge-domain voltage amplifier circuit 24 of the present invention.First charge-domain voltage amplification Circuit 24 includes：First anode charge-storage node Nip, the first negative terminal charge-storage node Nin, the second anode electric charge storage section Point Nop and the second negative terminal charge-storage node Non, one be connected to the first and second anode charge-storage node Nip and Nop it Between anode electric charge transmission controlling switch 301, be connected between the first and second negative terminal charge-storage node Nin and Non Negative terminal electric charge transmission controlling switch 302, be connected to the anode electric capacity 303 of the first anode charge-storage node Nip, be connected to the The anode capacitance programmable capacitor 309 of two anode charge-storage node Nop, it is connected to the first negative terminal charge-storage node Nin's Negative terminal electric capacity 304, the negative terminal capacitance programmable capacitor 310 for being connected to the second negative terminal charge-storage node Non, it is being connected to first just The first positive terminal voltage transmitting switch 305 of end charge-storage node Nip, be connected to the first anode charge-storage node Nip the Two positive terminal voltage transmitting switches 307, the 3rd positive terminal voltage transmitting switch 313 for being connected to the second anode charge-storage node Nop Deposited with being connected to the 4th positive terminal voltage transmitting switch 311 of the second anode charge-storage node Nop, being connected to the first negative terminal electric charge The first negative terminal voltage transmitting switch 306 of storage node Nin, the second negative terminal electricity for being connected to the first negative terminal charge-storage node Nin Transmitting switch 308 is pressed, the 3rd negative terminal voltage transmitting switch 314 of the second negative terminal charge-storage node Non is connected to and is connected to The 4th negative terminal voltage transmitting switch 312 of the second negative terminal charge-storage node Non.For the embodiment of the present invention, the first charge-domain Either end connection Vi in two analog voltage inputs of voltage amplifier circuit 24, other end connects reality by reference signal It is existing.
Fig. 4 is the work schedule control waveform diagram of circuit shown in Fig. 3.It is opposite in phase to control clock Clk and Clkn Clock, switch controlling signal Clkr, Clks and Clkt are that phase does not overlap clock.Heretofore described electric charge transmission control is opened Pass can realize that described voltage is passed using the implementation method described in the patent of invention of Patent No. 201010291245.6 Defeated switch can be realized using general metal-oxide-semiconductor or BJT switches.
Fig. 5 show a kind of implementation of the circuit of phase discriminator of the present invention 22.The circuit by signal shaping module and One subtractor sub-module is constituted.Input differential signal Voutp and Voutn are carried out shaping and obtain being input into phase by signal shaping module Position, used as fixed phase, input phase and fixed phase are carried out phase to the reference clock of reference clock output by subtractor sub-module Subtract, obtain phase error signal Vp.
Fig. 6 show reference clock of the present invention and produces the structured flowchart of circuit 21.The reference clock produces circuit 21 Including：One programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit.The programmable frequency adjustment circuit Controlled by K option code with the programmable duty cycle adjustment circuit.Under the K control of option code, frequency and dutycycle After fixed input clock priority is by the programmable frequency adjustment circuit and the programmable duty cycle adjustment circuit, i.e., Can obtain the reference clock Clkref of different frequency and dutycycle.
Fig. 7 is a kind of implementation that charge-domain range error of the present invention detects amplifying circuit 10, and the circuit is using complete poor Separation structure is realized.The circuit includes：Current sense resistor Rd, reference data produce the insensitive speed-sensitive switch electricity of circuit 71, common mode Tolerance divided voltage signal sampling network 72 and the second charge-domain voltage amplifier circuit 73.
The two ends of current sense resistor Rd are connected respectively to the first and the of charge-domain range error detection amplifying circuit 10 Two inputs, and it is connected to first, second input of the insensitive speed-sensitive switch electric capacity differential voltage signal sampling network 72 of common mode End Voutp and Voutn；Reference data produces circuit 71 under the K control of option code, produces differential reference voltage output end Vrefp and Vrefn, and it is connected to the third and fourth of the insensitive speed-sensitive switch electric capacity differential voltage signal sampling network 72 of common mode Input；The voltage signal of 72 pairs of 4 inputs of switching capacity differential voltage signal sampling network is further sampled, and is obtained To differential voltage signal Vi+ and Vi-；Amplify by the second charge-domain voltage amplifier circuit 73 and obtain error signal Vop and Von.
Fig. 8 show reference data of the present invention and produces circuit structure block diagram.The reference data generation circuit includes： One resistance string, a switch arrays and an output switch selection circuit.Resistance string is by 2K- 1 equal-sized resistance string Connection is formed, and its two ends connects reference voltage 3 and reference voltage 4 respectively, by 2K- 1 equal-sized electric resistance partial pressure can be obtained To 2KPlant voltage；Switch arrays include 2K- 1 voltage-selected switch, it exports one group under the control of output switch selection circuit Differential reference voltage Vrefp and Vrefn；Output switch selection circuit selects to open 2 switch arrays under the K control of option code Voltage transmitting switch in row.Reference data produces circuit to produce one group of differential reference voltage according to any one group of K option code Vrefp and Vrefn.Reference voltage 3 and reference voltage 4 shown in Fig. 8 are respectively Vref3 and Vref4 shown in Fig. 1.
As shown in figure 9, K charge-domain analog-digital converter 12 of present invention design includes：P grades is based on charge-domain signal transacting The sub- level circuit of streamline of technology, afterbody (P+1 grades) A-bit Flash analog-digital converter circuits, time delay are synchronously deposited Device and digital correction circuit module.Other mode of operation control module is also back work mould necessary to analog-digital converter work Block, the module is not identified in figure.The work of the adjacent sub- level circuit of two-stage is received in charge-domain analog-digital converter circuit in Fig. 9 The digit k of every grade of circuit of sum of series of two groups of controls of multi-phase clock, working condition complete complementary, and sub- level circuit can spirit Adjustment living.14 analog-digital converters for example for K=14, can be using 12 grades 1.5bit/ grades+1 grade of 2bit Flash totally 13 The structure of level, it would however also be possible to employ 4 grades 2.5bit/ grades+3 grades of 1.5bit/ grades+1 grade of 3bit Flash totally 8 grades of structure.
The charge-domain analog-digital converter of present invention design includes herein below：P grades is based on charge-domain signal processing technology Charge-domain pipelined sub- level circuit, it is used to carry out the charge packet that sampling is obtained various treatment completion analog-to-digital conversions and surplus is put Greatly, and by the output digital code of each height level circuit it is input to time delay SYN register, and each height level circuit output Charge packet enters next stage and repeats said process；Afterbody (P+1 grades) A-bit Flash analog-digital converter circuits, it will The P grades of charge packet for transmitting is re-converted into voltage signal, and carries out the analog-to-digital conversion work of afterbody, and by this level The output digital code of circuit is input to time delay SYN register, and this grade of circuit only completes analog-to-digital conversion, does not carry out surplus amplification；Prolong When SYN register, it is used to enter the digital code that each sub- pipelining-stage is exported line delay alignment, and the digital code alignd is defeated Enter to figure adjustment module；Digital correction circuit module, its output digital code for being used to receive SYN register, the number that will be received Character code carries out shifter-adder, to obtain the R bit digital output codes of analog-digital converter.In described above, R is positive integer, and A and P are equal To be not more than the positive integer of R.
Charge-domain pipelined sub- level circuit theory diagrams are shown in Figure 10.Circuit by fully differential signal processing channel structure Into whole circuit includes：2 this grade of electric charges transmission controlling switch, 2 charge-storage nodes, 6 be connected to charge-storage node Charge storage capacitance, C charge comparator, C by the control of comparator output result reference signal selection circuit, 2B+2 Voltage transmitting switch, wherein B are positive integer.During circuit normal work, prime differential electrical pocket is transmitted by electric charge control first Switch is transmitted and stored at this grade of charge-storage node, the voltage between the comparator node caused to the input of differential electrical pocket Difference variable quantity is compared with reference voltage 3 and reference voltage 4, obtains this grade of C and quantifies output digital code D1~DB；Numeral is defeated Going out yard D1~DB will export to time delay SYN register, while D1~DB will also respectively control the reference signal of this grade to select electricity Road, makes them produce the reference signal of a pair of complementations to control this grade of positive and negative terminal electric charge plus-minus capacitor bottom plate respectively respectively, to by preceding The differential electrical pocket that level is transferred to this grade carries out correspondingly sized plus-minus treatment, obtains this grade of differential margin charge packet；Finally, electricity The complete cost differential in road point surplus charge packet by the downward Primary Transmit of this level, enter by 2 pairs of this grade of difference charge-storage nodes of reference voltage Row resets, and completes charge-domain pipelined one work of whole clock cycle of sub- level circuit.Wherein, C is positive integer.
(P+1 grades) of the afterbody for the charge-domain pipelined analog-digital converter of present invention design in Fig. 9 is based on electricity The sub- level circuit A-bit Flash analog-digital converter circuits of streamline of lotus domain signal processing technology, it is right that the sub- level circuit will only need to The charge packet for receiving carries out the analog-to-digital conversion work of afterbody, and this grade of circuit output digital code is input into time delay synchronization Register, without carrying out surplus treatment.Remove the reference signal selection circuit in Figure 10 and controlled by reference signal selection circuit 4 electric capacity.
Figure 11 show delay circuit structured flowchart of the present invention.The delay circuit inside includes：N number of time delay Buffer cell and N number of K delay time register, the first time delay buffer cell~the N time delays buffer cell and a K delay deposit Device~n-th K delay time register.The delay code input of the first K delay time register~n-th K delay time register is complete Portion is connected to K delay code, and control signal input is all connected to Ctrl signals；First time delay buffer cell~the N time delays The delay code input of buffer cell is connected respectively to the delay code of the delay time register of K delay time register~n-th K Output end, the data output end of the first time delay buffer cell~the N time delay buffer cells is connected respectively to the 1st hand over word~the N hand over word is simultaneously exported, and the first control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected To Ctrln signals, the second control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected to Ctrl signals.Wherein, Ctrl and Ctrln is reverse clock.
Delay circuit is operable with being calibrated and compensated for pattern both of which under the control of Ctrl signals.In the calibration mode When, effectively, the 1st hand over word~the N input code is invalid, and input code is for the N output of hand over word without any for Ctrl signals Influence, the 1st calibration code~the N calibration code obtains the 1st after time delay buffer circuit 1~time delay buffer circuit N and turns respectively Escape~the N hand over word is simultaneously exported, and K postpones code and be imported into a K delay time register~n-th K delay deposit In device and be latched holding it is constant.When in the compensation mode, effectively, the 1st hand over word~the N input code has Ctrln signals Effect, and the 1st hand over word~the N hand over word is obtained after time delay buffer circuit and is exported, the 1st calibration code~the N school Quasi- code is invalid, and K stored in a K delay time register~n-th K delay time register postpones code and be imported into time delay Compensation of delay is carried out in buffer circuit 1~time delay buffer circuit N.
The delay circuit 19 of first delay circuit of the present invention 17 and second is using the delay circuit shown in Figure 11.
Figure 12 show the structured flowchart of compensation circuit of the present invention 110.The inside of the compensation circuit 110 is slow including time delay Circuit and K add circuit are rushed, and time delay buffer circuit and the K time delay of add circuit must be equal.Compensation circuit 110 exists It is operable with being calibrated and compensated for pattern both of which under the control of Ctrl signals.When in the calibration mode, Ctrl signals are effective, K The output of position add circuit will be invalid, and the 3rd N calibration code obtains N output code and export after time delay buffer circuit.Mending Repay when under pattern, effectively, the K output of add circuit will be effective, and N-K hand over word is after time delay buffer circuit for Ctrln signals Obtain N-K output code and export, K hand over word is added by K add circuit with K compensation codes and obtains K output code simultaneously Output, wherein Ctrl and Ctrln is reverse clock.
Figure 13 show the control block diagram of circuit 13 of the present invention.The control circuit 13 includes：Core control circuit, ROM reading circuits, first postpone code and produce circuit, the second delay code to produce circuit, compensation codes to produce circuit, option code to produce electricity Road, computing circuit, SRAM read/write circuits and K bit registers.
It is described control circuit 13 annexation be：First output end of core control circuit is connected to ROM reading circuits Input, the second output end of core control circuit is connected to the control signal that the first delay code produces circuit, core control 3rd output end of circuit processed is connected to the control signal that the second delay code produces circuit, the 4th output of core control circuit End is connected to the control signal that compensation codes produce circuit, and the 5th output end of core control circuit is connected to the control of computing circuit Input processed, the 6th output end of core control circuit is connected to the control signal that option code produces circuit, core control electricity 7th output end on road produces the 8th output end of calibration control signal Ctrl, core control circuit to be connected to K deposit simultaneously The control signal of device and SRAM read/write circuits, the input of core control circuit is connected to calibration and starts control signal；ROM reads Go out circuit and ROM address codes are produced according to the control instruction of core control circuit；The data input pin of computing circuit receives SRAM and reads The data that write circuit output end sends, and according to the control instruction of core control circuit produce K error codes, the 2nd K Error codes and the 3rd K error codes；First postpones code produces the data input pin of circuit to receive computing circuit data output end hair K error codes of for sending, and a K delay code is produced according to the control instruction of core control circuit；Second postpones code produces The data input pin of raw circuit receives the 2nd K error codes that computing circuit data output end sends, and controls electricity according to core The control instruction on road produces the 2nd K delay code；Compensation codes produce the data input pin of circuit to receive computing circuit data output The 3rd K error codes for sending are held, and K compensation codes are produced according to the control instruction of core control circuit；Option code produces electricity Road produces a K option code and the 2nd K option code according to the control instruction of core control circuit；The data of K bit registers Input receives the K quantization code that the output end of the K charge-domain analog-digital converter 12 sends, and according to core control circuit Control instruction will be stored in its internal data is activation and give SRAM read/write circuits；SRAM read/write circuits are according to core control circuit Control instruction produce SRAM address dates code, digital independent and write-in are carried out to SRAM module 14.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all it is of the invention spirit and Within principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.

Claims (10)

1. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function, it is characterized in that, including：Charge-domain amplitude is missed Difference detection amplifying circuit (10), charge-domain phase error detection amplifying circuit (11), K charge-domain analog-digital converter (12), control Circuit (13) processed, ROM module (15), SRAM module (14), phase accumulator (16), the first delay circuit (17), phase amplitude Converter (18), the second delay circuit (19), compensation circuit (110) and N current-mode DAC (111)；
First, second input of charge-domain phase error detection amplifying circuit (11) is connected respectively to N current-mode DAC (111) signal output difference port, the control signal of charge-domain phase error detection amplifying circuit (11) is connected to control First K option code output port of circuit (13), the differential voltage output of charge-domain phase error detection amplifying circuit (11) End is connected to the K differential voltage input of charge-domain analog-digital converter (12)；Charge-domain range error detects amplifying circuit (10) first, second input is connected respectively to the N signal output difference port of current-mode DAC (111), charge-domain amplitude The control signal of error-detecting amplifying circuit (10) is connected to the 2nd K option code output port of control circuit (13), electricity The differential voltage output end in lotus domain range error detection amplifying circuit (10) is connected to the K difference of charge-domain analog-digital converter (12) Component voltage input；Error input of the K K quantization code output of charge-domain analog-digital converter (12) to control circuit (13) Mouthful；
The ROM control ports output control signal of control circuit (13) gives ROM module (15), the SRAM controls of control circuit (13) Port output control signal gives SRAM module (14), and a K delay code output end of control circuit (13) is connected to first and prolongs Second input port of slow circuit (17), the 2nd K delay code output end of control circuit (13) is connected to the second delay circuit (19) the second input port, the calibration control signal Ctrl output ports of control circuit (13) are connected to charge-domain phase simultaneously Error-detecting amplifying circuit (11), K charge-domain analog-digital converter (12), compensation circuit (110), the first delay circuit (17) with And second delay circuit (19) calibration control signal Ctrl input ports；
First N calibration code output end of first input port connection ROM module (15) of the first delay circuit (17), first prolongs X phase controlling input code of the 3rd input port connection phase accumulator (16) of slow circuit (17), the first delay circuit (17) X hand over word output is arrived phase amplitude converter (18) by output port；First input of the second delay circuit (19) 2nd N calibration code output end of port connection ROM module (15), the 3rd input port connection phase of the second delay circuit (19) The N amplitude control input code of position amplitude controller output, the output port of the second delay circuit (19) exports N hand over word To compensation circuit (110)；3rd N calibration code output of first input port connection ROM module (15) of compensation circuit (110) End, the 3rd input port of compensation circuit (110) connects N hand over word of the second delay circuit (19) output, compensation circuit (110) N output code output is arrived the N data input pin of current-mode DAC (111) by output port；Wherein, N is positive integer, K is the no more than positive integer of N.
2. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, its Mode of operation includes calibration mode and compensation model；And calibration mode is introduced into when circuit works, afterwards into compensation model； When calibration mode is entered, X phase controlling input code, N amplitude control input yard, N output code, K delay code, 2nd K delay code and K compensation codes are invalid, and a N calibration code is input to the first delay circuit (17), the 2nd N school Quasi- code is input to the second delay circuit (19), and the 3rd N calibration code is input to compensation circuit (110)；The charge-domain amplitude is missed Difference calibration circuit first carries out range error calibration to N current-mode DAC (111), then the charge-domain phase error calibration electricity Road carries out phase error calibration to N current-mode DAC (111) and phase amplitude converter (18) successively；Entering compensation model When, X phase controlling input code is input to the first delay circuit (17), and N amplitude control input code is input to the second deferred telegram Road (19), N output code is input to compensation circuit (110)；First N calibration code, the 2nd N calibration code and the 3rd N calibration Code it is invalid, the first K postpone code, the 2nd K delay code and K compensation codes it is effective；The charge-domain range error calibrates circuit Start to carry out N current-mode DAC (111) range error compensation, the charge-domain phase error calibration circuit is simultaneously to N electricity Stream mould DAC (111) and phase amplitude converter (18) carry out phase compensation.
3. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 2, it is characterized in that, its When range error calibration is carried out to the N current-mode DAC (111), the job order of circuit is as follows：
Control circuit (13) controls charge-domain range error to detect amplifying circuit (10), K charge-domain first by Ctrl signals Analog-digital converter (12) and compensation circuit (110) enter calibration mode, while export the 2nd K option code being missed to charge-domain amplitude Difference detection amplifying circuit (10)；
Then control circuit (13) produces first group of the 2nd K option code, while controlling ROM module (15) to produce first group the 3rd N calibration code；First group of the 3rd N calibration code enters compensation circuit (110) and obtains N output code, and N output code enters to be treated N current-mode DAC (111) circuit of calibration, first group of range error corresponding with the 3rd N calibration code is obtained through digital-to-analogue conversion Differential output current；Charge-domain range error detects amplifying circuit (10) by detecting first group of range error differential output current Amount, and treatment obtains the first grouping error voltage；First grouping error voltage is carried out modulus and turned by K charge-domain analog-digital converter (12) Change, first group of range error K quantization code can be obtained and exported to control circuit (13)；Control circuit (13) obtains reception In SRAM module (14), the range error completed under a kind of input condition quantifies for first group of range error K quantization code storage；
And then, control circuit (13) can produce second group of the 2nd K option code and control ROM module (15) to produce second simultaneously The 3rd N calibration code of group, second group of the 3rd N calibration code enters compensation circuit (110) and obtains N output code, N output code Into N current-mode DAC (111) circuit to be calibrated, obtained and second group of the 3rd N calibration code corresponding through digital-to-analogue conversion Two groups of range error differential output currents；Charge-domain range error detects amplifying circuit (10) by comparing second group of difference output Simultaneously be amplified for its difference can obtain the second grouping error voltage by electric current and second group of reference voltage；K charge-domain modulus turns Second grouping error voltage is carried out analog-to-digital conversion by parallel operation (12), can obtain second group of range error K quantization code and output is arrived Control circuit (13)；Reception is obtained second group of range error K quantization code storage in SRAM module (14) by control circuit (13) In, the range error completed under second input condition quantifies；
Circulate according to this, when control circuit (13) produces the K option code of L groups the 2nd and controls ROM module (15) to produce L simultaneously After the 3rd N calibration code of group, and obtains K quantization code of L group range errors, and storage is in the SRAM module (14), control electric The internal computing circuit in road (13) will be calculated the K quantization code of L group range errors stored in SRAM module (14) Obtain K compensation codes；Control circuit (13) can be now arrived in compensation circuit (110) output of K compensation codes, and by compensation circuit (110) pattern is arranged to compensate for, while keeping K compensation codes constant；So far, complete to miss N current-mode DAC (111) amplitude Poor calibration；
In above-mentioned calibration process, control circuit (13) is while each group of output for producing is to the 3rd N school of compensation circuit (110) Quasi- code and output must be corresponded to the 2nd K option code of charge-domain range error detection amplifying circuit (10), i.e.,：J The 3rd N calibration code of group must be used cooperatively with the K option code of J groups the 2nd；Wherein, L is no more than 2KPositive integer；J is The no more than positive integer of L.
4. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 2, it is characterized in that, its When phase error calibration is carried out to the N current-mode DAC (111) and phase amplitude converter (18), the job order of circuit It is as follows：
1st, phase error calibration is carried out to N current-mode DAC (111) first：
1.1 controls circuit (13) control charge-domain phase error detection amplifying circuit (11) and the second deferred telegram by Ctrl signals Road (19) enters calibration mode, while exporting a K option code to charge-domain phase error detection amplifying circuit (11), starts Phase error calibration is carried out to N current-mode DAC (111)；
Then 1.2 control circuit (13) to produce first group of the first K option code, while controlling ROM module (15) to produce first group 2nd N calibration code；First group of the 2nd N calibration code enters the second delay circuit (19) and obtains N hand over word, N conversion Code enters N current-mode DAC (111) circuit to be calibrated, and corresponding with first group of the 2nd N calibration code the is obtained through digital-to-analogue conversion One group of phase error differential output current；Charge-domain phase error detection amplifying circuit (11) is by detecting first group of phase error Differential output current amount, and process and obtain first group of phase error voltage；K charge-domain analog-digital converter (12) is by first Group phase error voltage carries out analog-to-digital conversion, can obtain first group of phase error K quantization code and export to control circuit (13)；Reception is obtained first group of phase error K quantization code storage in SRAM module (14) by control circuit (13), completes one Plant N current-mode DAC (111) current phase error quantization under input condition；
1.3 and then, and control circuit (13) produces second group of the first K option code, while controlling ROM module (15) to produce second The 2nd N calibration code of group；Second group of the 2nd N calibration code enters the second delay circuit (19) and obtains N hand over word, and N turns Escape enters N current-mode DAC (111) circuit to be calibrated, obtains corresponding with second group of the 2nd N calibration code through digital-to-analogue conversion Second group of phase error differential output current；Charge-domain phase error detection amplifying circuit (11) is by detecting second group of phase Error differential output current amount, and process and obtain second group of phase error voltage；K charge-domain analog-digital converter (12) will Second group of phase error voltage carries out analog-to-digital conversion, can obtain second group of phase error K quantization code and export to control electricity Road (13)；Reception is obtained second group of phase error K quantization code storage in SRAM module (14) by control circuit (13), is completed N to be calibrated current-mode DAC (111) current phase error quantization under two kinds of input conditions；
1.4 circulate according to this, when control circuit (13) produces the N calibration code of L groups the 2nd and the K option code of L groups the, and obtain To K quantization code of L group phase errors, and after storing in SRAM module (14), the internal computing circuit of control circuit (13) Will the K quantization code of L group phase errors that stored in K bit register groups be carried out being calculated the 2nd K delay code；Control Circuit (13) can be now exported in the second delay circuit (19) the 2nd K delay code, and keeps the 2nd K delay code not Become, the second delay circuit (19) is arranged to compensate for pattern by control circuit (13), complete to the N phase of current-mode DAC (111) Calibrate for error；
2nd, afterwards, control circuit (13) controls the first delay circuit (17) to enter calibration mode by Ctrl signals, while exporting K Position option code starts to carry out phase error to phase amplitude converter (18) to charge-domain phase error detection amplifying circuit (11) Calibration；
Control circuit (13) controls ROM module (15) to produce a N calibration code, by the first delay circuit (17), charge-domain Phase error detection amplifying circuit (11) and K charge-domain analog-digital converter (12), using and to N current-mode DAC (111) Phase error calibrates identical step and method, obtains a K delay code and exports in the first delay circuit (17), while Keep a K delay code constant, control circuit (13) that the first delay circuit (17) is arranged to compensate for into pattern, complete to phase The phase error calibration of amplitude converter (18)；Now, calibration mode terminates；
In above-mentioned phase error calibration process, control circuit (13) is while an each group of N calibration code and the 2nd N of generation Position calibration code and output must be corresponded to a K option code of charge-domain phase error detection amplifying circuit (11), i.e.,： The N calibration code of J groups the first and the 2nd N calibration code must be used cooperatively with the K option code of J groups the；Wherein, L is No more than 2KPositive integer, J is the no more than positive integer of L.
5. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute Charge-domain phase error detection amplifying circuit (11) stated includes：Current sense resistor, reference clock produce circuit (21), phase demodulation Device (22), loop filter (23) and the first charge-domain voltage amplifier circuit (24)；The two ends of current sense resistor connect respectively To first, second input of charge-domain phase error detection amplifying circuit (11), and it is connected respectively to the of phase discriminator (22) One and second input；Reference clock produces circuit (21) under the K control of option code, produces reference clock and is connected to mirror 3rd input of phase device (22)；Phase discriminator (22) carries out further phase bit comparison and obtains phase to 3 signals of input Error signal；Phase error signal obtains voltage signal V by loop filter (23) filteringi；ViBy the first charge-domain voltage Amplifying circuit (24) amplification obtains error signal Vop and Von.
6. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute State charge-domain range error and detect that amplifying circuit (10) includes：Current sense resistor, reference data produce circuit (71), common mode not Sensitive speed-sensitive switch electric capacity differential voltage signal sampling network (72) and the second charge-domain voltage amplifier circuit (73)；Current detecting The two ends of resistance are connected respectively to the first and second inputs of charge-domain range error detection amplifying circuit (10), and are connected to First and second inputs of the insensitive speed-sensitive switch electric capacity differential voltage signal sampling network (72) of common mode；Reference data is produced Circuit (71) produces differential reference voltage output, and be connected to the insensitive speed-sensitive switch electricity of common mode under the K control of option code Third and fourth input of tolerance divided voltage signal sampling network (72)；Switching capacity differential voltage signal sampling network is to 4 The voltage signal of individual input is further sampled, and obtains differential voltage signal Vi+ and Vi-；By the second charge-domain voltage Amplifying circuit (73) amplification obtains error signal Vop and Von.
7. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute The K charge-domain analog-digital converter (12) stated includes：The P grades of sub- level circuit of streamline based on charge-domain signal processing technology, its For being carried out to the charge packet that obtains of sampling, various treatment complete analog-to-digital conversions and surplus is amplified, and by each height level circuit Output digital code is input to time delay SYN register, and the charge packet of each height level circuit output repeats above-mentioned into next stage Process；P+1 grades, be also afterbody A-bit Flash analog-digital converter circuits, its charge packet for transmitting P grades Voltage signal is re-converted into, and carries out the analog-to-digital conversion work of afterbody, and this grade of output digital code of circuit is input into To time delay SYN register, this grade of circuit only completes analog-to-digital conversion, does not carry out surplus amplification；Time delay SYN register, it is used for Line delay alignment is entered to the digital code that each sub- pipelining-stage is exported, and the digital code of alignment is input to figure adjustment module；Number The digital code of reception is carried out shifter-adder by word correcting circuit module, its output digital code for being used to receive SYN register, with Obtain the R bit digital output codes of analog-digital converter；Wherein, R is positive integer, and P and A is the no more than positive integer of R.
8. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute The first delay circuit (17) and the second delay circuit (19) are stated using identical delay circuit, structure includes：N number of time delay buffering Unit and N number of K delay time register；Wherein, the delay code of a K delay time register~n-th K delay time register is input into End is all connected to K delay code, and control signal input is all connected to Ctrl signals；First time delay buffer cell~the N The delay code input of time delay buffer cell is connected respectively to prolonging for the delay time register of K delay time register~n-th K Slow code output end, the data output end of the first time delay buffer cell~the N time delay buffer cells is connected respectively to the 1st hand over word ~the N hand over word is simultaneously exported, the first control signal input whole of the first time delay buffer cell~the N time delay buffer cells Ctrln signals are connected to, the second control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected To Ctrl signals；Wherein, Ctrl and Ctrln is one group of reverse signal.
9. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 8, it is characterized in that, institute State includes inside compensation circuit (110)：Time delay buffer circuit and K add circuit, and time delay buffer circuit and K addition electricity The time delay on road must be equal；Compensation circuit (110) can operate at two kinds of the pattern of being calibrated and compensated under the control of Ctrl signals Pattern；
When in the calibration mode, effectively, the K output of add circuit will be invalid for Ctrl signals, and the 3rd N calibration code is slow through time delay Rush after circuit and obtain N output code and export；
When in the compensation mode, effectively, the K output of add circuit will be effective, and N-K hand over word is slow through time delay for Ctrln signals Rush after circuit and obtain N-K output code and export, K hand over word is added by K add circuit with K compensation codes and obtains K Output code is simultaneously exported.
10. there is the low-power consumption DDS circuit of amplitude and phase error self-calibration function as claimed in claim 1, it is characterized in that, institute Stating control circuit (13) includes：Core control circuit, ROM reading circuits, first postpone code and produce circuit, second to postpone code generation Circuit, compensation codes produce circuit, option code to produce circuit, computing circuit, SRAM read/write circuits and K bit registers；
The annexation of foregoing circuit is：First output end of core control circuit is connected to the input of ROM reading circuits, core Second output end of heart control circuit is connected to the control signal that the first delay code produces circuit, the 3rd of core control circuit the Output end is connected to the control signal that the second delay code produces circuit, and the 4th output end of core control circuit is connected to compensation Code produces the control signal of circuit, the 5th output end of core control circuit to be connected to the control signal of computing circuit, core 6th output end of heart control circuit is connected to the control signal that option code produces circuit, the 7th output of core control circuit End produces the 8th output end of calibration control signal Ctrl, core control circuit to be connected to K bit registers and SRAM read-writes simultaneously The control signal of circuit, the input of core control circuit is connected to calibration and starts control signal；ROM reading circuits are according to core The control instruction of heart control circuit produces ROM address codes；The data input pin of computing circuit receives SRAM read/write circuit output ends The data of transmission, and K error codes, the 2nd K error codes and the 3rd K is produced according to the control instruction of core control circuit Position error codes；First postpone that code produces that the data input pin of circuit receives that computing circuit data output end sends the first K miss Difference code, and a K delay code is produced according to the control instruction of core control circuit；Second postpones code produces the data of circuit defeated Enter end and receive the 2nd K error codes that computing circuit data output end sends, and produced according to the control instruction of core control circuit Raw 2nd K delay code；Compensation codes produce that the data input pin of circuit receives that computing circuit data output end sends the 3rd K Error codes, and K compensation codes are produced according to the control instruction of core control circuit；Option code produces circuit to control electricity according to core The control instruction on road produces a K option code and the 2nd K option code；The data input pin of K bit registers receives described K The K quantization code that the output end of charge-domain analog-digital converter (12) sends, and will be deposited according to the control instruction of core control circuit Data is activation inside Chu Qi gives SRAM read/write circuits；SRAM read/write circuits are produced according to the control instruction of core control circuit SRAM address dates code, digital independent and write-in are carried out to SRAM module (14).
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