CN106936433A - Charge-domain phase error calibrates circuit and the DDS circuit using the calibration circuit - Google Patents

Charge-domain phase error calibrates circuit and the DDS circuit using the calibration circuit Download PDF

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CN106936433A
CN106936433A CN201710135890.0A CN201710135890A CN106936433A CN 106936433 A CN106936433 A CN 106936433A CN 201710135890 A CN201710135890 A CN 201710135890A CN 106936433 A CN106936433 A CN 106936433A
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circuit
code
calibration
charge
control
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CN106936433B (en
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陈珍海
万书芹
周德金
何宁业
刘琦
宁仁霞
吕海江
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Huangshan University
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Huangshan University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/18—Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging

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  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention provides a kind of charge-domain phase error calibration circuit and the DDS using the calibration circuit.The charge-domain phase error calibration circuit includes：Charge-domain phase error detection amplifying circuit, K charge-domain analog-digital converter, control circuit, ROM module, SRAM module and the first delay circuit and the second delay circuit.The DDS of the use charge-domain phase error calibration circuit includes：Phase accumulator, phase amplitude converter, N current-mode DAC, charge-domain phase error calibration circuit, clock generation circuit and mode control circuit.Charge-domain phase error calibration circuit and can be according to system accuracy and the automatic compromise selection calibration accuracy of hardware spending and speed, and with low-power consumption feature using the DDS of the calibration circuit.

Description

Charge-domain phase error calibrates circuit and the DDS circuit using the calibration circuit
Technical field
The present invention relates to a kind of error calibration circuit, a kind of specifically DDS of use charge-domain signal processing technology Phase error calibrates circuit and the DDS using the calibration circuit.
Background technology
Direct digital frequency synthesis technology is a kind of signal for synthesizing required various different frequencies by digital means, The technology of analog signal output is converted thereof into finally by digital analog converter.The technology with its it is peculiar the characteristics of：Can compile Journey, frequency hopping are fast, high resolution, frequency modulation high precision the advantages of and turn into one of major technique in current frequency synthesis technique, extensively It is general to be applied to the communication fields such as mobile communication, military and commercial radar system.
Direct Digital Frequency Synthesizers (DDS) are mainly made up of three modules：Phase accumulator, phase amplitude converter and Digital analog converter (DAC).Whole DDS systems generally have two input quantities：Reference clock fs and frequency control word X.It is phase-accumulated Device, when each clock pulses is input into, linear phase is constantly carried out to frequency control word and added up under the control of clock.Phase The data of accumulator output are exactly the phase of composite signal, the output frequency i.e. direct digital synthesis technique of phase accumulator The signal frequency of device output.The phase value input phase amplitude converter of accumulator output is intercepted, is exported and is somebody's turn to do through computing conversion The corresponding digitlization range value of phase value.Digital quantity is transformed into by analog quantity by digital analog converter, then by LPF Device is smoothed and filters unwanted sampled signal, output frequency pure sine or cosine signal.
From the operation principle of DDS it will be seen that because clock non-ideal characteristic, DAC input signals are asynchronous, DAC Internal module sequential is asynchronous, in power supply and circuit design the factor such as signal cross-talk that may be present influence, DAC can be caused Output signal there is phase error.In actual applications, due to fluctuation, the change of working environment etc. of processing technology, can also DDS is there is certain phase error and there is certain randomness, be embodied in the phase error phase not to the utmost of different DDS chips Together.In the requirement such as phased array radar carries out the application of precise control to DDS phase errors uniformity, phase is missed between DDS chips Problem will cause that DDS chips cannot meet required precision caused by difference is inconsistent.Therefore integrated design is in the height in DDS chips Accurate phase error calibration circuit has realistic meaning very much.
The content of the invention
The purpose of the present invention is to overcome the deficiencies in the prior art, there is provided one kind uses charge-domain signal processing technology DDS phase errors calibration circuit and the DDS using the calibration circuit, the calibration of high-precision phase error can be realized.
The purpose of the present invention can be achieved through the following technical solutions：Described charge-domain phase error calibration circuit, its Structure includes：Charge-domain phase error detection amplifying circuit, K charge-domain analog-digital converter, control circuit, ROM module, SRAM Module and the first delay circuit and the second delay circuit；
The annexation of foregoing circuit is：The first and second inputs difference of charge-domain phase error detection amplifying circuit It is connected to the N signal output difference port of current-mode DAC, the control of charge-domain phase error detection amplifying circuit in DDS chips Input processed is connected to K option code output port of control circuit, the differential electrical of charge-domain phase error detection amplifying circuit Pressure output end is connected to the K differential voltage input of charge-domain analog-digital converter；The K K of charge-domain analog-digital converter amount Change code output to the error input port of control circuit；The ROM control port output control signals of circuit are controlled to ROM module, Control the SRAM control ports output control signal of circuit to SRAM module, a K delay code output end of control circuit connects The second input port of the first delay circuit is connected to, the 2nd K delay code output end of control circuit is connected to the second deferred telegram Second input port on road, controls the calibration control signal Ctrl output ports of circuit to be connected to the inspection of charge-domain phase error simultaneously Survey the calibration control signal Ctrl of amplifying circuit, K charge-domain analog-digital converter, the first delay circuit and the second delay circuit Input port；The first input port of the first delay circuit connects a N calibration code output end of ROM module, and first postpones 3rd input port of circuit connects X phase controlling input code, and the output port of the first delay circuit exports X hand over word To the phase amplitude converter in DDS chips；The first input port of the second delay circuit connects the 2nd N school of ROM module Quasi- code output end, the 3rd input port of the second delay circuit connects N amplitude control input code, the output of the second delay circuit The N current-mode DAC that N hand over word output is arrived in DDS chips in port；Wherein, X and N are arbitrary positive integer, and K is not for Positive integer more than N.
The charge-domain phase error calibrates circuit, and its mode of operation includes calibration mode and compensation model；And in electricity Road is introduced into calibration mode when working, afterwards into compensation model；
When calibration mode is entered, X phase controlling input code, N amplitude control input yard, a K delay code and 2nd K delay code is invalid, and a N calibration code is input to the first delay circuit, and the 2nd N calibration code is input to second and prolongs Slow circuit, charge-domain phase error calibration circuit enters to the N current-mode DAC and phase amplitude converter in DDS chips successively Line phase calibrates for error；
When compensation model is entered, X phase controlling input code and N amplitude control input code are separately input to first and prolong Slow circuit and the second delay circuit, a N calibration code and the 2nd N calibration code are invalid, a K delay code and the 2nd K Postpone code effectively, charge-domain phase error calibration circuit is changed to N current-mode DAC in DDS chips and phase amplitude simultaneously Device carries out phase compensation.
When calibration mode is entered, the job order of circuit is as follows：
1st, phase error calibration is carried out to N current-mode DAC in DDS chips first：
Control circuit controls charge-domain phase error detection amplifying circuit, K charge-domain modulus first by Ctrl signals Converter and the second delay circuit enter calibration mode, while export K option code amplifies electricity to charge-domain phase error detection Road, starts to carry out phase error calibration to N current-mode DAC in DDS chips；
Then control circuit produces first group of K option code, while controlling ROM module to produce first group of the 2nd N calibration Code, N current-mode DAC obtains first group differential output current signal Iop and Ion corresponding with first group of the 2nd N calibration code； Charge-domain phase error detection amplifying circuit is measured by detecting Iop-Ion, and is processed to obtain error voltage；K charge-domain Error voltage is carried out analog-to-digital conversion by analog-digital converter, can be obtained first group of K quantization code and be exported to control circuit；Control Reception is obtained first group of K quantization code storage in SRAM module by circuit, completes the DDS cores to be calibrated under a kind of input condition N current-mode DAC-circuit phase error in piece quantifies；
And then, control circuit produces second group of K option code, while controlling ROM module to produce second group of the 2nd N school Quasi- code, is processed by N current-mode DAC, charge-domain phase error detection amplifying circuit and K charge-domain analog-digital converter, can To obtain second group of K quantization code and export to control circuit；Reception is obtained second group of K quantization code storage and existed by control circuit In SRAM module, the N current-mode DAC-circuit phase error completed in the DDS chips to be calibrated under two kinds of input conditions quantifies；
Circulate according to this, when the N calibration code of generation L groups the 2nd and K option code of L groups, and obtain the K quantization of L groups Code, and after storing in the SRAM module, the computing circuit inside control circuit will be to storing the L groups K in K bit register groups Position quantization code carries out being calculated the 2nd K delay code；Control circuit can now postpone the 2nd K delay code output to second In circuit, and keep the 2nd K delay code constant, complete the phase error calibration to N current-mode DAC in DDS chips；
2nd, phase error calibration is carried out to the phase amplitude converter in DDS chips：
Control circuit by Ctrl signals control the first delay circuit enter calibration mode, while export K option code to Charge-domain phase error detection amplifying circuit, starts to carry out phase error calibration to the phase amplitude converter in DDS chips；
Control circuit control ROM module produces a N calibration code, by the first delay circuit, charge-domain phase error Detection amplifying circuit and K charge-domain analog-digital converter, using and to N current-mode DAC in DDS chips phase error school Accurate identical step and method, obtain a K delay code and export in the first delay circuit, while holding the K is prolonged Slow code is constant, completes the phase error calibration to the phase amplitude converter in DDS chips；Now, the charge-domain phase is missed The calibration mode of difference calibration circuit terminates；
In above-mentioned calibration process, each group the first N calibration code, the 2nd N calibration code that control circuit is produced simultaneously Must be corresponded with K option code, i.e.,：The N calibration code of J groups the first and the 2nd N calibration code must be with J groups K Option code is used cooperatively；Wherein, L is no more than 2KPositive integer, J is the no more than positive integer of L.
Further, described charge-domain phase error detection amplifying circuit includes：Current sense resistor, reference clock are produced Raw circuit, phase discriminator, loop filter and charge-domain voltage amplifier circuit；
The annexation of foregoing circuit is：The two ends of current sense resistor are connected respectively to charge-domain phase error detection and put The first input end and the second input of big circuit, and it is connected respectively to the first input end and the second input of phase discriminator；Ginseng Clock generation circuit is examined under the K control of option code, reference clock is produced and is connected to the 3rd input of phase discriminator；Phase demodulation Device carries out further phase bit comparison and obtains phase error signal to 3 signals of input；Phase error signal is by loop Filter filtering obtains voltage signal Vi；ViAmplify by charge-domain voltage amplifier circuit and obtain error signal Vop and Von.
Further, described K charge-domain analog-digital converter includes：The P grades of stream based on charge-domain signal processing technology The sub- level circuit of waterline, for being carried out to the charge packet that sampling is obtained, various treatment complete analog-to-digital conversion and surplus is amplified, and will be every The output digital code of one sub- level circuit is input to time delay SYN register, and the charge packet of each height level circuit output enters Next stage repeats said process；P+1 grades, be also afterbody A-bit Flash analog-digital converter circuits, by P grades of transmission The charge packet for coming over is re-converted into voltage signal, and carries out the analog-to-digital conversion work of afterbody, and by the defeated of this grade of circuit Go out digital code and be input to time delay SYN register, this grade of circuit only completes analog-to-digital conversion, does not carry out surplus amplification；Time delay is synchronously posted Storage, for entering line delay alignment to the digital code that each sub- pipelining-stage is exported, and is input to digital school by the digital code of alignment Positive module；Digital correction circuit module, the output digital code for receiving SYN register, the digital code of reception is shifted It is added, to obtain the R bit digital output codes of analog-digital converter；Wherein, R is positive integer, and P and A is the no more than positive integer of R.
Further, first delay circuit and the second delay circuit use identical delay circuit, and structure includes： N number of time delay buffer cell and N number of K delay time register；Wherein, a K delay time register~n-th K delay time register Delay code input be all connected to K delay code, control signal input is all connected to calibrate control signal Ctrl；The The delay code input of one time delay buffer cell~the N time delay buffer cells is connected respectively to K delay time register~the N The delay code output end of individual K delay time register, the data output end point of the first time delay buffer cell~the N time delay buffer cells The 1st hand over word~the N hand over word is not connected to and is exported, the of the first time delay buffer cell~the N time delay buffer cells One control signal input is all connected to calibrate the reverse signal Ctrln of control signal Ctrl, and the first time delay buffer cell~ Second control signal input of N time delay buffer cells is all connected to signal Ctrl.
The delay circuit can operate at and be calibrated and compensated for pattern both of which；
When in the calibration mode, effectively, the 1st hand over word~the N input code is invalid, and input code is for N for Ctrl signals The output of position hand over word has no effect, and the 1st calibration code~the N calibration code is respectively through the first time delay buffer circuit~the N The 1st hand over word~the N hand over word is obtained after time delay buffer circuit and is exported, K postpones code and be imported into a K delay In register~n-th K delay time register and be latched holding it is constant；When in the compensation mode, Ctrln signals are effective, and the 1st Position hand over word~the N input code is effective, and the 1st hand over word~the N hand over word and defeated is obtained after time delay buffer circuit Go out, the 1st calibration code~the N calibration code is invalid, stored in a K delay time register~N number of K delay time register K postpones to carry out compensation of delay during code is imported into the first time delay buffer circuit~the N time delay buffer circuits.
Further, the control circuit includes：Core control circuit, ROM reading circuits, first postpone code and produce electricity Road, second postpone code and produce circuit, option code to produce circuit, computing circuit, SRAM read/write circuits and K bit registers；
The annexation of foregoing circuit is：First output end of core control circuit is connected to the input of ROM reading circuits End, the second output end of core control circuit is connected to the control signal that the first delay code produces circuit, core control circuit The 3rd output end be connected to the second delay code produce circuit control signal, core control circuit the 4th output end connection To the control signal of computing circuit, the 5th output end of core control circuit is connected to the control input that option code produces circuit End, the 6th output end of core control circuit produces calibration control signal Ctrl, and the 7th output end of core control circuit is simultaneously The control signal of K bit registers and SRAM read/write circuits is connected to, the input of core control circuit is connected to calibration and starts Control signal；ROM reading circuits produce ROM address codes according to the control instruction of core control circuit；The data of computing circuit are defeated Enter end and receive the data that SRAM read/write circuits output end sends, and according to the control instruction of core control circuit generation the K Error codes and the 2nd K error codes；First postpones code produces the data input pin of circuit to receive computing circuit data output end hair K error codes of for sending, and a K delay code is produced according to the control instruction of core control circuit；Second postpones code produces The data input pin of raw circuit receives the 2nd K error codes that computing circuit data output end sends, and controls electricity according to core The control instruction on road produces the 2nd K delay code；Option code produces circuit to produce K according to the control instruction of core control circuit Option code；The K quantization that the output end that the data input pin of K bit registers receives the K charge-domain analog-digital converter sends Code, and give SRAM read/write circuits according to data is activation that the control instruction of core control circuit will be stored in its inside；SRAM reads Write circuit produces SRAM address dates code according to the control instruction of core control circuit, digital independent is carried out to SRAM module and is write Enter.
The DDS circuit of circuit is calibrated using above-mentioned charge-domain phase error, its structure includes that described charge-domain phase is missed Difference calibration circuit, also includes：Phase accumulator, phase amplitude converter, N current-mode DAC, clock generation circuit and pattern control Circuit processed；
The annexation of foregoing circuit is as follows：First calibration control signal output of mode control circuit is connected to phase Accumulator, the phase amplitude converter and N calibration signal control end of current-mode DAC, the second calibration control of mode control circuit Signal output part processed is connected to the calibration signal control end of clock generation circuit, the 3rd calibration control signal of mode control circuit Output end is connected to the calibration signal control end that charge-domain phase error calibrates circuit；The output of phase accumulator is connected to electric charge Domain phase error calibrates X phase controlling input code input of circuit；The phase controlling input of phase amplitude converter connects The X hand over word output end that charge-domain phase error calibrates circuit is connected to, the N amplitude control of phase amplitude converter output is defeated Enter the N amplitude control input code input that code is connected to charge-domain phase error calibration circuit；N current-mode DAC is according to One calibrates control signal, N hand over word, work clock f0 and calibrates generation output difference current signal under the control of clock fc Iop and Ion；Charge-domain phase error calibrates circuit under the control of the calibration control signals of calibration clock fc and the 3rd, by inspection Survey differential current signal Iop and Ion and processed, obtain by the X hand over word and N hand over word and difference of phase compensation Export phase amplitude converter and N current-mode DAC；Clock generation circuit is produced under the control of the second calibration control signal Raw calibration clock fc and work clock f0, work clock f0 are used to control calibration clock phase accumulator, phase amplitude converter With N current-mode DAC, calibration clock fc is for controlling phase amplitude converter, N current-mode DAC and charge-domain phase error Calibration circuit.
Described DDS circuit has two kinds of mode of operations of calibration mode and compensation model；And it is introduced into when circuit works Calibration mode, afterwards into compensation model；
When calibration mode is entered, mode control circuit controls clock generation circuit to circuit by the second calibration control signal Close work clock f0, output calibration clock fc；Mode control circuit also controls charge-domain phase by the 3rd calibration control signal Position error calibration circuit starts to carry out phase error calibration to DDS circuit；Mode control circuit is also by the first calibration control letter Number control phase accumulator, phase amplitude converter and N current-mode DAC enter calibration mode；Phase amplitude converter, electric charge Domain phase error calibration circuit and N current-mode DAC will start the calibration of DDS phase errors under the control of calibration clock fc Work；The calibration of DDS phase errors caused by the N phase error of current-mode DAC is carried out first, is then carried out phase amplitude and is turned The calibration of DDS phase errors caused by the phase error of parallel operation, now X phase controlling input code and N amplitude control input Code is in disarmed state；
When compensation model is entered, mode control circuit controls clock generation circuit to close by the second calibration control signal Calibration clock fc, output services clock f0；Mode control circuit also controls charge-domain phase to miss by the 3rd calibration control signal Difference calibration circuit starts to carry out phase error compensation to DDS circuit, by by the X of phase compensation hand over word and N hand over word And it is respectively outputted to phase amplitude converter and N current-mode DAC；Mode control circuit is also by the first calibration control signal control Phase accumulator processed, phase amplitude converter and N current-mode DAC enters normal mode of operation, phase amplitude converter and N Current-mode DAC operationally will work under the control of clock f0；X phase controlling input code and N amplitude control input code are opened Begin effective.
It is an advantage of the invention that：The high-precision phase position error calibration circuit for being proposed can be according to system accuracy and hardware spending Automatic compromise selection calibration accuracy；By using charge-domain signal processing technology, computing is not used in terms of error detection process Amplifier, with low-power consumption feature；Error signal is quantified using charge-domain ADC, error compensating method all uses number Word signal processing technology, further realizes that power consumption is minimized.
Brief description of the drawings
Fig. 1 is that charge-domain phase error of the present invention calibrates circuit block diagram.
Fig. 2 is charge-domain phase error detection amplification circuit structure block diagram of the present invention.
Fig. 3 is charge-domain voltage amplifier circuit schematic diagram of the present invention.
Fig. 4 is charge-domain voltage amplifier circuit working waveform figure of the present invention.
Fig. 5 is phase detector circuit structured flowchart of the present invention.
Fig. 6 is that reference clock of the present invention produces circuit structure block diagram.
Fig. 7 is charge-domain analog-digital converter circuit block diagram of the present invention.
Fig. 8 is charge-domain pipelined sub- level circuit block diagram of the present invention.
Fig. 9 is delay circuit structured flowchart of the present invention.
Figure 10 is present invention control circuit block diagram.
Figure 11 is the DDS circuit block diagram that use charge-domain phase error of the present invention calibrates circuit.
Specific embodiment
Preferred embodiment of the present invention scheme is described in detail below in conjunction with accompanying drawing.
Fig. 1 show charge-domain phase error calibration circuit block diagram of the present invention.The charge-domain phase error calibrates circuit Including：Charge-domain phase error detection amplifying circuit 10, K charge-domain analog-digital converter 11, control circuit 12, ROM module 14, The delay circuit 15 of SRAM module 13 and first and the second delay circuit 16.
The annexation of foregoing circuit is：First and second inputs of charge-domain phase error detection amplifying circuit 10 point The N signal output difference port of current-mode DAC 115 (to induction signal Iop and Ion), charge-domain in DDS chips are not connected to The control signal of phase error detection amplifying circuit 10 is connected to K option code output port of control circuit 12, charge-domain The differential voltage that the differential voltage output end of phase error detection amplifying circuit 10 is connected to K charge-domain analog-digital converter 11 is defeated Enter end；Error input port of the K K of the charge-domain analog-digital converter 11 quantization code output to control circuit 12；Control circuit 12 ROM control ports output control signal controls the SRAM control port output control signals of circuit 12 to give to ROM module 14 SRAM module 13, a K delay code output end of control circuit 12 is connected to the second input port of the first delay circuit 15, Control circuit 12 the 2nd K postpone code output end and be connected to the second input port of the second delay circuit 16, control circuit 12 Calibration control signal Ctrl output ports simultaneously be connected to charge-domain phase error detection amplifying circuit 10, K charge-domain mould The calibration control signal Ctrl input ports of number converter 11, the first delay circuit 15 and the second delay circuit 16；First prolongs The first input port of slow circuit 15 connects a N calibration code output end of ROM module 14, the 3rd of the first delay circuit 15 the Input port connects X phase controlling input code, and X hand over word output is arrived DDS cores by the output port of the first delay circuit 15 Phase amplitude converter 114 in piece；The first input port of the second delay circuit 16 connects the 2nd N school of ROM module 14 Quasi- code output end, the 3rd input port of the second delay circuit 16 connects N amplitude control input code, the second delay circuit 16 The N current-mode DAC 115 that output port arrives in DDS chips N hand over word output.
Above-mentioned charge-domain phase error calibration circuit, including two kinds of mode of operations of calibration mode and compensation model.In electricity Road is introduced into calibration mode when working, afterwards into compensation model；When calibration mode is entered, X phase controlling input code, N Amplitude control input code, a K delay code and the 2nd K delay code are invalid, and a N calibration code is input to the first delay Circuit 15, the 2nd N calibration code is input to the second delay circuit 16, and the charge-domain phase error calibrates circuit successively to DDS N current-mode DAC 115 and phase amplitude converter 114 in chip carry out phase error calibration；When compensation model is entered, X phase controlling input code and N amplitude control input code are separately input to the first delay circuit 15 and the second delay circuit 16, First N calibration code and the 2nd N calibration code are invalid, and a K delay code and the 2nd K delay code are effective, the charge-domain Phase error calibration circuit enters line phase to the N current-mode DAC 115 and phase amplitude converter 114 in DDS chips simultaneously Compensation.
The operation principle of foregoing circuit is：When calibration mode is opened, control circuit 12 is controlled first by Ctrl signals Charge-domain phase error detection amplifying circuit 10, K charge-domain analog-digital converter 11 and the second delay circuit 16 enter calibrating die Formula, while exporting K option code to charge-domain phase error detection amplifying circuit 10, starts to N current-mode in DDS chips DAC 115 carries out phase error calibration.
First group of K option code of control circuit 12 and then generation, while controlling ROM module 14 to produce first group the 2nd N Calibration code cali (1)；First group of the 2nd N calibration code cali (1) is into the second delay circuit 16 and obtains N hand over word, N The N circuit of current-mode DAC 115 that hand over word enters in DDS chips to be calibrated, obtains and first group the 2nd N through digital-to-analogue conversion The corresponding first group of differential output current signal Iop and Ion of calibration code；Charge-domain phase error detection amplifying circuit 10 is by inspection Iop-Ion amounts are surveyed, is processed to and is produced first group of reference clock produced by circuit to enter line phase with internal reference clock Detection, and its phase difference value is amplified can obtain error voltage Vop-Von；K charge-domain analog-digital converter 11 will be by mistake Potential difference Vop-Von carries out analog-to-digital conversion, can obtain first group of K quantization code and export to control circuit 12；Control circuit Reception is obtained first group of K quantization code storage in SRAM module 13 by 12, completes the DDS cores to be calibrated under a kind of input condition The current phase error quantizations of N current-mode DAC 115 in piece.
And then, second group of K option code of control circuit 12 and then generation, while controlling ROM module 14 to produce second group 2nd N calibration code cali (2)；Second group of the 2nd N calibration code cali (2) into the second delay circuit 16 and obtain N turn Escape, the N circuit of current-mode DAC 115 that N hand over word enters in DDS chips to be calibrated, obtains and second through digital-to-analogue conversion The corresponding second group of differential output current signal Iop and Ion of the N calibration code of group the 2nd；Charge-domain phase error detection amplifies electricity Road 10 is measured by detecting Iop-Ion, when being processed to and producing second group produced by circuit to refer to internal reference clock Clock carries out phase-detection, and its phase difference value is amplified can obtain error voltage Vop-Von；K charge-domain modulus turns Error voltage Vop-Von is carried out analog-to-digital conversion by parallel operation 11, can be obtained second group of K quantization code and be exported to control circuit 12；Reception is obtained second group of K quantization code storage in SRAM module 13 by control circuit 12, is completed under two kinds of input conditions The current phase error quantizations of N current-mode DAC 115 in DDS chips to be calibrated.
Circulate according to this, when the N calibration code cali (L) of generation L groups the 2nd and K option code of L groups, and obtain L groups K Position quantization code, and after storing in the SRAM module 13, the computing circuit inside control circuit 12 will be to storing in K bit registers K quantization code of L groups in group carries out being calculated the 2nd K delay code.Control circuit 12 now can be defeated by the 2nd K delay code Go out in the second delay circuit 16, and keep the 2nd K delay code constant, complete to N current-mode DAC in DDS chips 115 phase error calibration.
Afterwards, control circuit 12 controls the first delay circuit 15 to enter calibration mode by Ctrl signals, while output K Option code starts to carry out phase to the phase amplitude converter 114 in DDS chips to charge-domain phase error detection amplifying circuit 10 Position calibrates for error.The control control ROM module 14 of circuit 12 produces a N calibration code, by the first delay circuit 15, charge-domain Phase error detection amplifying circuit 10 and K charge-domain analog-digital converter 11, using and to N current-mode DAC in DDS chips 115 phase error calibrates identical step and method, obtains a K delay code and exports in the first delay circuit 15, Keep a K delay code constant simultaneously, complete the phase error calibration to phase amplitude converter 114.The charge-domain phase The calibration mode of position error calibration circuit terminates.
First delay circuit 15 and the second delay circuit 16 are arranged to compensate for pattern by control circuit 12 simultaneously, and it is right to start The phase error of N current-mode DAC 115 and phase amplitude converter 114 in DDS chips is compensated.Control circuit 12 is closed Disconnected a N calibration code and the 2nd N calibration code, close charge-domain phase error detection amplifying circuit 10 and K charge-domain mould Number converter 11, the charge-domain phase error calibration circuit enters compensation model.
In described above, N is any positive integer, and K is the no more than positive integer of N, and L is no more than 2KPositive integer.Upper State in calibration process, ginseng is arrived in each group the first N calibration code, the 2nd N calibration code and the output that control circuit 12 is produced simultaneously K option code for examining clock generation circuit must be corresponded, i.e.,：The N calibration code of J groups the first and the 2nd N calibration code are equal Must must be used cooperatively with K option code of J groups；Wherein, J is the no more than positive integer of L.
Charge-domain phase error of the present invention calibrates circuit in actual use, to the essence of phase error calibration Degree, hardware spending size can be configured with prover time length according to the different K and L values of selection, to meet different accuracy With the calibration accuracy and rate request of speed DDS chips.
Fig. 2 is a kind of embodiment of charge-domain phase error detection amplifying circuit 10 of the present invention, and the circuit includes：Electric current is examined Measuring resistance Rd 20, reference clock produces circuit 21, phase discriminator 22, loop filter 23 and charge-domain voltage amplifier circuit 24.Electricity The two ends of stream detection resistance Rd are connected respectively to the first and second inputs of charge-domain phase error detection amplifying circuit 10, and It is connected to the first and second input Voutp and Voutn of phase discriminator 22；Reference clock produces circuit 21 in K option code Under control, produce reference clock Clkref and be connected to the 3rd input of phase discriminator 22；3 letters of input of phase discriminator 22 pair Number carrying out further phase bit comparison obtains phase error signal Vp, and phase error signal Vp is filtered by loop filter 23 To voltage signal Vi；Amplify by charge-domain voltage amplifier circuit 24 and obtain error signal Vop and Von.
Fig. 3 show the schematic diagram of charge-domain voltage amplifier circuit 24 of the present invention.Charge-domain voltage amplifier circuit 24 is wrapped Include：First anode charge-storage node Nip, the first negative terminal charge-storage node Nin, the second anode charge-storage node Nop and Second negative terminal charge-storage node Non, one be connected between the first and second anode charge-storage node Nip and Nop just End electric charge transmission controlling switch 301, is connected to the negative terminal between the first and second negative terminal charge-storage node Nin and Non Electric charge transmits controlling switch 302, is connected to the anode electric capacity 303 of the first anode charge-storage node Nip, is connected to the second anode The anode capacitance programmable capacitor 309 of charge-storage node Nop, the negative terminal electricity for being connected to the first negative terminal charge-storage node Nin Hold 304, be connected to the negative terminal capacitance programmable capacitor 310 of the second negative terminal charge-storage node Non, be connected to the first anode electric charge The first positive terminal voltage transmitting switch 305 of memory node Nip, the second anode for being connected to the first anode charge-storage node Nip Voltage transmitting switch 307, the 3rd positive terminal voltage transmitting switch 313 for being connected to the second anode charge-storage node Nop and connection The 4th positive terminal voltage transmitting switch 311 to the second anode charge-storage node Nop, it is connected to the first negative terminal charge-storage node The first negative terminal voltage transmitting switch 306 of Nin, the second negative terminal voltage transmission for being connected to the first negative terminal charge-storage node Nin Switch 308, the 3rd negative terminal voltage transmitting switch 314 for being connected to the second negative terminal charge-storage node Non and to be connected to second negative Hold the 4th negative terminal voltage transmitting switch 312 of charge-storage node Non.For the embodiment of the present invention, charge-domain voltage amplification electricity Either end connection Vi in two analog voltage inputs on road 24, other end connects reference signal and is capable of achieving.
Fig. 4 is the work schedule control waveform diagram of circuit shown in Fig. 3.It is opposite in phase to control clock Clk and Clkn Clock, switch controlling signal Clkr, Clks and Clkt are that phase does not overlap clock.Heretofore described electric charge transmission control is opened Pass can realize that described voltage is passed using the implementation method described in the patent of invention of Patent No. 201010291245.6 Defeated switch can be realized using general metal-oxide-semiconductor or BJT switches.
Fig. 5 show a kind of embodiment of the circuit of phase discriminator of the present invention 22.The circuit is by signal shaping module and one Individual subtractor sub-module is constituted.Input differential signal Voutp and Voutn are carried out shaping and obtain being input into phase by signal shaping module Position, used as fixed phase, input phase and fixed phase are carried out phase to the reference clock of reference clock output by subtractor sub-module Subtract, obtain phase error signal Vp.
Fig. 6 show reference clock of the present invention and produces the structured flowchart of circuit 21.The reference clock produces circuit 21 Including：One programmable frequency adjustment circuit and a programmable duty cycle adjustment circuit.The programmable frequency adjustment circuit Controlled by K option code with the programmable duty cycle adjustment circuit.Under the K control of option code, frequency and dutycycle After fixed input clock priority is by the programmable frequency adjustment circuit and the programmable duty cycle adjustment circuit, i.e., Can obtain the reference clock Clkref of different frequency and dutycycle.
As shown in fig. 7, K charge-domain analog-digital converter 11 of present invention design includes：P grades is based on charge-domain signal transacting The sub- level circuit of streamline of technology, afterbody (P+1 grades) A-bit Flash analog-digital converter circuits, time delay are synchronously deposited Device and digital correction circuit module.Other mode of operation control module is also back work mould necessary to analog-digital converter work Block, the module is not identified in figure.The work of the adjacent sub- level circuit of two-stage is received in charge-domain analog-digital converter circuit in Fig. 7 The digit k of every grade of circuit of sum of series of two groups of controls of multi-phase clock, working condition complete complementary, and sub- level circuit can spirit Adjustment living.14 analog-digital converters for example for K=14, can be using 12 grades 1.5bit/ grades+1 grade of 2bit Flash totally 13 The structure of level, it would however also be possible to employ 4 grades 2.5bit/ grades+3 grades of 1.5bit/ grades+1 grade of 3bit Flash totally 8 grades of structure.
The charge-domain analog-digital converter 11 of present invention design includes herein below：P grades is based on charge-domain signal processing technology Charge-domain pipelined sub- level circuit, it is used to carrying out various treatment to the charge packet that obtains of sampling completing analog-to-digital conversion and surpluses Amplify, and the output digital code of each height level circuit is input to time delay SYN register, and each height level circuit output Charge packet enter next stage repeat said process；Afterbody (P+1 grades) A-bit Flash analog-digital converter circuits, its The charge packet that P grades transmits is re-converted into voltage signal, and carries out the analog-to-digital conversion work of afterbody, and incite somebody to action this The output digital code of level circuit is input to time delay SYN register, and this grade of circuit only completes analog-to-digital conversion, does not carry out surplus amplification； Time delay SYN register, it is used to enter the digital code that each sub- pipelining-stage is exported line delay alignment, and the digital code that will be alignd It is input to figure adjustment module；Digital correction circuit module, its output digital code for being used to receive SYN register, by what is received Digital code carries out shifter-adder, to obtain the R bit digital output codes of analog-digital converter.In described above, R is positive integer, A and P It is the no more than positive integer of R.
Charge-domain pipelined sub- level circuit theory diagrams are shown in Fig. 8.Circuit is made up of the signal processing channel of fully differential, Whole circuit includes：2 this grade of electric charges transmission controlling switch, 2 charge-storage nodes, 6 be connected to charge-storage node Charge storage capacitance, C charge comparator, the C reference signal selection circuit by the control of comparator output result, 2B+2 electricity Pressure transmitting switch, wherein B is positive integer.During circuit normal work, prime differential electrical pocket transmits control by electric charge first to be opened Pass is transmitted and stored at this grade of charge-storage node, the voltage difference between the comparator node caused to the input of differential electrical pocket Variable quantity is compared with reference voltage 3 and reference voltage 4, obtains this grade of C and quantifies output digital code D1~DB；Numeral output Code D1~DB will be exported to time delay SYN register, while D1~DB will also respectively control the reference signal of this grade to select electricity Road, makes them produce the reference signal of a pair of complementations to control this grade of positive and negative terminal electric charge plus-minus capacitor bottom plate respectively respectively, to by preceding The differential electrical pocket that level is transferred to this grade carries out correspondingly sized plus-minus treatment, obtains this grade of differential margin charge packet；Finally, electricity The complete cost differential in road point surplus charge packet is by the downward Primary Transmit of this level, 1 pair of this grade of differential charge of reference voltage 2 and reference voltage Memory node is resetted, and completes charge-domain pipelined one work of whole clock cycle of sub- level circuit.Wherein, C is just whole Number.Reference voltage 1~4 shown in Fig. 8 is identical with the reference voltage 1~4 shown in Fig. 3.
(P+1 grades) of the afterbody for the charge-domain pipelined analog-digital converter of present invention design in Fig. 7 is based on electricity The sub- level circuit A-bit Flash analog-digital converter circuits of streamline of lotus domain signal processing technology, it is right that the sub- level circuit will only need to The charge packet for receiving carries out the analog-to-digital conversion work of afterbody, and this grade of circuit output digital code is input into time delay synchronization Register, without carrying out surplus treatment.Remove reference signal selection circuit in Fig. 8 and controlled by reference signal selection circuit 4 electric capacity.
Fig. 9 show delay circuit structured flowchart of the present invention.The delay circuit inside includes：N number of time delay buffering Unit and N number of K delay time register, the first time delay buffer cell~the N time delay buffer cells, K delay time register~ N-th K delay time register.The delay code input of the first K delay time register~n-th K delay time register all connects K delay code is connected to, control signal input is all connected to Ctrl signals；First time delay buffer cell~the N time delays are buffered The delay code that the delay code input of unit is connected respectively to a K delay time register~n-th K delay time register is exported End, the data output end of the first time delay buffer cell~the N time delay buffer cells is connected respectively to the 1st hand over word~the N Hand over word is simultaneously exported, and the first control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected to Ctrln signals, the second control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected to signal Ctrl.Wherein, Ctrl and Ctrln is reverse clock.
Delay circuit is operable with being calibrated and compensated for pattern both of which under the control of Ctrl signals.In the calibration mode When, effectively, the 1st hand over word~the N input code is invalid, and input code is for the N output of hand over word without any for Ctrl signals Influence, the 1st calibration code~the N calibration code obtains the 1st after time delay buffer circuit 1~time delay buffer circuit N and turns respectively Escape~the N hand over word is simultaneously exported, and K postpones code and be imported into a K delay time register~n-th K delay deposit In device and be latched holding it is constant.When in the compensation mode, effectively, the 1st hand over word~the N input code has Ctrln signals Effect, and the 1st hand over word~the N hand over word is obtained after time delay buffer circuit and is exported, the 1st calibration code~the N school Quasi- code is invalid, and K stored in a K delay time register~n-th K delay time register postpones code and be imported into time delay Compensation of delay is carried out in buffer circuit 1~time delay buffer circuit N.
The delay circuit 16 of first delay circuit of the present invention 15 and second is using the delay circuit knot shown in Fig. 9 Structure.
Figure 10 show the control block diagram of circuit 12 of the present invention.The control circuit 12 includes：Core control circuit, ROM reading circuits, first postpone code produce circuit, second postpone code produce circuit, option code produce circuit, computing circuit, SRAM read/write circuits and K bit registers.
Annexation is：First output end of core control circuit is connected to the input of ROM reading circuits, core control Second output end of circuit is connected to the control signal that the first delay code produces circuit, the 3rd output end of core control circuit The control signal that the second delay code produces circuit is connected to, the 4th output end of core control circuit is connected to computing circuit Control signal, the 5th output end of core control circuit is connected to the control signal that option code produces circuit, core control 6th output end of circuit produces calibration control signal Ctrl, and the 7th output end of core control circuit is connected to K and posts simultaneously The control signal of storage and SRAM read/write circuits, the input of core control circuit is connected to calibration and starts control signal；ROM Reading circuit produces ROM address codes according to the control instruction of core control circuit；The data input pin of computing circuit receives SRAM The data that read/write circuit output end sends, and a K error codes and the 2nd K are produced according to the control instruction of core control circuit Position error codes；First postpone that code produces that the data input pin of circuit receives that computing circuit data output end sends the first K miss Difference code, and a K delay code is produced according to the control instruction of core control circuit；Second postpones code produces the data of circuit defeated Enter end and receive the 2nd K error codes that computing circuit data output end sends, and produced according to the control instruction of core control circuit Raw 2nd K delay code；Option code produces circuit to produce K option code according to the control instruction of core control circuit；K deposit The data input pin of device receives the K quantization code that the output end of the K charge-domain analog-digital converter 11 sends, and according to core Control the control instruction of circuit to will be stored in its internal data is activation and give SRAM read/write circuits；SRAM read/write circuits are according to core Control the control instruction of circuit to produce SRAM address dates code, digital independent and write-in are carried out to SRAM module 13.
Figure 11 is the DDS circuit block diagram that use charge-domain phase error of the present invention calibrates circuit.The DDS circuit bag Contain：Phase accumulator 113, phase amplitude converter 114, N current-mode DAC 115, charge-domain phase error calibration circuits 110th, clock generation circuit 111 and mode control circuit 112.
The annexation of the DDS circuit is as follows：First calibration control signal output connection of mode control circuit 112 To phase accumulator 113, phase amplitude converter 114 and the N calibration signal control end of current-mode DAC 115, Schema control Second calibration control signal output of circuit 112 is connected to the calibration signal control end of clock generation circuit 111, Schema control 3rd calibration control signal output of circuit 112 is connected to the calibration signal control of charge-domain phase error calibration circuit 110 End；The output of phase accumulator 113 is connected to the X phase controlling input code input of charge-domain phase error calibration circuit 110 End；The phase controlling input of phase amplitude converter 114 is connected to X conversion of charge-domain phase error calibration circuit 110 Code output end, the N amplitude control input code of the output of phase amplitude converter 114 is connected to charge-domain phase error calibration circuit 110 N amplitude control input code input；N current-mode DAC 115 according to the first calibration control signal, N hand over word, Output difference current signal Iop and Ion are produced under the control of work clock f0 and calibration clock fc；Charge-domain phase error is calibrated Circuit 110 calibration clock fc and the 3rd calibration control signal control under, by detecting differential current signal Iop and Ion simultaneously Processed, obtain the X hand over word and N hand over word by phase compensation and be respectively outputted to phase amplitude converter 114 With N current-mode DAC 115；Clock generation circuit 111 produces clock alignment clock under the control of the second calibration control signal Fc and work clock f0, work clock f0 are used to control calibration clock phase accumulator 113, phase amplitude converter 114 and N Current-mode DAC 115, calibration clock fc is used to control phase amplitude converter 114, N current-mode DAC 115 and charge-domain phase Position error calibration circuit 110.
Use charge-domain phase error of the present invention calibrates the DDS circuit of circuit, including calibration mode and compensation model Two kinds of mode of operations.The DDS circuit of the use charge-domain phase error calibration circuit is introduced into calibration mode when working, laggard Enter compensation model；When calibration mode is entered, mode control circuit 112 controls clock to produce electricity by the second calibration control signal Close work clock f0 on road 111, output calibration clock fc；Mode control circuit 112 is also controlled by the 3rd calibration control signal Charge-domain phase error calibration circuit 110 starts to carry out phase error calibration to DDS circuit；Mode control circuit 112 also passes through First calibration control signal control phase accumulator 113, phase amplitude converter 114 and N current-mode DAC 115 enter calibration Pattern；Phase amplitude converter 114, charge-domain phase error calibration circuit 110 and N current-mode DAC115 will be in calibrations Under the control of clock fc, start DDS phase error calibration operations；Carry out first caused by the N phase error of current-mode DAC 115 The calibration of DDS phase errors, then carries out the calibration of DDS phase errors caused by the phase error of phase amplitude converter 114, Now X phase controlling input code and N amplitude control input code are in disarmed state.
As DDS caused by the phase error that charge-domain phase error calibration circuit 110 completes to phase amplitude converter 114 After the calibration of phase error, when the DDS circuit of the use charge-domain phase error calibration circuit 110 enters compensation model, Mode control circuit 112 controls clock generation circuit 111 to close calibration clock fc, output services by the second calibration control signal Clock f0；Mode control circuit 112 also controls charge-domain phase error calibration circuit 110 to start by the 3rd calibration control signal Phase error compensation is carried out to DDS circuit, by the X of phase compensation hand over word and N hand over word and phase will be respectively outputted to Position amplitude converter 114 and N current-mode DAC 115；Mode control circuit 112 also controls phase by the first calibration control signal Bit accumulator 113, phase amplitude converter 114 and N current-mode DAC 115 enter normal mode of operation, phase amplitude conversion Device 114 and N current-mode DAC 115 operationally will work under the control of clock f0；X phase controlling input code and N width Degree control input code starts effective, and it is defeated that the DDS circuit of the use charge-domain phase error calibration circuit starts normal frequency Go out synthetic work pattern.
In actual applications, the selection of calibration clock fc and work clock f0 frequencies can be rolled over according to system application demand Inner feelings is selected, to realize low-power consumption, can be by the set of frequency of fc into a relatively low frequency, and its cost is that prover time has been prolonged It is long；To realize calibration speed faster, can be by the set of frequency of fc an into frequency higher, its cost is that circuit power consumption has Increased.
The foregoing is only presently preferred embodiments of the present invention, be not intended to limit the invention, it is all it is of the invention spirit and Within principle, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.

Claims (10)

1. charge-domain phase error calibrates circuit, it is characterized in that, including：Charge-domain phase error detection amplifying circuit (10), K Charge-domain analog-digital converter (11), control circuit (12), ROM module (14), SRAM module (13) and the first delay circuit And the second delay circuit (16) (15)；
The annexation of foregoing circuit is：The first and second inputs difference of charge-domain phase error detection amplifying circuit (10) It is connected to the N signal output difference port of current-mode DAC (115), charge-domain phase error detection amplifying circuit in DDS chips (10) control signal is connected to K option code output port of control circuit (12), and charge-domain phase error detection is amplified The differential voltage output end of circuit (10) is connected to the K differential voltage input of charge-domain analog-digital converter (11)；K electric charge Error input port of the K quantization code output of domain analog-digital converter (11) to control circuit (12)；The ROM of control circuit (12) Control port output control signal gives to the SRAM control port output control signals of ROM module (14), control circuit (12) SRAM module (13), a K delay code output end of control circuit (12) is connected to the second defeated of the first delay circuit (15) Inbound port, the 2nd K delay code output end of control circuit (12) is connected to the second input port of the second delay circuit (16), The calibration control signal Ctrl output ports of control circuit (12) are connected to charge-domain phase error detection amplifying circuit simultaneously (10), the K calibration control letter of charge-domain analog-digital converter (11), the first delay circuit (15) and the second delay circuit (16) Number Ctrl input ports；First N calibration code of first input port connection ROM module (14) of the first delay circuit (15) is defeated Go out end, the 3rd input port of the first delay circuit (15) connects X phase controlling input code, the first delay circuit (15) it is defeated The phase amplitude converter (114) that exit port arrives in DDS chips X hand over word output；The first of second delay circuit (16) 2nd N calibration code output end of input port connection ROM module (14), the 3rd input port of the second delay circuit (16) connects N amplitude control input code is connect, the output port of the second delay circuit (16) exports to N in DDS chips N hand over word Current-mode DAC (115)；Wherein, X and N are arbitrary positive integer, and K is the no more than positive integer of N.
2. charge-domain phase error as claimed in claim 1 calibration circuit, it is characterized in that, its mode of operation include calibration mode and Compensation model；And calibration mode is introduced into when circuit works, afterwards into compensation model；
When calibration mode is entered, X phase controlling input code, N amplitude control input code, K delay code and the 2nd K Position delay code is invalid, and a N calibration code is input to the first delay circuit (15), and the 2nd N calibration code is input to second and prolongs Slow circuit (16), charge-domain phase error calibrates circuit successively to N current-mode DAC (115) in DDS chips and phase amplitude Converter (114) carries out phase error calibration；
When compensation model is entered, X phase controlling input code and N amplitude control input code are separately input to the first deferred telegram Road (15) and the second delay circuit (16), a N calibration code and the 2nd N calibration code are invalid, K delay code and second K postpones code effectively, and charge-domain phase error calibration circuit is simultaneously to N current-mode DAC (115) in DDS chips and phase Amplitude converter (114) carries out phase compensation.
3. charge-domain phase error as claimed in claim 2 calibrates circuit, it is characterized in that, when calibration mode is entered, circuit Job order is as follows：
1st, phase error calibration is carried out to N current-mode DAC (115) in DDS chips first：
Control circuit (12) controls charge-domain phase error detection amplifying circuit (10), K charge-domain first by Ctrl signals Analog-digital converter (11) and the second delay circuit (16) enter calibration mode, while export K option code being missed to charge-domain phase Difference detection amplifying circuit (10), starts to carry out phase error calibration to N current-mode DAC (115) in DDS chips；
Then control circuit (12) produces first group of K option code, while controlling ROM module (14) to produce first group the 2nd N Calibration code, N current-mode DAC (115) obtains first group of differential output current signal corresponding with first group of the 2nd N calibration code Iop and Ion；Charge-domain phase error detection amplifying circuit (10) is measured by detecting Iop-Ion, and is processed to obtain error electricity Pressure；Error voltage is carried out analog-to-digital conversion by K charge-domain analog-digital converter (11), can obtain first group of K quantization code and defeated Go out to control circuit (12)；Reception is obtained first group of K quantization code and stored in SRAM module (13) by control circuit (12), complete Into N current-mode DAC (115) current phase error quantization in the DDS chips to be calibrated under a kind of input condition；
And then, control circuit (12) produces second group of K option code, while controlling ROM module (14) to produce second group of the 2nd N Position calibration code, by N current-mode DAC (115), charge-domain phase error detection amplifying circuit (10) and K charge-domain modulus Converter (11) treatment, can obtain second group of K quantization code and export to control circuit (12)；Control circuit (12) will be received Second group of K quantization code storage is obtained in SRAM module (13), is completed in the DDS chips to be calibrated under two kinds of input conditions N current-mode DAC (115) current phase error quantization；
Circulate according to this, when the N calibration code of generation L groups the 2nd and K option code of L groups, and obtain K quantization code of L groups, and After storing in SRAM module (13), the internal computing circuit of control circuit (12) will be to storing the L in K bit register groups K quantization code of group carries out being calculated the 2nd K delay code；Control circuit (12) can now arrive the 2nd K delay code output In second delay circuit (16), and keep the 2nd K delay code constant, complete to N current-mode DAC (115) in DDS chips Phase error calibration；
2nd, phase error calibration is carried out to the phase amplitude converter (114) in DDS chips：
Control circuit (12) controls the first delay circuit (15) to enter calibration mode by Ctrl signals, while K selection of output Code gives charge-domain phase error detection amplifying circuit (10), starts to carry out phase to the phase amplitude converter (114) in DDS chips Position calibrates for error；
Control circuit (12) controls ROM module (14) to produce a N calibration code, by the first delay circuit (15), charge-domain Phase error detection amplifying circuit (10) and K charge-domain analog-digital converter (11), using and to N electric current in DDS chips The phase error of mould DAC (115) calibrates identical step and method, obtains a K delay code and exports to the first deferred telegram In road (15), while keeping a K delay code constant, the phase to the phase amplitude converter (114) in DDS chips is completed Calibrate for error；Now, the calibration mode of the charge-domain phase error calibration circuit terminates；
In above-mentioned calibration process, control circuit (12) is while each group the first N calibration code, the 2nd N calibration code producing Must be corresponded with K option code, i.e.,：The N calibration code of J groups the first and the 2nd N calibration code must be with J groups K Option code is used cooperatively；Wherein, L is no more than 2KPositive integer, J is the no more than positive integer of L.
4. charge-domain phase error as claimed in claim 1 calibrates circuit, it is characterized in that, described charge-domain phase error detection Amplifying circuit (10) includes：Current sense resistor (20), reference clock produce circuit (21), phase discriminator (22), loop filter And charge-domain voltage amplifier circuit (24) (23)；
The annexation of foregoing circuit is：The two ends of current sense resistor (20) are connected respectively to charge-domain phase error detection and put The first input end and the second input of big circuit (10), and it is connected respectively to the first input end of phase discriminator (22) and second defeated Enter end；Reference clock produces circuit (21) under the K control of option code, produces reference clock and is connected to phase discriminator (22) 3rd input；Phase discriminator (22) carries out further phase bit comparison and obtains phase error signal to 3 signals of input；Phase Position error signal obtains voltage signal V by loop filter (23) filteringi；ViPut by charge-domain voltage amplifier circuit (24) Obtain error signal Vop and Von greatly.
5. charge-domain phase error as claimed in claim 1 calibrates circuit, it is characterized in that, K described charge-domain analog-to-digital conversion Device (11) includes：The P grades of sub- level circuit of streamline based on charge-domain signal processing technology, for entering to the charge packet that sampling is obtained The various treatment of row complete analog-to-digital conversion and surplus is amplified, and the output digital code of each height level circuit is input into time delay synchronization Register, and the charge packet of each height level circuit output enters next stage repetition said process；P+1 grades, be also last Level A-bit Flash analog-digital converter circuits, are re-converted into voltage signal, and carry out by the charge packet that P grades transmits The analog-to-digital conversion work of afterbody, and the output digital code of this grade of circuit is input to time delay SYN register, this grade of circuit Analog-to-digital conversion is only completed, surplus amplification is not carried out；Time delay SYN register, for entering to the digital code that each sub- pipelining-stage is exported Line delay is aligned, and the digital code of alignment is input into figure adjustment module；Digital correction circuit module, for receiving synchronous posting The output digital code of storage, shifter-adder is carried out by the digital code of reception, to obtain the R bit digital output codes of analog-digital converter； Wherein, R is positive integer, and P and A is the no more than positive integer of R.
6. charge-domain phase error as claimed in claim 1 calibration circuit, it is characterized in that, first delay circuit (15) and the Two delay circuits (16) use identical delay circuit, and structure includes：N number of time delay buffer cell and N number of K delay deposit Device；Wherein, the delay code input of a K delay time register~n-th K delay time register is all connected to K delay Code, control signal input is all connected to calibration control signal Ctrl；First time delay buffer cell~the N time delay buffer cells Delay code input be connected respectively to the delay code output end of the delay time register of K delay time register~n-th K, The data output end of the first time delay buffer cell~the N time delay buffer cells is connected respectively to the 1st hand over word~the N conversion Code is simultaneously exported, and the first control signal input of the first time delay buffer cell~the N time delay buffer cells is all connected to calibration The reverse signal Ctrln of control signal Ctrl, the second control signal of the first time delay buffer cell~the N time delay buffer cells is defeated Enter end and be all connected to signal Ctrl.
7. charge-domain phase error as claimed in claim 6 calibrates circuit, it is characterized in that, the delay circuit can operate at school Accurate and compensation model both of which；
When in the calibration mode, effectively, the 1st hand over word~the N input code is invalid for Ctrl signals, and input code turns for N The output of escape has no effect, and the 1st calibration code~the N calibration code is respectively through the first time delay buffer circuit~the N time delays The 1st hand over word~the N hand over word is obtained after buffer circuit and is exported, K postpones code and be imported into a K delay deposit In device~n-th K delay time register and be latched holding it is constant；When in the compensation mode, effectively, the 1st turns Ctrln signals Escape~the N input code effectively, and obtains the 1st hand over word~the N hand over word and exports after time delay buffer circuit, the 1 calibration code~the N calibration code is invalid, and K stored in a K delay time register~N number of K delay time register prolongs Slow code carries out compensation of delay in being imported into the first time delay buffer circuit~the N time delay buffer circuits.
8. charge-domain phase error as claimed in claim 1 calibrates circuit, it is characterized in that, control circuit (12) includes：Core The heart control circuit, ROM reading circuits, first postpone code produce circuit, second postpone code produce circuit, option code produce circuit, Computing circuit, SRAM read/write circuits and K bit registers；
The annexation of foregoing circuit is：First output end of core control circuit is connected to the input of ROM reading circuits, core Second output end of heart control circuit is connected to the control signal that the first delay code produces circuit, the 3rd of core control circuit the Output end is connected to the control signal that the second delay code produces circuit, and the 4th output end of core control circuit is connected to computing The control signal of circuit, the 5th output end of core control circuit is connected to the control signal that option code produces circuit, core 6th output end of heart control circuit produces the 7th output end of calibration control signal Ctrl, core control circuit to be connected to simultaneously The control signal of K bit registers and SRAM read/write circuits, the input of core control circuit is connected to calibration and starts control letter Number；ROM reading circuits produce ROM address codes according to the control instruction of core control circuit；The data input termination of computing circuit The data that SRAM read/write circuits output end sends are received, and a K error codes are produced according to the control instruction of core control circuit With the 2nd K error codes；First postpone that code produces that the data input pin of circuit receives that computing circuit data output end sends the One K error codes, and a K delay code is produced according to the control instruction of core control circuit；Second postpones code produces circuit Data input pin receive the 2nd K error codes that computing circuit data output end sends, and according to the control of core control circuit System instruction produces the 2nd K delay code；Option code produces circuit to produce K selection according to the control instruction of core control circuit Code；The K quantization that the output end that the data input pin of K bit registers receives the K charge-domain analog-digital converter (11) sends Code, and give SRAM read/write circuits according to data is activation that the control instruction of core control circuit will be stored in its inside；SRAM reads Write circuit produces SRAM address dates code according to the control instruction of core control circuit, and digital independent is carried out to SRAM module (13) And write-in.
9. the DDS circuit of circuit is calibrated using charge-domain phase error described in claim 1, it is characterized in that, including claim 1 Described charge-domain phase error calibrates circuit (110), also includes：Phase accumulator (113), phase amplitude converter (114), N current-mode DAC (115), clock generation circuit (111) and mode control circuit (112)；
The annexation of foregoing circuit is as follows：First calibration control signal output of mode control circuit (112) is connected to phase Bit accumulator (113), phase amplitude converter (114) and the N calibration signal control end of current-mode DAC (115), Schema control Second calibration control signal output of circuit (112) is connected to the calibration signal control end of clock generation circuit (111), pattern 3rd calibration control signal output of control circuit (112) is connected to the calibration of charge-domain phase error calibration circuit (110) Signal control end；The output of phase accumulator (113) is connected to X phase control of charge-domain phase error calibration circuit (110) Input code input processed；The phase controlling input of phase amplitude converter (114) is connected to charge-domain phase error calibration electricity The X hand over word output end on road (110), the N amplitude control input code of phase amplitude converter (114) output is connected to electric charge The N amplitude control input code input in domain phase error calibration circuit (110)；N current-mode DAC (115) is according to the first school Produced under the control of quasi- control signal, N a hand over word, work clock f0 and calibration clock fc output difference current signal Iop and Ion；Charge-domain phase error calibrates circuit (110) under the control of the calibration control signals of calibration clock fc and the 3rd, by inspection Survey differential current signal Iop and Ion and processed, obtain by the X hand over word and N hand over word and difference of phase compensation Export phase amplitude converter (114) and N current-mode DAC (115)；Clock generation circuit (111) is in the second calibration control Under the control of signal, calibration clock fc and work clock f0, work clock f0 is produced to be used for control calibration clock phase accumulator (113), phase amplitude converter (114) and N current-mode DAC (115), calibration clock fc are used to control phase amplitude converter (114), N current-mode DAC (115) and charge-domain phase error calibrate circuit (110).
10. DDS circuit as claimed in claim 9, it is characterized in that, there are two kinds of mode of operations of calibration mode and compensation model；And And calibration mode is introduced into when circuit works, afterwards into compensation model；
When calibration mode is entered, mode control circuit (112) controls clock to produce electricity to circuit by the second calibration control signal Close work clock f0 on road (111), output calibration clock fc；Mode control circuit (112) is also by the 3rd calibration control signal Control charge-domain phase error calibration circuit starts to carry out phase error calibration to DDS circuit；Mode control circuit (112) also leads to Cross the first calibration control signal and control phase accumulator (113), phase amplitude converter (114) and N current-mode DAC (115) Into calibration mode；Phase amplitude converter (114), charge-domain phase error calibration circuit and N current-mode DAC (115) will DDS phase error calibration operations can be started under the control of calibration clock fc；The N phase of current-mode DAC (115) is carried out first The calibration of DDS phase errors, then carries out DDS caused by the phase error of phase amplitude converter (114) caused by the error of position The calibration of phase error, now X phase controlling input code and N amplitude control input code are in disarmed state；
When compensation model is entered, mode control circuit (112) controls clock generation circuit by the second calibration control signal (111) calibration clock fc, output services clock f0 are closed；Mode control circuit (112) is also by the 3rd calibration control signal control Charge-domain phase error processed is calibrated circuit (110) and starts to carry out phase error compensation to DDS circuit, by by the X of phase compensation Position hand over word and N hand over word and it is respectively outputted to phase amplitude converter (114) and N current-mode DAC (115)；Pattern control Circuit (112) processed is also by the first calibration control signal control phase accumulator (113), phase amplitude converter (114) and N Current-mode DAC (115) enters normal mode of operation, and phase amplitude converter (114) and N current-mode DAC (115) will be in works Worked under the control for making clock f0；X phase controlling input code and N amplitude control input code start effectively.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109884607A (en) * 2019-03-21 2019-06-14 杭州电子科技大学 A kind of synthetic aperture address code generating method based on FPGA
CN110838843A (en) * 2019-11-22 2020-02-25 中国电子科技集团公司第五十八研究所 Anti-irradiation DDS circuit

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WO2001022119A1 (en) * 1999-09-23 2001-03-29 Constellation Technology Corporation Apparatus and method for automatic correction of pole-zero error in a spectroscopy system
CN108631783A (en) * 2018-06-08 2018-10-09 中国电子科技集团公司第五十八研究所 A kind of reference voltage mismatch calibration circuit for multichannel ADC

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WO2001022119A1 (en) * 1999-09-23 2001-03-29 Constellation Technology Corporation Apparatus and method for automatic correction of pole-zero error in a spectroscopy system
CN108631783A (en) * 2018-06-08 2018-10-09 中国电子科技集团公司第五十八研究所 A kind of reference voltage mismatch calibration circuit for multichannel ADC

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Publication number Priority date Publication date Assignee Title
CN109884607A (en) * 2019-03-21 2019-06-14 杭州电子科技大学 A kind of synthetic aperture address code generating method based on FPGA
CN110838843A (en) * 2019-11-22 2020-02-25 中国电子科技集团公司第五十八研究所 Anti-irradiation DDS circuit
CN110838843B (en) * 2019-11-22 2022-08-02 中国电子科技集团公司第五十八研究所 Anti-irradiation DDS circuit

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