CN109884607A - A kind of synthetic aperture address code generating method based on FPGA - Google Patents
A kind of synthetic aperture address code generating method based on FPGA Download PDFInfo
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Abstract
The invention discloses the synthetic aperture address code generating methods based on FPGA, for synthetic aperture radar/sonar pulse compressed images data high speed processing, cnt_i, cnt_j are generated using three tunnels synthesis range counter, cnt_k count value, to drive multichannel address code generation module；Address code generation module passes through the driving of No. three counters, utilizes pipeline organization parallel generation address code d-1；And the delay of address code k-i is carried out using shift register, the address code d-1 generated with pipeline organization is synchronized, so that the address code for reaching high speed generates effect；Present invention could apply to the high-speed parallel generations to address code under the exigent occasion of synthetic aperture algorithm speed, is carried out.
Description
Technical field
The invention belongs to the fields FPGA, are related to a kind of synthetic aperture address code generating method based on FPGA.
Background technique
Currently, synthetic aperture algorithm generally can only require to use under lower occasion in processing speed, lacking one kind can
The calculation method handled in real time after image data is obtained up to/sonar in side clearance.Existing method generally uses at present
CPU is realized, when according to the mode of the instruction sequences execution image information huge for processing data volume, is needed longer
Time, and image to be processed is bigger, the time needed is more long.And for the generation of the address code of synthetic aperture algorithm,
It needs to carry out more complicated operation, and needs to carry out the storage of mass data during processing.Height is being required to use
Speed obtains the occasion of the image after synthetic aperture processing, such as needs almost real-time quick obtaining bulk zone in aircraft/submarine
In the case where high pay-off target, hence it is evident that be difficult to reach its high speed and require in real time.
Summary of the invention
In view of the deficiencies of the prior art, the present invention proposes a kind of synthetic aperture address code generating method based on FPGA, this
Kind method can be applied to generate the high-speed parallel under the exigent occasion of synthetic aperture algorithm speed, carrying out address code.
The present invention advantage high using FPGA operation efficiency, is based on standard turn around delay formula
Address code calculating is carried out, the realization of entire algorithm is accelerated, t in formuladFor turn around delay；R0For air route
The vertical range of shortcut；X is the horizontal distance of lateral range.When radar synthetic aperture is realized, the turn around delay formula
Due to x < < R0, can be reduced to
But in view of synthetic aperture algorithm structure compatibility used in radar and sonar, the close of radical is not carried out to it
Like abbreviation.
The generation of address code is divided into 16 tunnels using the parallel characteristics of FPGA and handled by the present invention, and then guarantees the high speed calculated
Property, and the image of the image and intermediate aperture length enough of aperture processing two sides deficiency aperture length is handled respectively, shape
At three main roads, the high-speed parallel processing structure of 3*16 path.
To achieve the above object, the technical scheme is that a kind of synthetic aperture address code generation side based on FPGA
Method, comprising the following steps:
The generation of address code is divided into 16 tunnels using FPGA parallel characteristics by S10, and aperture is handled two sides deficiency aperture length
Image and the image of intermediate aperture length enough handled respectively, form three main roads, the high-speed parallel of 3*16 path
Processing structure；
The synthesis width of S20, aperture processing count, counter cnt_i, cnt_j, cnt_k in three main roads, respectively into
The different nested counting of row: in the first via, cnt_i circulation counts up to 0 from cnt_k；Cnt_j counts up to DIS_LINE/16 from 0,
It is counted for 16 tunnel line numbers, wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to AL- from 0
1, wherein cnt_k cnt_j is every complete a wheel circulation when change it is primary, to image before the part in complete aperture insufficient aperture
The aperture of length AL is cumulative to be counted；In second tunnel, cnt_i circulation counts up to 0 from AL-1；Cnt_j counts up to DIS_ from 0
LINE/16, wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to DIS_DOOR-AL- from AL
1, wherein cnt_k changes primary in the every one wheel circulation of completion of cnt_j, and the part progress hole of complete pore size is fallen within to image
Diameter accumulated counts；In third road, cnt_i circulation counts up to 0 from DIS_DOOR-cnt_k-1；Cnt_j counts up to DIS_ from 0
LINE/16, wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to DIS_ from DIS_DOOR-AL
DOOR-1, wherein cnt_k changes primary in the every one wheel circulation of completion of cnt_j, wherein the cnt_i in three main road counters
It is every to complete a wheel circulation, i.e. when cnt_i=0, respective refresh_flag is set to high level a cycle, provides a brush
New signal is handled for aperture, cumulative to the aperture of image insufficient aperture length AL after the part in complete aperture to count
Number, DIS_LINE are that range line corresponds to row, and DIS_DOOR is range gate respective column, and AL is aperture length points；
S30 generates address code d-1；
S40 generates address code k-i.
Preferably, the S30 the following steps are included:
S31 adds (rd_num-1) × (DIS_ using combinational logic circuit according to input number rd_num on cnt_j
LINE/16) obtain certain in 16 tunnels all the way in point and image border to be calculated pixel distance, utilize fixed point-floating-point to convert IP
Core is converted into 32 single precision floating datums, if in input data being the i-th period, then rising in+4 periods of I
Edge can obtain respective value R0_j_pix；The calculating that cnt_i-AL/2-1 is realized using combinational logic is obtained as a result, be denoted as x_i,
And 32 single precision floating datums are converted into using fixed point-floating-point conversion IP kernel, it is tied in+4 period rising edges of I
Fruit is denoted as fp_x_i；
S32 carries out the calculating of R0_j_pix × 1/fs by floating-point multiplier, and wherein 1/fs is the inverse of sample frequency,
That is sampling period corresponding 32 single-precision floating point values obtain multiplication result in+7 period rising edges of I, are denoted as t_pix, are
Wave beam reaches the two-way time used in tested point from testing image edge；Fp_x_i × delta_sa is carried out by floating-point multiplier
Calculating, delta_sa is the half of length of real aperture, i.e. azimuth resolution is multiplied in+7 period rising edges of I
Method result is denoted as x_i_rl, is actual distance of the sampled point to be calculated to air route coordinate origin；
S33, t_pix utilize floating-point adder with two-way time Ts used in most short vertical range of the air route to imaging region
It sums, obtains wave beam in+10 period rising edges of I and correspond to the two-way time from the vertical range that air route reaches point to be calculated
t_R0_j；X_i_rl is subjected to square operation using floating-point multiplier, obtains x_i_sqr in+10 period rising edges of I；
T_R0_j is multiplied by S34 using floating-point multiplier single-precision floating point value corresponding with c/2, and c is velocity of wave,
+ 13 period rising edges of I obtain the one way vertical range R0_j that wave beam reaches point to be calculated from air route；X_i_sqr is utilized
Shift register is shifted, and is allowed to obtain x_i_sqr_dly in+16 period rising edge outputs of I, be used for align data；
R0_j is carried out square operation using floating-point multiplier, obtains result R0_ in+16 period rising edges of I by S35
j_sqr；
X_i_sqr_dly is added with R0_j_sqr using floating-point adder by S36, is risen in+19 periods of I
Along obtain point to be calculated to coordinate origin one way oblique distance square R_sqr；
R_sqr is carried out evolution operation using floating-point square-root extractor, obtained in+29 period rising edges of I to be calculated by S37
Point arrives the one way oblique distance R of coordinate origin；
R was multiplied, on+32 periods of I by S38 using floating-point multiplier single-precision floating point value corresponding with 2/c
Liter edge obtains energy converter and receives round trip delay time td used in the echo of point to be calculated；
Td is subtracted the two-way time used in most short vertical range of the air route to imaging region using floating-point subtracter by S39
The corresponding single-precision floating point value of Ts obtains Tr in+35 period rising edges of I；
Tr is multiplied, at I+38 by S310 using floating-point multiplier single-precision floating point value corresponding with sample frequency fs
Period rising edge obtains tested point round trip delay delay_pix；
Delay_pix is carried out the conversion of floating-point to fixed-point number, and utilizes group by S311 using floating-point-fixed point conversion IP kernel
Logical realization delay_fixed-1 operation, obtains tested point address code dly_tb_d_1 in+40 period rising edges of I, i.e.,
d-1。
Preferably, the S40 the following steps are included:
S41 forms combinational logic circuit calculated value cnt_k-cnt_i using the value of cnt_i in S20 and cnt_k；
S42 is shifted cnt_k-cnt_i using shift register, in+40 period rising edges of I, is obtained and ground
The address code dly_tb_k_i, i.e. k-i of location code dly_tb_d_1 synchronism output.
Beneficial effects of the present invention are as follows:
The present invention uses the address code of the road 3*16 parallel generation synthetic aperture algorithm, so that the formation speed of address code is substantially
It improves, so that the time needed for the synthetic aperture method that traditional sequence executes is significantly shortened, synthetic aperture is greatly saved
The processing time needed for algorithm.
Detailed description of the invention
Fig. 1 is the algorithm flow chart of the synthetic aperture address code generating method based on FPGA of the embodiment of the present invention；
Fig. 2 is the clock diagram of the synthetic aperture address code generating method based on FPGA of the embodiment of the present invention.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.
On the contrary, the present invention covers any substitution done on the essence and scope of the present invention being defined by the claims, repairs
Change, equivalent method and scheme.Further, in order to make the public have a better understanding the present invention, below to of the invention thin
It is detailed to describe some specific detail sections in section description.Part without these details for a person skilled in the art
The present invention can also be understood completely in description.
It is the embodiment of the present invention the technical scheme is that the synthetic aperture address code based on FPGA referring to Fig. 1-2
The algorithm flow chart and clock diagram of generation method, comprising the following steps:
The generation of address code is divided into 16 tunnels using FPGA parallel characteristics by S10, and aperture is handled two sides deficiency aperture length
Image and the image of intermediate aperture length enough handled respectively, form three main roads, the high-speed parallel of 3*16 path
Processing structure；
The synthesis width of S20, aperture processing count, counter cnt_i, cnt_j, cnt_k in three main roads, respectively into
The different nested counting of row: in the first via, cnt_i circulation counts up to 0 from cnt_k；Cnt_j counts up to DIS_LINE/16 from 0,
It is counted for 16 tunnel line numbers, wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to AL- from 0
1, wherein cnt_k cnt_j is every complete a wheel circulation when change it is primary, to image before the part in complete aperture insufficient aperture
The aperture of length AL is cumulative to be counted；In second tunnel, cnt_i circulation counts up to 0 from AL-1；Cnt_j counts up to DIS_ from 0
LINE/16, wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to DIS_DOOR-AL- from AL
1, wherein cnt_k changes primary in the every one wheel circulation of completion of cnt_j, and the part progress hole of complete pore size is fallen within to image
Diameter accumulated counts；In third road, cnt_i circulation counts up to 0 from DIS_DOOR-cnt_k-1；Cnt_j counts up to DIS_ from 0
LINE/16, wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to DIS_ from DIS_DOOR-AL
DOOR-1, wherein cnt_k changes primary in the every one wheel circulation of completion of cnt_j, wherein the cnt_i in three main road counters
It is every to complete a wheel circulation, i.e. when cnt_i=0, respective refresh_flag is set to high level a cycle, provides a brush
New signal is handled for aperture, cumulative to the aperture of image insufficient aperture length AL after the part in complete aperture to count
Number, DIS_LINE are that range line corresponds to row, and DIS_DOOR is range gate respective column, and AL is aperture length points；
S30 generates address code d-1；
S40 generates address code k-i.
In specific embodiment, S30 the following steps are included:
S31 makes referring to the first row and secondary series of the second row in Fig. 1 and Fig. 2 clock diagram according to input number rd_num
With combinational logic circuit on cnt_j plus (rd_num-1) × (DIS_LINE/16) obtain certain in 16 tunnels all the way in wait count
Pixel distance of the point with image border is calculated, IP kernel is converted using fixed point-floating-point, is converted into 32 single precision floating datums, if
It is the i-th period in input data, then respective value R0_j_pix can be obtained in+4 period rising edges of I；Referring to Fig. 1
Middle the third line realizes the calculating of cnt_i-AL/2-1 using combinational logic, obtains as a result, being denoted as x_i, and utilize fixed point-floating-point
Conversion IP kernel is converted into 32 single precision floating datums, obtains in+4 period rising edges of I as a result, being denoted as fp_x_i；
S32 is arranged referring to the third of the second row and Fig. 2 clock diagram in Fig. 1, carries out R0_j_pix × 1/ by floating-point multiplier
The calculating of fs, wherein 1/fs is the inverse of sample frequency, i.e. sampling period corresponding 32 single-precision floating point values, at I+7
Period rising edge obtains multiplication result, is denoted as t_pix, when being that wave beam reaches round trip used in tested point from testing image edge
Between；The calculating of fp_x_i × delta_sa is carried out by floating-point multiplier referring to the third line in Fig. 1, delta_sa is true aperture
The half of length, i.e. azimuth resolution obtain multiplication result in+7 period rising edges of I and are denoted as x_i_rl, are to be calculated
Actual distance of the sampled point to air route coordinate origin；
S33, referring to the 4th column of the second row in Fig. 1 and Fig. 2 clock diagram, t_pix and air route are hung down to the most short of imaging region
It is directly summed apart from two-way time Ts used using floating-point adder, obtains wave beam from boat in+10 period rising edges of I
The vertical range that road reaches point to be calculated corresponds to two-way time t_R0_j；Referring to the third line in Fig. 1, x_i_rl is utilized into floating multiplication
Musical instruments used in a Buddhist or Taoist mass carries out square operation, obtains x_i_sqr in+10 period rising edges of I；
T_R0_j is utilized floating-point multiplier and c/2 pairs referring to the 5th column of the second row in Fig. 1 and Fig. 2 clock diagram by S34
The single-precision floating point value answered is multiplied, and c is velocity of wave, and it is to be calculated from air route arrival to obtain wave beam in+13 period rising edges of I
The one way vertical range R0_j of point；Referring to the 6th column of the third line in Fig. 1 and Fig. 2 clock diagram, x_i_sqr is utilized into shift LD
Device is shifted, and is allowed to obtain x_i_sqr_dly in+16 period rising edge outputs of I, be used for align data；
R0_j is carried out a square behaviour using floating-point multiplier referring to the 6th column of the second row in Fig. 1 and Fig. 2 clock diagram by S35
Make, obtains result R0_j_sqr in+16 period rising edges of I；
S36, referring to the 7th column of the first row in Fig. 1 and the second row and Fig. 2 clock diagram, by x_i_sqr_dly and R0_j_
Sqr is added using floating-point adder, and it is oblique to the one way of coordinate origin to obtain point to be calculated in+19 period rising edges of I
Away from square R_sqr；
R_sqr is carried out evolution using floating-point square-root extractor referring to the 8th column of fourth line in Fig. 1 and Fig. 2 clock diagram by S37
Operation ,+29 period rising edges of I obtain point to be calculated to coordinate origin one way oblique distance R；
R is utilized floating-point multiplier list corresponding with 2/c referring to the 9th column of fourth line in Fig. 1 and Fig. 2 clock diagram by S38
Precision floating point values are multiplied ,+32 period rising edges of I obtain energy converter receive used in the echo of point to be calculated it is double
Journey delay time td；
S39, referring to the tenth column of fourth line in Fig. 1 and Fig. 2 clock diagram, by td using floating-point subtracter subtract air route at
The corresponding single-precision floating point value of the two-way time Ts as used in the most short vertical range in region is obtained in+35 period rising edges of I
To Tr；
Tr is utilized floating-point multiplier and sampling frequency referring to the 11st column of fourth line in Fig. 1 and Fig. 2 clock diagram by S310
The corresponding single-precision floating point value of rate fs is multiplied, and obtains tested point round trip delay delay_pix in+38 period rising edges of I；
S311 is turned delay_pix using floating-point-fixed point referring to the 12nd column of fourth line in Fig. 1 and Fig. 2 clock diagram
It changes IP kernel and carries out the conversion of floating-point to fixed-point number, and realize that delay_fixed-1 is operated using combinational logic, in+40 week of I
Phase rising edge obtains tested point address code dly_tb_d_1, i.e. d-1.
Preferably, the S40 the following steps are included:
S41 forms combinational logic circuit calculated value using the value of cnt_i in S20 and cnt_k referring to the first row in Fig. 1
cnt_k-cnt_i；
S42, referring to the 12nd column to 14 column of fourth line in Fig. 1 and Fig. 2 clock diagram, using shift register by cnt_
K-cnt_i is shifted, and in+40 period rising edges of I, obtains the address code with address code dly_tb_d_1 synchronism output
Dly_tb_k_i, i.e. k-i.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all in essence of the invention
Made any modifications, equivalent replacements, and improvements etc., should all be included in the protection scope of the present invention within mind and principle.
Claims (3)
1. a kind of synthetic aperture address code generating method based on FPGA, which comprises the following steps:
The generation of address code is divided into 16 tunnels using FPGA parallel characteristics by S10, by the figure of aperture processing two sides deficiency aperture length
As being handled respectively with the image of intermediate aperture length enough, three main roads, the high-speed parallel processing of 3*16 path are formed
Structure；
The synthesis width of S20, aperture processing count, and counter cnt_i, cnt_j, the cnt_k in three main roads are carried out not respectively
Same nested counting: in the first via, cnt_i circulation counts up to 0 from cnt_k；Cnt_j counts up to DIS_LINE/16 from 0, is 16
Road line number is counted, and wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to AL-1 from 0,
Middle cnt_k cnt_j is every complete a wheel circulation when change it is primary, to image before the part in complete aperture insufficient aperture length
The aperture of AL is cumulative to be counted；In second tunnel, cnt_i circulation counts up to 0 from AL-1；Cnt_j counts up to DIS_LINE/ from 0
16, wherein cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to DIS_DOOR-AL-1 from AL, wherein
Cnt_k changes once in the every one wheel circulation of completion of cnt_j, and the part progress aperture for falling within complete pore size to image is cumulative
It counts；In third road, cnt_i circulation counts up to 0 from DIS_DOOR-cnt_k-1；Cnt_j counts up to DIS_LINE/16 from 0,
Middle cnt_j changes primary in the every one wheel circulation of completion of cnt_i；Cnt_k counts up to DIS_DOOR-1 from DIS_DOOR-AL,
Middle cnt_k changes primary in the every one wheel circulation of completion of cnt_j, wherein every one wheel of completion of cnt_i in three main road counters
Respective refresh_flag when i.e. cnt_i=0, is set to high level a cycle, provides a refresh signal by circulation, is used
It is handled in aperture, cumulative to the aperture of image insufficient aperture length AL after the part in complete aperture to count, DIS_
LINE is that range line corresponds to row, and DIS_DOOR is range gate respective column, and AL is aperture length points；
S30 generates address code d-1；
S40 generates address code k-i.
2. the method according to claim 1, wherein the S30 the following steps are included:
S31 adds (rd_num-1) × (DIS_ using combinational logic circuit according to input number rd_num on cnt_j
LINE/16) obtain certain in 16 tunnels all the way in point and image border to be calculated pixel distance, utilize fixed point-floating-point to convert IP
Core is converted into 32 single precision floating datums, if in input data being the i-th period, then rising in+4 periods of I
Edge can obtain respective value R0_j_pix；The calculating that cnt_i-AL/2-1 is realized using combinational logic is obtained as a result, be denoted as x_i,
And 32 single precision floating datums are converted into using fixed point-floating-point conversion IP kernel, it is tied in+4 period rising edges of I
Fruit is denoted as fp_x_i；
S32 carries out the calculating of R0_j_pix × 1/fs by floating-point multiplier, and wherein 1/fs is the inverse of sample frequency, that is, adopts
Sample period corresponding 32 single-precision floating point values obtain multiplication result in+7 period rising edges of I, are denoted as t_pix, are wave beam
The two-way time used in tested point is reached from testing image edge；The meter of fp_x_i × delta_sa is carried out by floating-point multiplier
It calculates, delta_sa is the half of length of real aperture, i.e. azimuth resolution, obtains multiplication knot in+7 period rising edges of I
Fruit is denoted as x_i_rl, is actual distance of the sampled point to be calculated to air route coordinate origin；
S33, t_pix utilize floating-point adder to carry out with two-way time Ts used in most short vertical range of the air route to imaging region
Summation, obtains wave beam in+10 period rising edges of I and corresponds to two-way time t_ from the vertical range that air route reaches point to be calculated
R0_j；X_i_rl is subjected to square operation using floating-point multiplier, obtains x_i_sqr in+10 period rising edges of I；
T_R0_j is multiplied by S34 using floating-point multiplier single-precision floating point value corresponding with c/2, and c is velocity of wave, I+
13 period rising edges obtain the one way vertical range R0_j that wave beam reaches point to be calculated from air route；X_i_sqr is utilized into displacement
Register is shifted, and is allowed to obtain x_i_sqr_dly in+16 period rising edge outputs of I, be used for align data；
R0_j is carried out square operation using floating-point multiplier, obtains result R0_j_ in+16 period rising edges of I by S35
sqr；
X_i_sqr_dly is added with R0_j_sqr using floating-point adder by S36, is obtained in+19 period rising edges of I
To point to be calculated to square R_sqr of the one way oblique distance of coordinate origin；
R_sqr is carried out evolution operation using floating-point square-root extractor, obtains point to be calculated in+29 period rising edges of I and arrive by S37
The one way oblique distance R of coordinate origin；
R is multiplied, in+32 period rising edges of I by S38 using floating-point multiplier single-precision floating point value corresponding with 2/c
It obtains energy converter and receives round trip delay time td used in the echo of point to be calculated；
Td is subtracted used in most short vertical range of the air route to imaging region Ts pairs of the two-way time using floating-point subtracter by S39
The single-precision floating point value answered obtains Tr in+35 period rising edges of I；
Tr was multiplied, in+38 periods of I by S310 using floating-point multiplier single-precision floating point value corresponding with sample frequency fs
Rising edge obtains tested point round trip delay delay_pix；
Delay_pix is carried out the conversion of floating-point to fixed-point number, and is patrolled using combination by S311 using floating-point-fixed point conversion IP kernel
It collects and realizes delay_fixed-1 operation, obtain tested point address code dly_tb_d_1, i.e. d-1 in+40 period rising edges of I.
3. the method according to claim 1, wherein the S40 the following steps are included:
S41 forms combinational logic circuit calculated value cnt_k-cnt_i using the value of cnt_i in S20 and cnt_k；
S42 is shifted cnt_k-cnt_i using shift register, in+40 period rising edges of I, acquirement and address code
The address code dly_tb_k_i of dly_tb_d_1 synchronism output, i.e. k-i.
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