CN1384675A - Gaussian minimum frequency deviation digital key modulation method and device - Google Patents

Abstract

The present invention is Gaussian minimum frequency deviation digital key modulation method and device. By means of the base band modulation phase of modulation bit and the sine and cosine table constituted by the whole quantized phases, orthogonal base band signal I and Q are obtained. By using FPGA, as one general programmable integrated device, and outer memory, GKSK orthogonal base band signal is obtained. This method is convenient, flexible and fast in design and upgrading, and is favorable to raising system performance and lowering hardware cost.

Description

A kind of Gaussian minimum frequency deviation digital key modulation method and device

The invention belongs to modulator approach and device in the moving communicating field, relate in particular to a kind of GMSK (Guassian Minimum Shift Keying) digital modulation implementation method.

At moving communicating field, digital modulation technique has good anti-interference and potential language cryptographic capabilities.Minimum shift keying (MSK) is a kind of binary digit frequency modulation, and it has performances such as constant amplitude envelope, arrowband and coherent detection ability be good.The GMSK modulation is a kind of MSK modulation to differential coding data adding premodulated gauss low frequency filter, can control the power spectrum of its output when keeping the constant amplitude envelope trait.The MSK modulation is that modulation index is 0.5 binary frequency modulation, and one of premodulated Gauss's bandpass filter is changed bandwidth B T=0.3, and the basic principle of GMSK modulation as shown in Figure 1.

The data information transmission speed of input difference encoder 11 is 270.833kbit/s, differential encoder be used to finish will input 0,1 information become amplitude and be ± 1 relocatable code, this function was divided into for two steps and realizes:

The first step is with the data value d of each modulation bit _i∈ [0,1] carries out differential coding, becomes the unipolarity relocatable code

${\hat{d}}_i=d_i\&CirclePlus;d_{i-1}---(d_i\&Element;\{\mathrm{0,1}\left\}\right)------\left(1\right)$ In second step, be for conversion into bipolarity relocatable code α through amplitude again _i: $a_i=1-2{\hat{d}}_i-----(a_i\&Element;\{-\mathrm{1,1}\left\}\right)-----\left(2\right)$ The impulse response of gauss low frequency filter 12 is h (t): $h\left(t\right)=\frac{\sqrt{2\mathrm{\&pi;}}\mathrm{<figure-callout\; id="2"\; label="B\; ln"\; filenames="A01112781.300181.png"\; state="\{\{state\}\}">B</figure-callout>}}{\sqrt{\ln }}\exp (-\frac{2{\mathrm{\&pi;}}^2{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="A01112781.300181.png"\; state="\{\{state\}\}">B</figure-callout>}}^2}{{\ln }^2}{t}^2)-----\left(3\right)$

Wherein the bandwidth B of gauss low frequency filter 12 is 0.3/T;

After data flow process frequency shift keying 13 (MSK) modulation that enters gauss low frequency filter 12, output radio frequency GMSK signal S (t): $S\left(t\right)=\sqrt{\frac{{2E}_s}{T}}\cos (2\mathrm{\&pi;}{f}_{0}t+\mathrm{\&psi;}\left(t\right)+{\mathrm{\&psi;}}_0)-----\left(4\right)$ Be expressed as with the quadrature modulation mode: $S\left(t\right)=\sqrt{\frac{{2E}_s}{T}}[I\&times;\cos (2{\mathrm{\&pi;f}}_{0}t+{\mathrm{\&psi;}}_0)-Q\&times;\sin (2\mathrm{\&pi;}{f}_{0}t+{\mathrm{\&psi;}}_0)]---\left(5\right)$ Wherein ψ (t) is the phase place of GMSK baseband signal;

f ₀Be the radio-frequency carrier signal frequency;

E _SBe the modulation bit energy;

ψ ₀Initial phase for radio-frequency carrier signal.Therefore, the base band orthogonal signalling are:

I＝cos(ψ(t))

Q＝sin(ψ(t)) (6)

Can draw from top theory analysis, can look into the sine and cosine table that constitutes after the whole phase quantization of 0～2 π again, draw digital orthogonal baseband signal I and Q by obtaining the phase place of baseband signal.

In existing GSM cell mobile communication systems, the realization of GMSK digital modulation comprises dual mode: 1) analog circuit, and the complex structure of this method, the cost height, very flexible, the stable performance degree of realization is poor, and precision is not high; 2) special-purpose ASIC module, this method is because of being subjected to limit module, and very flexible, cost height are used in design.Development along with modern crafts and device, integrated level, speed and the design means of Field Programmable Gate Array FPGA (Field Programmable Gate Array) rapidly improve, provide attainable basis for FPGA is used for the GMSK modulation, also reflected the needs of current techniques development.

The objective of the invention is according to the continuous characteristics of Gauss's FM signal phase change, adopt recursion and brachymemma quantification technique to realize the method for GMSK baseband modulation, and utilize general integrated device-Field Programmable Gate Array FPGA and external memory storage to obtain the GMSK digital orthogonal baseband signal, this method has convenient, the characteristics fast flexibly of design upgrading, the requirement that compliance with system is upgraded, the flexibility of increase system and the degree of freedom also help improving simultaneously performance, reduce hardware cost.

To achieve these goals, the present invention adopts digital processing technology to realize GMSK base band orthogonal signalling, on this basis, adopts general quadrature modulation mode can realize radio frequency GMSK modulation signal easily.

Below, with reference to accompanying drawing, for those skilled in the art that, from the detailed description to the inventive method, above-mentioned and other purposes of the present invention, feature and advantage will be apparent.

Fig. 1 represents the basic principle figure of GMSK modulation;

Fig. 2 represents that the present invention adopts FPGA and external memory storage to carry out the rough schematic of quadrature base band GMSK modulation;

Fig. 3 provides GMSK baseband modulation phase place ψ (t) and the baseband modulation phase place of a last modulation bit and the recurrence relation table of additive phase;

Fig. 4 represents the rectangular pulse response function g (t) of Gaussian filter and the graph of relation between the t/T;

Fig. 5 represents the flow chart of method that the present invention adopts;

Fig. 6 represents an embodiment who adopts FPGA and EPROM to carry out GMSK baseband modulation method;

Fig. 7 adopts the frequency spectrum analogous diagram of the GMSK baseband modulation signal of principle embodiment shown in Figure 6;

Fig. 8 adopts the GMSK baseband modulation signal of principle embodiment shown in Figure 6 and the range error analysis chart of desirable baseband modulation signal;

Fig. 9 adopts the GMSK baseband modulation signal of principle embodiment shown in Figure 6 and the phase error analysis chart of desirable baseband modulation signal.

GMSK baseband modulation method is to utilize digital processing technology to realize the basis of GMSK modulation signal, and this method can realize that the parallel bit rate is that the N times of GMSK to base band quadrature (I/Q) signal of modulation bit rate modulates, and wherein N is the integer greater than 2.

With reference to figure 2, the GMSK signal generally adopts the mode of quadrature modulation to realize, input bit is flowed through after FPGA21 handles, and searches the method for prepositioned sine and cosine table in the external memory storage 22 and obtains base band quadrature I and Q signal.

Table shown in Figure 3 provides the recurrence relation of the baseband modulation phase place of input modulation bit.From this table, can recognize that the method for GMSK modulation is actually and forms by recurrence relation.Because GMSK is a kind of Gauss's FM signal, its envelope is constant, therefore, information is included among the phase place, and its phase change is continuous, the GMSK baseband signal can be divided on time domain with the modulation bit duration T is the signal in cycle, any time t can be expressed as t=kT+ τ (0≤τ≤T wherein, k is the modulation bit sequence number), the recurrence relation of GMSK baseband signal phase place ψ (t) is like this: the baseband modulation phase place of any time t was formed by baseband modulation phase place (ψ (kT)) and additive phase (ψ (τ)) two parts addition of a last modulation bit last moment.Additive phase is promptly: $\mathrm{\&psi;}\left(\mathrm{\&tau;}\right)=\frac{\mathrm{\&pi;}}{2}{\&Integral;}_0^{\mathrm{\&tau;}}\left[\underset{i=-\&infin;}{\overset{\&infin;}{\mathrm{\&Sigma;}}}{a}_{k-i}g(t^{\&prime;}-\mathrm{iT})\right]{\mathrm{dt}}^{\&prime;}$

Owing to include the rectangular pulse response g (t) of Gaussian filter among the ψ (τ), its span be (∞ ,+∞), the relation of g (t) function and t/T need be carried out brachymemma to g (t) and handle shown in curve among Fig. 4, and brachymemma length is big more, error is more little, but operand is also big more.When brachymemma length is 5T, account for 99.99994658%, when brachymemma length is got 7T, account for 99.9999999999%, composition error and operand two aspect factors, brachymemma length is defined as 5T～7T, in this brachymemma length, operand is not too big, but precision is enough.

The quantification of additive phase ψ (τ) is mainly comprised the quantification of time and amplitude two aspects.Temporal quantification is relevant with the index of communication system, has determined the speed of I and Q, if a bit period is quantized into N point, the brachymemma length of g (t) is got MT, and so, the value of τ just has the N kind: $\frac{T}{N},\frac{2T}{N},\frac{3T}{N},\&CenterDot;\&CenterDot;\&CenterDot;...T;$ Like this, g (t) is quantized into M * N point of quantification, and ψ (τ) is quantized into N additive phase.According to the recurrence relation of baseband modulation phase place, in a bit duration, the phase modulation of a last modulation bit last moment is constant, and the baseband modulation phase place is quantized into N point, so the speed of I and Q is N times of modulation bit rate; Quantification on amplitude has determined the precision of additive phase ψ (τ), and existing register generally has 8,16,24 and 32.Use 8 bit representations, quantization error is 0.2289 °, uses 16 bit representations, and quantization error is 0.000894 °, therefore becomes 16 enough to satisfy precision amplitude quantizing.

If the brachymemma length of the time of consideration is taken as 5T, then $\mathrm{\&psi;}\left(\mathrm{\&tau;}\right)=\underset{i=-2}{\overset{2}{\mathrm{\&Sigma;}}}{a}_{k-i}\left[\frac{\mathrm{\&pi;}}{2}{\&Integral;}_0^{\mathrm{\&tau;}}g(t^{\&prime;}-\mathrm{iT}){\mathrm{dt}}^{\&prime;}\right]$

Wherein the parameter of g (t) is determined, as can be seen, additive phase ψ (τ) is relevant with two factors:

1) bipolarity of two modulation bit of bipolarity relocatable code of this modulation bit and front and back thereof is relative

Sign indicating number;

2) value of τ.

Draw thus, can determine the phase modulation curve shape of a bit duration by per 5 adjacent modulation bit.Therefore when brachymemma length was got 5T, in the bit duration, the phase modulation curve had 2 ⁵Kind.

In a bit duration, the bipolarity relocatable code information of 5 adjacent modulation bit has determined 2 ⁵Plant the additive phase curve, every kind of additive phase curve is quantized into N point, and every N point formed an additive phase group, and each point is represented with 16 bit codes, for realizing conveniently, saves resource and improves processing speed, can be with 2 in the bit duration ⁵The centrifugal pump of kind of additive phase group is made an additive phase table, the capacity of this additive phase table bitwise, the size of table is M * N * 16 (bits).The arrangement of additive phase table can be with the unipolarity relocatable code of 5 adjacent modulation bit as placing 2 ⁵Plant the relative address sign indicating number of additive phase group, N the additive phase that sequence arrangement is quantized in each additive phase group.Therefore, the additive phase group of the unipolarity relocatable code of per 5 adjacent modulation bit decision is the relative address sign indicating number of N additive phase group doubly at the relative address sign indicating number of additive phase table.In addition, conveniently the data of additive phase table have been done the processing of phase place patrix 2 π for realizing.

The placement of sine and cosine table is that phase place is arrived the quantification of big i.e. 0 to 2 π from childhood is tactic in proper order, therefore, can the relative address sign indicating number of phase place as inquiry sine and cosine table will be quantized, the size of sine and cosine table is relevant with the quantification gradation of phase place, if quantification gradation is the K level, sine and cosine value L bit representation, the size of sine and cosine table are K * L * 2 (bits).L gets more than 12, and baseband phase is got 12～16, and quantification gradation K is 2 ¹²～2 ¹⁶

Fig. 5 provides and adopts the inventive method to carry out the schematic flow sheet that the GMSK modulation realizes, below this flow process is described.

At first enter piece 501 initialization, comprise initialization, the initialization of sine and cosine table and the several aspects of initialization of register of additive phase table.The initialization of additive phase table and sine and cosine table is placed into corresponding memory space respectively with certain tactic table exactly, and obtains the leading address of table; Simultaneously with address register and phase register initialization zero.Address register is used for depositing the address of additive phase, and phase register is used for depositing the baseband modulation phase place of a modulation bit last moment.After initialization is finished, enter piece 502, get first modulation bit,, enter piece 503 then and carry out differential coding, obtain the unipolarity relocatable code of the current modulation bit consistent with the speed of getting modulation bit as current modulation bit; Entering piece 504 then is stored in the unipolarity relocatable code in the corresponding bit of address register, obtain the relative address sign indicating number of current additive phase group, add the leading address of additive phase table, become the first address of additive phase group, if additive phase gauge outfit address is 0, the first address of additive phase group is exactly the relative address sign indicating number, according to the first address of additive phase group, as long as the content of address register is added up 1, can obtain N additive phase address in the additive phase group in proper order.The bit of placing current unipolarity relocatable code is relevant with the arrangement of the unipolarity relocatable code of M adjacent modulation bit of additive phase table, for example, for a N be 16, M is 5 additive phase table, its relative address sign indicating number has 9, its high 5 unipolarity relocatable codes of having arranged from high to low on time from back to front, then current unipolarity relocatable code should be placed into high 5 highest order, otherwise current unipolarity relocatable code should be placed on high 5 lowest order.Look into the additive phase table in piece 505, the content according to address register obtains additive phase; Enter piece 506 then, the baseband modulation phase place addition of the last modulation bit last moment in additive phase of obtaining tabling look-up and the phase register obtains a baseband modulation phase place of current modulation bit, as the relative address sign indicating number of sine and cosine table; In piece 507,, obtain the inquire address of sine and cosine table with the leading address addition of baseband modulation phase place and sine and cosine table; Enter step 508 then,, obtain one group of digital orthogonal baseband signal I and Q according to the inquire address of sine and cosine table, and output; After finishing the modulation of a time quantization point, judge whether all to be 1 to hanging down 4 in the address register, if do not satisfy condition, N the additive phase that shows the additive phase group also do not got, and the modulation of current modulation bit is not also finished, and enters piece 509, the additive phase address adds 1, obtain the inquire address of the next additive phase of this additive phase group, turn back to piece 505, be used to finish the quadrature baseband modulation signal I/Q of next point of quantification; If satisfy condition, show N the quadrature baseband modulation signal I/Q that finishes current modulation bit, enter piece 510, the content of phase register is refreshed, N baseband modulation phase place deposited in the phase register, when next modulation bit was modulated, as the baseband modulation phase place of a last modulation bit last moment, to produce (piece 506) used for the phase place of calculating next bit duration.Then enter piece 511, the content of address register is moved to left accordingly or moves to right, will hang down 4 positions 0 then, enter piece 512, take off a modulation bit, turn back to piece 503, finish the function of N quadrature baseband modulation signal I/Q again as current bit.

Can find out that from flow chart method of the present invention has adopted two circulations, the effect of interior circulation is N the I/Q value that produces in the bit duration, and outer circulation is the I/Q value that produces in the different bit durations.

The principle process of the inventive method that provides in conjunction with Fig. 5, Fig. 6 provides the structural representation that utilizes FPGA and external memory storage to realize a preferred embodiment of the present invention.FPGA60 finishes the memory function and the logic function of additive phase table among Fig. 5, logic function mainly is the modulation bit according to input, through differential encoder 61, generation has the address of the data storage of additive phase table, with the baseband modulation phase place addition of last bit last moment of the additive phase that obtains and phased memory, obtained current baseband modulation phase place again.Externally stored the sine and cosine table in the memory 65, the leading address of sine and cosine table is 0, can obtain base band quadrature I and Q signal with the baseband modulation phase place as the address of external memory storage.Different Logic function according to FPGA60 realizes can be divided into its structure differential encoder 61, address generator 62, data storage 63 and 64 4 parts of baseband modulation phase generator.

0,1 information that differential encoder 61 is finished input becomes relocatable code, amplitude is constant, it is made up of 610,611 and XOR gate 612 of two triggers, and the rate of change of trigger 610,611 is consistent with modulation bit rate, finishes the conversion of modulation bit absolute code and relocatable code.The function that relocatable code converts bipolar code to has been included in the additive phase table in the data storage 63.

Enter address generator 62 through the relocatable code behind the differential coding, address generator is made up of move to right shift register 620 and modulo-N counter 621 of one 5 bit, and the speed of 5 bit shift registers 620 is modulation bit rate; The design speed of modulo-N counter 621 is relevant with the speed of I and Q, if use mould 16 counters, then the parallel bit speed of I and Q is 16 times modulation bit rate; The output of shift register 620 and modulo-N counter 621 is spliced into the address of additive phase memory from high to low, and the rate of change of address is a N modulation bit rate doubly.For example: with high 5 as the address of the output of shift register, as low 4, the rate of change of address is 16 times a modulation bit rate with the output of mould 16 counters.

In order to reduce time-delay, the additive phase table is stored in two data memories 630 and 631, half table before and after data table stores device A630 and data table stores device B631 have deposited respectively, leading address all is 0, is selected the output of data table stores device A630 or data table stores device B631 by the highest order control of address.In order to prevent that adder from overflowing the trouble of bringing in the realization, the data of additive phase table have been done the processing of phase place patrix 2 π, data table stores device A630 and data table stores device B631 have adopted the design philosophy of decoder in realization, the resource that takies be the ROM mode realize 20%, and time delay is below 15ns, save resource, accelerated addressing speed.

Baseband modulation phase generator 64 comprises phased memory 640, adder 641 and output latch 642, be used for realizing the addition function and the output control of content in additive phase and the phased memory, the speed of phased memory is modulation bit rate, the speed of output latch 642 and additive phase output is N times of modulation bit rate, exports the inquire address of the baseband modulation phase place of N times of modulation bit rate as external memory storage 65 by it.

For reducing cost, the sine and cosine table leaves in the external memory storage, and the reading rate of external memory storage EPROM is a N times of modulation bit rate.

Fig. 7 provides the frequency spectrum analogous diagram of the digital orthogonal baseband signal that adopts preferred embodiment output.Abscissa among the figure and ordinate are represented frequency (Hz of unit) and amplitude (dB of unit) respectively, setting I and Q speed is 16 times of modulation rates, 16 quantification phase places and 12 I/Q export the GMSK baseband modulation signal of realizing, gather 2400 I/Q sampling points, obtain with Computer Simulation.The frequency spectrum of GMSK baseband modulation signal drops within the 200kHz (monolateral band) as can be seen, and when frequency deviation was 200kHz, its amplitude greater than-30dBc, illustrated that the frequency spectrum of GMSK baseband modulation signal has satisfied the requirement of standard with respect to the decay of 0 frequency deviation.

Fig. 8 has provided the range error analysis of GMSK baseband modulation signal.Abscissa is 2400 I/Q sampling points, ordinate is the relative error of GMSK baseband signal amplitude, it is the absolute error of GMSK baseband signal amplitude and the relative value of corresponding desirable amplitude, the amplitude peak error is 3.390E-6 as can be seen, explanation realizes that with the present invention the caused range error of GMSK baseband modulation signal is little, the precision height.

Fig. 9 has provided the error phase analysis of GMSK baseband modulation signal.Abscissa is 2400 I/Q sampling points, ordinate is a GMSK baseband signal absolute phase error, it is the phase place of 2400 GMSK baseband signals and the difference of corresponding desired phase, unit is a radian, the maximum phase error is the 1.36e-4 radian as can be seen, promptly 0.0078 °, illustrate that the phase error of the GMSK baseband modulation signal generation that realizes with the present invention is less, the precision height.

The invention provides a kind of FPGA implementation method and device of practicable GMSK digital modulation, the advantage that adopts this method to realize comprises:

1, simple, it is few to take resource, has guaranteed modulation accuracy again simultaneously, has improved modulating performance.Realize base band GMSK modulation with FPGA and external memory storage, it is little to have time delay, the interface characteristic of simple, and it is 0 all that its initialization makes the leading address of additive phase table and sine and cosine table, has reduced operand, has simplified realization.

2, with flexible design FPGA realization efficiently GMSK digital modulation, increased the flexibility and the degree of freedom of system, reduced the complexity and the cost of system modulation module, FPGA only takies resource below 5,000.

The front provides the description to preferred embodiment, so that any technical staff in this area can use or utilize the present invention.To the various modifications of these embodiment, be conspicuous to those skilled in the art, can be applied to other embodiment to total principle described here and not use creativeness.Thereby, the embodiment shown in the present invention will be not limited to here, and the wide region of principle that should disclose and new feature according to meeting here.

Claims (20)

1, a kind of Gaussian minimum frequency deviation digital key modulation method said method comprising the steps of:

A) carry out initialization;

B) carry out differential coding according to modulation bit, obtain the unipolarity relocatable code of current modulation bit;

C) described unipolarity relocatable code is deposited, obtained the relative address sign indicating number, and add the leading address of additive phase table, generate the inquire address of additive phase group;

D), find one group of additive phase according to described additive phase group polling address and additive phase table;

E), generated the relative address sign indicating number of the baseband modulation phase place of current modulation bit as the sine and cosine table according to described additive phase and the baseband modulation phase place of a last modulation bit last moment;

F), obtain the inquire address of sine and cosine table with the baseband modulation phase place of described current modulation bit and the leading address addition of sine and cosine table;

G) according to inquire address, look into described sine and cosine table, obtain digital orthogonal baseband signal.

2, method according to claim 1 is characterized in that, described initialization further comprises:

1) initialization of the initialization of additive phase table and sine and cosine table specifically comprises the respective stored space that the table of a definite sequence is placed into described additive phase table and sine and cosine table respectively, and obtains the leading address of table;

2) initialization of register specifically comprises address register and phase register are initialized as 0.

3, method according to claim 2 is characterized in that, described address register is used to deposit the address of additive phase, and described phase register is used to deposit the baseband modulation phase place of a modulation bit last moment.

4, method according to claim 1 is characterized in that, the speed of described current unipolarity relocatable code is identical with modulation bit speed.

5, method according to claim 1 is characterized in that, the baseband modulation phase place of current modulation bit in the described step e):

ψ(t)＝ψ(KT)+ψ(τ)

Wherein, K represents the modulation bit sequence number;

ψ (KT) was the baseband modulation phase place of a last modulation bit last moment;

ψ (τ) is an additive phase.

6, method according to claim 1, it is characterized in that, in a bit period, described additive phase is quantified as N point according to following formula, this N additive phase has been formed the additive phase group, and wherein the length of blocking of the rectangular pulse of Gaussian filter response g (t) is got MT: $\mathrm{\&psi;}\left(\mathrm{\&tau;}\right)=\frac{\mathrm{\&pi;}}{2}{\&Integral;}_0^{\mathrm{\&tau;}}\left[\underset{i=-\&infin;}{\overset{\&infin;}{\mathrm{\&Sigma;}}}{\mathrm{\&alpha;}}_{k-i}g(t^{\&prime;}-\mathrm{iT})\right]{\mathrm{dt}}^{\&prime;}$

7, method according to claim 6 is characterized in that, described M and N are integer.

8, method according to claim 7 is characterized in that, described M is 5～7 integer, and N is 2～32 integer.

9, a kind of GMSK (Guassian Minimum Shift Keying) digital modulation device, described device comprises:

Differential encoder comprises two triggers and an XOR gate, carries out XOR according to two trigger outputs of clock control, and the modulation bit that is used to finish input becomes the unipolarity relocatable code;

Address generator, comprise a M bit shift register and modulo-N counter, the direction of displacement of described shift register is relevant with the arrangement of additive phase table, be used for arrangement according to the additive phase table, described shift register carries out the immigration of certain orientation with the unipolarity relocatable code of described differential encoder output, the address that described modulo-N counter and shift register combination produce additive phase;

Data storage is used to deposit the additive phase table;

The baseband modulation phase generator comprises phased memory, adder and output latch, is used to realize additive phase and the adduction output control mutually of a last bit last moment phase modulation;

External memory storage is used to deposit the sine and cosine table.

10, device according to claim 9 is characterized in that, the displacement rate of change of shift register is a modulation bit rate, is used to produce the high position of additive phase inquire address.

11, device according to claim 9 is characterized in that, the count rate of described modulo-N counter is a N times of modulation bit rate, is used to generate the low level of additive phase inquire address, and quantizes the additive phase accumulated counts to N in the bit period.

12, device according to claim 9 is characterized in that, the additive phase address of N times of modulation bit rate of described address generator output.

13, device according to claim 9 is characterized in that, described phased memory is used to store the baseband modulation phase place of a bit last moment.

14, device according to claim 9 is characterized in that, the baseband modulation phase place of N times of modulation bit rate of described output latch control output.

15, device according to claim 9, it is characterized in that, described data storage comprises data storage A and data storage B, and described data storage A is used to deposit preceding half additive phase table, and described data storage B is used to deposit later half additive phase table.

16, device according to claim 9 is characterized in that, the reading rate of described external memory storage is a N times of modulation bit rate.

17, device according to claim 16 is characterized in that, described external memory storage can be selected PROM and FLASH.

18, device according to claim 9 is characterized in that, described N and M are integer.

19, device according to claim 18 is characterized in that, described M is 5～7 integer, and N is 16～32.

20, device according to claim 9 is characterized in that, the rate of change that is used for the described trigger of differential coding is a modulation bit rate.

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