CN110838843A - Anti-irradiation DDS circuit - Google Patents
Anti-irradiation DDS circuit Download PDFInfo
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- CN110838843A CN110838843A CN201911152636.7A CN201911152636A CN110838843A CN 110838843 A CN110838843 A CN 110838843A CN 201911152636 A CN201911152636 A CN 201911152636A CN 110838843 A CN110838843 A CN 110838843A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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Abstract
The invention discloses an anti-irradiation DDS circuit, and belongs to the technical field of integrated circuits. The anti-radiation DDS circuit comprises a DDS inner core and a DDS outer core, wherein the DDS inner core is used for generating interleaved digital sinusoidal signals date1 and date 2; the digital data transmitting module is used for transmitting digital sinusoidal signals date1 and date2 to the analog receiving stage and the DAC module; the dynamic correction circuit is characterized in that the digital data sending module generates a data clock dco and sends the data clock dco to the dynamic correction circuit, the output end of the dynamic correction circuit generates a selection signal and sends the selection signal to the clock delay module, and the dynamic correction circuit, the digital data sending module and the clock delay module form a negative feedback loop. The invention can online correct phase deviation error caused by SET effect without updating configuration signal by introducing negative feedback loop, simplifies circuit configuration and use difficulty in irradiation application, and can be widely applied to anti-irradiation DDS or related large-scale digital-analog mixed circuit.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an anti-irradiation DDS circuit.
Background
A DDS (Direct Digital Synthesizer, Direct Digital frequency Synthesizer) is a device that adopts a full Digital frequency and phase waveform synthesis technology. The radiation-resistant DDS has the characteristics of direct processor control, high-speed programmable configuration, precise frequency hopping and fine adjustment, good stability and the like, is widely applied to the fields of radar, broadband communication and measurement and control, and has larger use requirements as a special reinforced device in the field of aerospace.
Due to the SET effect of high-energy protons and neutrons in a space radiation environment, various soft errors of a device can be caused, and for a DDS (direct digital synthesizer), the SET effect can affect a clock or a configuration signal to cause phase offset of an output digital signal, so that sampling errors of a DAC (digital-to-analog converter) at the later stage are caused; due to the fact that the working speed is high, the offset cannot be corrected in time in the traditional TMR reinforcing mode.
Disclosure of Invention
The invention aims to provide an anti-irradiation DDS circuit to solve the problem that the traditional DDS is easily affected by the SET effect to generate phase offset of an output digital signal, so that a subsequent DAC (digital-to-analog converter) is mistakenly adopted.
In order to solve the above technical problem, the present invention provides an anti-irradiation DDS circuit, including:
a DDS core generating interleaved digital sinusoidal signals date1 and date 2;
the digital data transmitting module is used for transmitting digital sinusoidal signals date1 and date2 to the analog receiving stage and the DAC module;
the anti-radiation DDS circuit further comprises:
the dynamic correction circuit is characterized in that the digital data sending module generates a data clock dco and sends the data clock dco to the dynamic correction circuit, the output end of the dynamic correction circuit generates a selection signal and sends the selection signal to the clock delay module, and the dynamic correction circuit, the digital data sending module and the clock delay module form a negative feedback loop.
Optionally, the dynamic correction circuit includes an inverter, a D flip-flop DEF1, a D flip-flop DEF2, an exclusive or gate XOR, an AND gate AND, AND an N-bit counter;
the C input end of the D flip-flop DEF1 and the inverter input end are both connected with an analog receiving clock Sysclk/2, the D input ends of the D flip-flop DEF1 and the D flip-flop DEF2 are both connected with a data clock dco, and the inverter output end is connected with the C input end of the D flip-flop DEF 2;
the Q output ends of the D flip-flop DEF1 AND the D flip-flop DEF2 are respectively connected with two input ends of the exclusive-OR gate XOR, the output end of the D flip-flop DEF1 AND the Q output end of the D flip-flop DEF2 are connected with one input end of the AND gate AND, AND the other input end of the AND gate AND is connected with a function enabling signal en;
AND the AND gate AND output end is connected with the enabling end EN of the N-bit counter, AND the CLK end of the N-bit counter is connected with the counter clock Count _ CLK.
Optionally, the phase of the data clock dco is the same as the digital sinusoidal signals date1 and date2 output by the DDS core.
Optionally, the analog receiving clock Sysclk/2 has the same frequency and the same phase as the receiving clock of the analog receiving stage.
Optionally, the function enable signal en is used to control the function enable of the dynamic correction circuit.
Optionally, the counter clock Count _ clk is an M-frequency division clock of the DDS core clock, where M is determined according to actual needs, and M =1, 2, or 4.
Optionally, the N value of the N-bit counter is determined by the number of stages of the clock delay module, and the number 2N is greater than the number of stages of the clock delay module.
Optionally, the dynamic correction circuit outputs a 2N-bit control code to the clock delay module.
The invention provides an anti-radiation DDS circuit, which comprises a DDS core, a data processing circuit and a data processing circuit, wherein the DDS core is used for generating interleaved digital sinusoidal signals date1 and date 2; the digital data transmitting module is used for transmitting digital sinusoidal signals date1 and date2 to the analog receiving stage and the DAC module; the dynamic correction circuit is characterized in that the digital data sending module generates a data clock dco and sends the data clock dco to the dynamic correction circuit, the output end of the dynamic correction circuit generates a selection signal and sends the selection signal to the clock delay module, and the dynamic correction circuit, the digital data sending module and the clock delay module form a negative feedback loop.
The invention can online correct phase deviation error caused by SET effect without updating configuration signal by introducing negative feedback loop, simplifies circuit configuration and use difficulty in irradiation application, and can be widely applied to anti-irradiation DDS or related large-scale digital-analog mixed circuit.
Drawings
FIG. 1 is a schematic diagram of the structure of an anti-radiation DDS circuit provided by the invention;
FIG. 2 is a schematic diagram of a dynamic calibration circuit according to the present invention;
fig. 3 shows the timing of signals before and after phase shifting of a conventional DDS circuit.
Detailed Description
The radiation-resistant DDS circuit provided by the invention is further described in detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides an anti-irradiation DDS circuit, the structure of which is shown in figure 1, comprising a DDS Core, wherein a digital Core clock Core _ clk is input into the DDS Core, and the DDS Core generates interleaved digital sinusoidal signals date1 and date2 to a digital data sending module; the digital data transmitting module transmits digital sinusoidal signals date1 and date2 to the analog receiving stage and the DAC module; an analog receiving clock Sysclk/2 is also input into the analog receiving stage, and a system clock Sysclk is also input into the DAC module; the DAC module generates an Analog output signal Analog _ out. Preferably, the radiation-resistant DDS circuit further includes a dynamic correction circuit, the digital data transmitting module generates a data clock dco to the dynamic correction circuit, an output end of the dynamic correction circuit generates a selection signal Delay _ select to the clock Delay module, and an analog receiving clock Sysclk/2 is transmitted to the digital data transmitting module through the clock Delay module. The dynamic correction circuit, the digital data sending module and the clock delay module form a negative feedback loop, automatically judge and feed back and adjust when phase deviation caused by SET effect occurs, and lock after phase recovery.
Specifically, referring to fig. 2, the dynamic correction circuit includes an inverter INV, a D flip-flop DEF1, a D flip-flop DEF2, an XOR gate XOR, an AND gate AND, AND an N-bit counter; wherein the C input terminal of the D flip-flop DEF1 and the inverter input terminal are both connected to an analog receive clock Sysclk/2, the D input terminals of the D flip-flop DEF1 and the D flip-flop DEF2 are both connected to a data clock dco, and the inverter output terminal is connected to the C input terminal of the D flip-flop DEF 2; the Q output ends of the D flip-flop DEF1 AND the D flip-flop DEF2 are respectively connected with two input ends of the exclusive-OR gate XOR, the output end of the D flip-flop DEF1 AND the Q output end of the D flip-flop DEF2 are connected with one input end of the AND gate AND, the other input end of the AND gate AND is connected with a function enabling signal en, the function enabling signal en is used for controlling the function enabling of the dynamic correction circuit, AND en =1 is enabled; the AND gate AND output end is connected with an enabling end EN of the N-bit counter, the CLK end of the N-bit counter is connected with a counter clock Count _ CLK, the counter clock Count _ CLK is an M frequency division clock of the DDS kernel clock, M is determined according to actual needs, AND M =1, 2 or 4.
Specifically, the phase of the data clock dco is the same as the digital sinusoidal signals date1 and date2 output by the DDS core; the analog receive clock Sysclk/2 is at the same frequency and phase as the receive clock of the analog receive stage. The value of N of the N-bit counter is determined by the number of stages of the clock delay module, and the value of 2N is greater than the number of stages of the clock delay module. Since the delay adjustment is 15 stages in the first embodiment, the N-bit counter is a 4-bit counter, and is capable of outputting 15 stages of control signals.
Fig. 3 is a phase contrast diagram before and after the DDS circuit is affected by the irradiation SET effect, data1 and data2 are interleaved digital sinusoidal signals output by the DDS core, and the corresponding data sequences are d0, d2, d4 … and d1, d3, d5 …, and Sysclk/2 are analog receiving clocks, which have a fixed phase difference with the digital sinusoidal signals data1 and data2 and are determined according to actual needs, the analog receiving stage respectively collects data by using the upper and lower edges of the clocks, the sequence of the received signals during normal operation is d0, d1, d2, and d3 ….
In the first embodiment, the data clock dco is a data clock of 1GSPS, the analog receiving clock Sysclk/2 is a sampling signal of 1GHz, when the anti-irradiation DDS circuit normally works, the D flip-flops DFF1 and DFF2 collect data of the same level, and after xor, the data is 0, and the N-bit counter at the subsequent stage is not triggered to work; when the SET effect causes the collection error of the receiving stage, the analog receiving clock Sysclk/2 will collect the data with different levels through the D flip-flops DFF1 and DFF2, and after xor, it will be 1, and trigger the N-bit counter to start counting, the N-bit counter will output the continuously accumulated selection signal in 62.5MHz period, and from 0000 to 1111, it will be provided to the clock delay module, after the selection signal value output by the N-bit counter is adjusted to the next data period and the correct sequence is restored, it will re-lock the enabling of the N-bit counter, so as to complete the whole detection and correction.
It is particularly noted that in the dynamic correction circuit, the cycle counter clock Count _ clk of the N-bit counter should be less than or equal to the frequency of the DDS Core to ensure correct response of the feedback, in this example a division of 32 of the system clock Sysclk, i.e. a division of 16 of the analog receive clock Sysclk/2, which is the same as the digital Core clock Core _ clk.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (8)
1. An irradiation resistant DDS circuit comprising:
a DDS core generating interleaved digital sinusoidal signals date1 and date 2;
the digital data transmitting module is used for transmitting digital sinusoidal signals date1 and date2 to the analog receiving stage and the DAC module;
characterized in that, the anti-irradiation DDS circuit further comprises:
the dynamic correction circuit is characterized in that the digital data sending module generates a data clock dco and sends the data clock dco to the dynamic correction circuit, the output end of the dynamic correction circuit generates a selection signal and sends the selection signal to the clock delay module, and the dynamic correction circuit, the digital data sending module and the clock delay module form a negative feedback loop.
2. The radiation hard DDS circuit of claim 1 wherein the dynamic correction circuit comprises an inverter, a D flip-flop DEF1, a D flip-flop DEF2, an exclusive or gate XOR, an AND gate AND, AND an N-bit counter;
the C input end of the D flip-flop DEF1 and the inverter input end are both connected with an analog receiving clock Sysclk/2, the D input ends of the D flip-flop DEF1 and the D flip-flop DEF2 are both connected with a data clock dco, and the inverter output end is connected with the C input end of the D flip-flop DEF 2;
the Q output ends of the D flip-flop DEF1 AND the D flip-flop DEF2 are respectively connected with two input ends of the exclusive-OR gate XOR, the output end of the D flip-flop DEF1 AND the Q output end of the D flip-flop DEF2 are connected with one input end of the AND gate AND, AND the other input end of the AND gate AND is connected with a function enabling signal en;
AND the AND gate AND output end is connected with the enabling end EN of the N-bit counter, AND the CLK end of the N-bit counter is connected with the counter clock Count _ CLK.
3. The radiation hard DDS circuit of claim 1 wherein the data clock dco is in the same phase as the digital sinusoidal signals date1 and date2 output by the DDS core.
4. The radiation hard DDS circuit of claim 2 wherein the analog receive clock Sysclk/2 is at the same frequency and in the same phase as the receive clock of the analog receive stage.
5. The radiation hard DDS circuit of claim 2 wherein the function enable signal en is used to control a function enable of the dynamic correction circuit.
6. The radiation resistant DDS circuit of claim 2 wherein the counter clock Count clk is a M-division clock of the DDS core clock, where M is selected according to actual needs, and M =1, 2 or 4.
7. The radiation hard DDS circuit of claim 1 wherein the N value of the N-bit counter is determined by the number of stages of the clock delay module, the value 2N being greater than the number of stages of the clock delay module.
8. The radiation hard DDS circuit of claim 1 wherein the dynamic correction circuit outputs a 2N bit control code to the clock delay module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911152636.7A CN110838843B (en) | 2019-11-22 | 2019-11-22 | Anti-irradiation DDS circuit |
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| CN201911152636.7A CN110838843B (en) | 2019-11-22 | 2019-11-22 | Anti-irradiation DDS circuit |
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| CN110838843B CN110838843B (en) | 2022-08-02 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788390A (en) * | 2016-12-20 | 2017-05-31 | 中国电子科技集团公司第五十八研究所 | For DDS digital cores and the circuit interface system of digital analog converter |
| CN106936433A (en) * | 2017-03-09 | 2017-07-07 | 黄山学院 | Charge-domain phase error calibrates circuit and the DDS circuit using the calibration circuit |
| CN207720116U (en) * | 2018-02-09 | 2018-08-10 | 南华大学 | A kind of digital delay phase-locked loop of quick lock in |
| CN108614271A (en) * | 2018-07-06 | 2018-10-02 | 中国计量大学 | A kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation |
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- 2019-11-22 CN CN201911152636.7A patent/CN110838843B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106788390A (en) * | 2016-12-20 | 2017-05-31 | 中国电子科技集团公司第五十八研究所 | For DDS digital cores and the circuit interface system of digital analog converter |
| CN106936433A (en) * | 2017-03-09 | 2017-07-07 | 黄山学院 | Charge-domain phase error calibrates circuit and the DDS circuit using the calibration circuit |
| CN207720116U (en) * | 2018-02-09 | 2018-08-10 | 南华大学 | A kind of digital delay phase-locked loop of quick lock in |
| CN108614271A (en) * | 2018-07-06 | 2018-10-02 | 中国计量大学 | A kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation |
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