CN108614271A - A kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation - Google Patents
A kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation Download PDFInfo
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- CN108614271A CN108614271A CN201810741637.4A CN201810741637A CN108614271A CN 108614271 A CN108614271 A CN 108614271A CN 201810741637 A CN201810741637 A CN 201810741637A CN 108614271 A CN108614271 A CN 108614271A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S15/00—Systems using the reflection or reradiation of acoustic waves, e.g. sonar systems
- G01S15/88—Sonar systems specially adapted for specific applications
- G01S15/89—Sonar systems specially adapted for specific applications for mapping or imaging
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
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- Computer Networks & Wireless Communication (AREA)
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- Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)
Abstract
The invention discloses a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation, including the ends PC, jtag interface, FPGA, have source crystal oscillator, DAC module, filter module, feedback module and start key；The present invention generates the roads m phase signal parallel using DDS technologies；And feedback module and feedback signal processing module are added after filter circuit；Its feature is only to be detected multiple signals with the roads a m selector and ADC module, greatly reduces the consumption of resource so that structure is compacter；Feedback signal processing module can be detected the practical initial phase of multiple signals simultaneously；It only can obtain all channel initial phases with a zero detection module and combine the mode tabled look-up into the conversion of row amplitude and phase successively, considerably reduce the shared resource of feedback signal processing.
Description
Technical field
The present invention relates to a kind of multichannel DDS signal generator more particularly to a kind of channel ultrasonics with feedback compensation
Wave arbitrary waveform signal generator.
Background technology
Ultrasonic phased array technology forms focusing, the scanning of synthesis acoustic beam by the transmitting of control each array element of array energy transducer
Etc. various effects, to carry out ultrasonic imaging.Under phased array supersonic emission state, each array element is by centainly prolonging in array energy transducer
When rule sequence excite, the ultrasound emission beamlet of generation forms focus point and directive property in space combination.Change each array element to swash
The delay rule of hair, thus it is possible to vary focal position and beam position are formed in scanning focused within the scope of certain space.Ultrasonic phase
Key figure technology in control array 1 system is primarily referred to as the space-time control of wave beam, using advanced Digital Electronic Technique and micro- calculating
Machine technology accurately controls the phased wave beam of emission state, to obtain best launching beam characteristic.
Direct Digital Frequency Synthesizers (DDS) generate compared with traditional frequency synthesizer in frequency synthesis, random waveform
Aspect has many advantages, for example, frequency conversion is fast, output signal settling time is short, the purity of frequency spectrum is high, high frequency accuracy and
The advantages that resolution ratio and easily controllable various modulation systems.FPGA (Field-Programmable Gate Array, scene
Programmable gate array) as a kind of high performance programmable logic device excellent solution pair can be provided for a variety of circuits
It, will be more flexible easily-controllable with FPGA realizations for Digital Frequency Synthesize.It, can will be whole and since the integrated level of FPGA is especially high
A system is downloaded in same chip, realizes so-called system on chip (So C), so that the volume of miscellaneous goods significantly, improves system
Reliability.
Existing multichannel ultrasonic signal transmission technology, the basic structure in each channel is by phase accumulator (PD), wave
Shape memory (RAM), digital analog converter (DAC) and low-pass filter (LPF) composition, formed has certain phase difference independently of each other
Multi-channel signal generator.
Above-mentioned ultrasonic phased array lift-off technology has the following disadvantages：One, due to the delay inequality between wiring and chip
The different phase error caused between actual phase and desired phase is big.Two, the Multi-channel signal generator with feedback is in multi-path
When need multiple phase accumulators (PD), wave memorizer (RAM), digital analog converter (DAC) and filter circuit and modulus to turn
Parallel operation (ADC) causes circuit complicated, it is difficult to realize.
Invention content
In view of the above-mentioned deficiencies in the prior art, it is an object of the present invention to provide a kind of multichannel ultrasonic with feedback compensation times
Meaning waveform generator.
The purpose of the present invention is achieved through the following technical solutions：A kind of multichannel ultrasonic with feedback compensation times
Meaning waveform generator, including the ends PC, jtag interface, FPGA, DAC module, filter module, feedback module；
The phase and amplitude of ultrasonic wave waveform is mapped data storage to m waveform look-up by the ends PC by jtag interface
In table RAM, wherein m indicates port number, amplitude and phase mapping data is stored in two phase look-up table RAM, first phase
The phase information of look-up table storage first quartile and fourth quadrant, second phase look-up table the second quadrant of storage and third quadrant
The data type of phase information, phase signal and amplitude signal is binary system unsigned number, defines highest order and indicates sign bit,
Remaining position indicates data bit；
The FPGA receives mapping data in corresponding RAM, channel control signals, frequency control signal by jtag interface
With initial phase signal；In FPGA inner utilization DDS, m channel, m are formed according to channel control signals and frequency control signal
The signal in a channel is searched from corresponding waveform look-up table successively, obtains the amplitude signal corresponding to phase, then by width
Value signal, which is connected in DAC module, carries out digital-to-analogue conversion, is filtered later to output waveform using filter module, filtered
Each channel is connected in feedback module；
The feedback module is made of a multiple selector and an ADC module；Multiple selector and ADC module are successively
Each channel is sampled, and the signal after sampling is transported in the feedback signal processing module in FPGA；
The feedback signal processing module includes buffer, zero detection module, phase compensation unit, phase difference calculating list
Member, state detection unit and phase only pupil filter unit；
The zero detection module is made of the counter of a comparator and m systems, the counting of zero detection module
Device starts counting up, and the amplitude signal sampled is compared with the minimum amplitude signal in m channel, if it is detected that amplitude is big
Amplitude signal is then denoted as w in minimum amplitudei, the channel position i corresponding to it is obtained by counter, it successively will thereafter m-1
Amplitude signal is denoted as：wi+1 wi+2 …wm w1 w2…wi-1, corresponding to channel ordinal number be denoted as：i+1 i+2 … 1 2 …
i-1；Take a value for counting each channel after the period successively again：w′i w′i+1 w′i+2 … w′m w′1 w′2 … w′i-1；By institute
The data obtained are sent in state detection unit, the previous amplitude signal in each channel are subtracted each other with the latter amplitude signal, highest
Position is that the value of sign bit is indicated with A；If the amplitude of previous amplitude signal be more than the latter amplitude signal amplitude, A=0,
If the A=1 less than if；Simultaneously by the roads m amplitude signal wi wi+1 wi+2 … wm w1 w2 … wi-1It is sent into phase compensation unit, profit
Corresponding phase value is obtained from phase look-up table with look-up table, if A=1, is inquired from first phase look-up table corresponding
Phase；If A=0, corresponding phase value is inquired from second phase look-up table；And the phase in each channel is compensated；
Phase value after compensation is subtracted each other to obtain each by the phase difference calculating unit with preset initial phase signal
The value of phase difference between channels, highest order, that is, sign bit is indicated with B；If compensation after phase value be more than initial phase, B=0, if
Less than then B=1；Again initial phase is changed according to phase difference calculating unit；B=0 then indicates that phase is advanced, and B=then indicates phase
After steric retardation；The initial phase in channel is subtracted by the phase difference according to phase only pupil filter unit if advanced, if lag is according to phase
Initial phase is added the complement code of the phase difference by amending unit, is finally fed back to DDS and is modified.
Further, phase is generated at the ends PC turn the .mif files of amplitude and the .mif of amplitude phase inversion position using MATLAB
File generates RAM IP kernels by the IP kernel function in II softwares of Quartus, and the .mif file datas of generation is imported it
In；Control instruction and emission parameter are passed to by jtag interface in FPGA.
Further, by there is source crystal oscillator to generate clock signal fcLk, and it is connected respectively to FPGA, DAC module, feedback mould
In the multiple selector and ADC of block.
Further, the channel control signals include the channel position and port number m of user's selection, the FREQUENCY CONTROL
Signal is the frequency signal of transmitting ultrasonic wave waveform set by user, and the initial phase signal is transmitting set by user ultrasound
The initial phase signal of wave waveform.
Further, the FPGA receiving channels control signal and frequency control signal generation one are corresponding phase-accumulated
The initial phase signal that the data that phase accumulator exports are sent into corresponding m adder with reception is added up, is obtained by device
To the address information in each channel, believe according to the corresponding amplitude of phase in address information to its corresponding waveform look-up table, is searched
Number.
The beneficial effects of the invention are as follows：Compared with prior art, the present invention generates the roads m phase letter parallel using DDS technologies
Number.And feedback module and feedback signal processing module are added after filter circuit.Its feature be only with the roads a m selector with
ADC module is detected multiple signals, greatly reduces the consumption of resource so that structure is compacter.Feedback signal simultaneously
Processing module can be detected the practical initial phase of multiple signals.It can only be owned with a zero detection module successively
Channel initial phase simultaneously combines the mode tabled look-up into the conversion of row amplitude and phase, improves the precision of detection phase, greatly
Reduce the shared resource of feedback signal processing.
Description of the drawings
Fig. 1 is the integrally-built schematic diagram of the present invention；
Fig. 2 is the fundamental diagram inside FPGA；
Fig. 3 is the fundamental diagram of DDS；
Fig. 4 is the schematic block diagram of feedback module；
Fig. 5 is the schematic block diagram of feedback signal processing.
Specific implementation mode
The present invention is described in further detail below in conjunction with the drawings and specific embodiments.
The present invention can utilize MATLAB to hold the .mif files and width for generating phase and turning amplitude in PC (personal computer)
It is worth the .mif files of phase inversion position.Abundant IP kernel (IP core) in II softwares of Quartus provided by altera corp
Function generates RAM IP kernels and imports the .mif file datas of generation wherein.Control program and emission parameter are write, is passed through
Jtag interface is passed in the development board of altera corp FPGA (field programmable gate array) chip, its corresponding phase is made
It is stored in corresponding waveform look-up table (RAM) and phase look-up table (RAM), and is formed inside FPGA dedicated with amplitude information
Circuit.
Fig. 1 is overall structure of the present invention, the invention mainly comprises the ends PC, jtag interface, FPGA, have source crystal oscillator,
DAC module, filter module, feedback module and start key.Wherein the ends PC by jtag interface by the phase and width of ultrasonic wave waveform
In value mapping data storage to m waveform look-up table, wherein m indicates port number, and amplitude and phase mapping data are stored to two
In phase look-up table, the phase look-up table storage first quartile of first amplitude and phase mapping and the phase letter of fourth quadrant
The phase information of phase look-up table storage the second quadrant and third quadrant of breath, second amplitude and phase mapping.And in FPGA
Inside forms corresponding special circuit.There is the clock signal f that source crystal oscillator generatescLkIt is connected respectively to FPGA, DAC module and feedback
In module.
Fig. 2 gives the fundamental diagram inside FPGA.FPGA receives the mapping number in corresponding RAM by jtag interface
According to, channel control signals, frequency control signal and initial phase signal；The channel control signals include the channel of user's selection
Serial number and port number m, the frequency control signal are the frequency signal of transmitting ultrasonic wave waveform set by user, the initial phase
Position signal is the initial phase signal of transmitting ultrasonic wave waveform set by user；After the completion of data transmission, start key is pressed；
FPGA inner utilizations DDS (Direct Digital Frequency Synthesizers) forms m according to channel control signals and frequency control signal and leads to
Road, the signal in m channel from corresponding waveform look-up table i, obtain the amplitude signal corresponding to phase, then amplitude is believed successively
It number is connected in DAC (digital analog converter) module and to carry out digital-to-analogue conversion, output waveform is filtered later, it is filtered
Each channel is connected in feedback module, the feedback signal processing module being signally attached in FPGA that its feedback module is exported.
Fig. 3 gives the fundamental diagram of DDS.FPGA receiving channels control signal and frequency control signal generation one is right
The data that phase accumulator exports are sent into corresponding m adder the letter of the initial phase with reception by the phase accumulator answered
It number adds up, obtains the address information in each channel, according in address information to its corresponding waveform look-up table i, search phase
The corresponding amplitude signal in position.
Fig. 4 gives the schematic block diagram of feedback module in the present invention.It is by a multiple selector and an ADC module group
At.Multiple selector uses identical frequency f with ADC modulecLkClock signal.It successively samples each channel, and will
Signal after sampling is transported in the feedback signal processing module in FPGA.
Fig. 5 gives the schematic block diagram of feedback signal processing of the present invention.Zero detection module by a comparator and m into
The counter of system forms, and the numerical value of m is determined by channel control signals.Its operation principle is that counter starts counting up, and will be sampled
Amplitude signal be compared with the minimum amplitude signal in m channel.If it is detected that amplitude is more than the minimum value then by amplitude
Signal is denoted as wi, the channel position i corresponding to it is obtained by counter, data are deposited into memory successively, and will thereafter
M-1 amplitude signal is denoted as：wi+1 wi+2 … wm w1 w2 … wi-1, corresponding to channel ordinal number be denoted as：i+1 i+2 …
1 2 … i-1；Take a value for counting each channel after the period according to this again：w′i w′i+1 w′i+2 … w′m w′1 w′2 …
w′i-1.The data of gained are sent in state detection unit, by the previous amplitude signal in each channel and the latter amplitude signal into
Row subtracts each other, and the value of highest order, that is, sign bit is indicated with A.If the amplitude of previous amplitude signal is more than the latter amplitude signal
Amplitude, then A=0, if the A=1 less than if.
Simultaneously by the roads m amplitude signal wi wi+1 wi+2 … wm w1 w2 … wi-1It is sent into phase compensation unit, using looking into
Table method obtains corresponding phase value p from phase look-up tableiIf A=1, corresponding phase is inquired from first phase look-up table
Place value.If A=0, corresponding phase value is inquired from second phase look-up table.And the phase in each channel is compensated：I.e.
The phase of channel i is pi- 0, second channel phases is pi+1- 1, the phase in the last one channel is p successivelyi-1-(m-1)。
Phase value after compensation is subtracted each other to obtain each channel by phase difference calculating unit with preset initial phase signal
The value of phase difference, highest order, that is, sign bit indicates that the phase value after compensation is more than B=0 if initial phase, if being less than with B
Then B=1.Again initial phase is changed according to phase difference calculating unit.Such as B=0 then indicates that phase is advanced；B=1 then tables
Show delayed phase.The initial phase in channel subtracts the phase difference if advanced, if lag initial phase is plus the phase difference
Complement code is finally fed back to DDS and is modified.
In this description, it is noted that provide the signal generator of multichannel in the embodiment of the present invention, be only this
One specific example of invention, it is clear that technical scheme of the present invention is not limited to the signal generator described in example, in fact, this
The technical solution of invention can also make various modifications, transformation and deformation.Therefore, the description and the appended drawings should be considered as explanation
Property and not restrictive.It is every according to the technical essence of the invention to any simple modification made by above example and equivalent
Variation and modification, are considered as belonging to the scope of protection of the present invention.
Claims (5)
1. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation, which is characterized in that including the ends PC, JTAG
Interface, FPGA, DAC module, filter module, feedback module；
The phase and amplitude of ultrasonic wave waveform is mapped data storage to m waveform look-up table by the ends PC by jtag interface
In RAM, wherein m indicates port number, amplitude and phase mapping data is stored in two phase look-up table RAM, first phase is looked into
The phase information of table storage first quartile and fourth quadrant, second phase look-up table is looked for store the phase of the second quadrant and third quadrant
The data type of position information, phase signal and amplitude signal is binary system unsigned number, defines highest order and indicates sign bit, remaining
Position indicates data bit；
The FPGA receives mapping data in corresponding RAM, channel control signals, frequency control signal and just by jtag interface
Beginning phase signal；In FPGA inner utilization DDS, m channel is formed according to channel control signals and frequency control signal, m logical
The signal in road is searched from corresponding waveform look-up table successively, obtains the amplitude signal corresponding to phase, then amplitude is believed
It number is connected in DAC module and to carry out digital-to-analogue conversion, output waveform is filtered using filter module later, it is filtered each logical
Road is connected in feedback module；
The feedback module is made of a multiple selector and an ADC module；Multiple selector is with ADC module successively to each
Channel is sampled, and the signal after sampling is transported in the feedback signal processing module in FPGA；
The feedback signal processing module include buffer, zero detection module, phase compensation unit, phase difference calculating unit,
State detection unit and phase only pupil filter unit；
The zero detection module is made of the counter of a comparator and m systems, and the counter of zero detection module is opened
Begin to count, the amplitude signal sampled is compared with the minimum amplitude signal in m channel, if it is detected that amplitude is more than most
Amplitude signal is then denoted as w by small magnitudei, the channel position i corresponding to it is obtained by counter, it successively will m-1 amplitude thereafter
Signal is denoted as：wi+1 wi+2 … wm w1 w2 … wi-1, corresponding to channel ordinal number be denoted as：i+1 i+2 … 1 2 …
i-1；Take a value for counting each channel after the period successively again：w′i w′i+1 w′i+2 … w′m w′1 w′2 … w′i-1；By institute
The data obtained are sent in state detection unit, the previous amplitude signal in each channel are subtracted each other with the latter amplitude signal, highest
Position is that the value of sign bit is indicated with A；If the amplitude of previous amplitude signal be more than the latter amplitude signal amplitude, A=0,
If the A=1 less than if；Simultaneously by the roads m amplitude signal wi wi+1 wi+2 … wm w1 w2 … wi-1It is sent into phase compensation unit, profit
Corresponding phase value is obtained from phase look-up table with look-up table, if A=1, is inquired from first phase look-up table corresponding
Phase value；If A=0, corresponding phase value is inquired from second phase look-up table；And the phase in each channel is compensated；
Phase value after compensation is subtracted each other to obtain each channel by the phase difference calculating unit with preset initial phase signal
The value of phase difference, highest order, that is, sign bit is indicated with B；If the phase value after compensation is more than initial phase, B=0, if being less than
Then B=1；Again initial phase is changed according to phase difference calculating unit；B=0 then indicates that phase is advanced, and B=then indicates phase steric retardation
Afterwards；The initial phase in channel is subtracted by the phase difference according to phase only pupil filter unit if advanced, if lag is according to phase only pupil filter
Initial phase is added the complement code of the phase difference by unit, is finally fed back to DDS and is modified.
2. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is that generating phase at the ends PC using MATLAB turns the .mif files of amplitude and the .mif files of amplitude phase inversion position, passes through
IP kernel function in II softwares of Quartus generates RAM IP kernels, and the .mif file datas of generation are imported wherein；Control is referred to
It enables and emission parameter is passed to by jtag interface in FPGA.
3. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is, by there is source crystal oscillator to generate clock signal fcLk, and it is connected respectively to FPGA, DAC module, the choosing of the multichannel of feedback module
It selects on device and ADC.
4. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is that the channel control signals include the channel position and port number m of user's selection, and the frequency control signal is user
The frequency signal of the transmitting ultrasonic wave waveform of setting, the initial phase signal are the first of transmitting ultrasonic wave waveform set by user
Beginning phase signal.
5. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is that the FPGA receiving channels control signal and frequency control signal generate a corresponding phase accumulator, by phase
The initial phase signal that the data of accumulator output are sent into corresponding m adder with reception adds up, and obtains each logical
The address information in road searches the corresponding amplitude signal of phase according in address information to its corresponding waveform look-up table.
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| CN109814656A (en) * | 2018-12-28 | 2019-05-28 | 中电科仪器仪表有限公司 | A kind of signal generating apparatus and method for arbitrary waveform generator |
| CN110045017A (en) * | 2019-04-26 | 2019-07-23 | 中国计量大学 | The underwater ultrasound phased array fault detection system of wireless data transmission and method of detection |
| CN110234119A (en) * | 2019-06-06 | 2019-09-13 | 四川九洲电器集团有限责任公司 | Signal source based on DAC chip generates system |
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| CN110380216A (en) * | 2019-07-30 | 2019-10-25 | 西安天和防务技术股份有限公司 | Phase configuration method, apparatus, equipment and storage medium in phased-array radar |
| CN110333490A (en) * | 2019-07-30 | 2019-10-15 | 西安电子工程研究所 | Asynchronous multiple channel random waveform production method based on the flow work mode |
| CN110333490B (en) * | 2019-07-30 | 2022-12-27 | 西安电子工程研究所 | Asynchronous multichannel arbitrary waveform generation method based on pipeline working mode |
| CN110838843A (en) * | 2019-11-22 | 2020-02-25 | 中国电子科技集团公司第五十八研究所 | Anti-irradiation DDS circuit |
| CN110838843B (en) * | 2019-11-22 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | Anti-irradiation DDS circuit |
| CN111707975A (en) * | 2020-06-24 | 2020-09-25 | 中国电子科技集团公司第四十一研究所 | Radio frequency signal generation system and method suitable for helium optical pump magnetometer |
| CN113720222A (en) * | 2021-08-30 | 2021-11-30 | 山西宇翔信息技术有限公司 | Radio fuze and phase correction method, platform and readable storage medium thereof |
| CN114129920A (en) * | 2021-11-29 | 2022-03-04 | 中国医学科学院生物医学工程研究所 | Phased array ultrasonic transducer excitation system for improving accurate frequency |
| CN114129920B (en) * | 2021-11-29 | 2023-09-26 | 中国医学科学院生物医学工程研究所 | Phased array ultrasonic transducer excitation system for improving accurate frequency |
| CN115033053A (en) * | 2022-03-03 | 2022-09-09 | 阿里巴巴达摩院(杭州)科技有限公司 | Signal processing method and storage medium |
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