CN110234119A - Signal source based on DAC chip generates system - Google Patents
Signal source based on DAC chip generates system Download PDFInfo
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- CN110234119A CN110234119A CN201910490059.6A CN201910490059A CN110234119A CN 110234119 A CN110234119 A CN 110234119A CN 201910490059 A CN201910490059 A CN 201910490059A CN 110234119 A CN110234119 A CN 110234119A
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- dac
- dac chip
- filter
- signal
- chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/0003—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain
- H04B1/0028—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage
- H04B1/0039—Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain wherein the AD/DA conversion occurs at baseband stage using DSP [Digital Signal Processor] quadrature modulation and demodulation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
- H04W16/14—Spectrum sharing arrangements between different networks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
- H04W16/18—Network planning tools
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W16/00—Network planning, e.g. coverage or traffic planning tools; Network deployment, e.g. resource partitioning or cells structures
- H04W16/24—Cell structures
- H04W16/26—Cell enhancers or enhancement, e.g. for tunnels, building shadow
Abstract
The present invention relates to the signal sources the present invention relates to jammer technical field, disclosed based on DAC chip to generate system.It include: FPGA module, DAC chip and channel circuit, the FPGA module respectively with the first DAC chip, second DAC chip, the connection of third DAC chip, the channel circuit includes first filter, second filter, third filter, combiner and 2 output ends, first DAC chip, second DAC chip, third DAC chip is separately connected the first DAC filter, 2nd DAC filter, third filter, the first filter, second filter is all connected with combiner, the combiner and third filter pass through 2 output ends respectively and export 2 tunnel radiofrequency signals.Above scheme eliminates up-converter module compared with traditional DDS+up-conversion scheme, is of great significance to system low cost, light-weight design, as the signal source part of system, can be widely applied to the communications field.
Description
Technical field
The present invention relates to jammer technical field, the signal source for being based particularly on DAC chip generates system.
Background technique
With the high speed development of the present communication technology, miniaturization, the integrated, cost control of equipment are required increasingly
Height, how to design low cost, high integration, miniaturization equipment be urgent problem at this stage.
Existing signal source design realizes that up-conversion uses baseband signal and high frequency using base band+up-conversion conceptual design
Phenomena such as realizing after signal mixing, frequency aliasing, intermodulation are necessarily had in optical mixing process appearance, brings very disaster to design
Degree, and technical indicator is not fine；Up-converter module is larger in cost, the weight accounting of equipment complete machine simultaneously, causes certain
Cost wastes and performance is general.Base band+up-conversion conceptual design is used for the generation of high-frequency, high-bandwidth signals, is realized
Mainly include following disadvantage in the scheme of derived digital signal:
1. signal is spuious serious.Phenomena such as frequency aliasing, intermodulation are necessarily had in optical mixing process appearance, brings to design
Great difficulty, and technical indicator is not fine.
2. volume is big, power consumption is high.Up-converter module is larger in cost, the weight accounting of equipment complete machine, cause it is certain at
This waste and performance is general.
3. number of channels is more.Since wireless telecom equipment system is numerous, from VHF to 6GHz, frequency of use is numerous.By tradition
The limited influence of derived digital signal bandwidth needs that entire interference band could be covered using multiple channels.
4. frequency range is fixed, it is not easy to extend, flexibility is poor.It often interferes with machine channel and divides more (more than usual 10 channel),
Frequency range is relatively fixed, and since communications band whole world difference is big, and traditional jammer is to meet Global coverage, generally requires with pre-
The mode Redundancy Design for staying hardware corridor, further increases equipment volume, weight, but is limited to volume, consumption reasons, frequency range sometimes
It is larger to extend difficulty.It is poor that this allows for entire interference signal waveform, interference band dynamic restructuring.
Summary of the invention
The technical problems to be solved by the present invention are: in view of the above problems, providing the signal based on DAC chip
Source generates system.
The technical solution adopted by the invention is as follows: the signal source based on DAC chip generates system, comprising: FPGA module,
DAC chip and channel circuit, the FPGA module are connect with the first DAC chip, the second DAC chip, third DAC chip respectively,
The channel circuit includes first filter, second filter, third filter, combiner and 2 output ends, and described first
DAC chip, the second DAC chip, third DAC chip are separately connected the first DAC filter, the 2nd DAC filter, third filtering
Device, the first filter, second filter are all connected with combiner, the combiner and third filter pass through respectively 2 it is defeated
Outlet exports 2 tunnel radiofrequency signals.
Further, first DAC chip, the second DAC chip, third DAC chip select 14 RF digital analog converters,
Kernel has four-way construction of switch.
Further, first DAC chip, the second DAC chip, third DAC chip work baseband mode export 0~
The signal of 1.425GHz works in the signal of mixed mode output 1.425GHz~4.2GHz.
Further, the channel circuit further includes 2 power splitters, and power splitter is respectively set in 2 output ends, will be each
Output end separates 4 groups of radiofrequency signals.
Further, the channel circuit further includes gain control circuit, and combiner and third filter output signal are logical
It crosses after gain control circuit again by 2 output end outputs.
Further, the gain control circuit includes MCU controller and 2 groups of concatenated attenuators and amplifier, combining
Device and third filter are separately connected 1 attenuator, and 2 amplifiers are connected with power splitter respectively, the MCU controller and FPGA
It is connected, and controls attenuator.
Further, the FPGA module is synthesized using 8 tunnels, and 8 road DDS export same frequency but phase phase difference 1/8 simultaneously
The data of phase accumulation value, 8 tunnel output signals input to DAC chip parallel-serial conversion, generate single-carrier signal after synthesis.
Further, multiple single-carrier signals are added to obtain multi-carrier signal in time domain.
Further, the signal source based on DAC chip generates system further include: single chip machine controlling circuit, monolithic
Machine control circuit is connect with FPGA module.
Further, the signal source based on DAC chip generates system further include: power circuit, potential circuit are adopted
It is powered with+12V, is allocated by the DC-DC module of power circuit.
Compared with prior art, having the beneficial effect that by adopting the above technical scheme
(1) broadband channel is designed, frequency range flexible combination.The present invention using three have a lot of social connections tape channel design.It can be according to user's
Actual demand, interference band needed for flexible setting, to adapt to unused application demand.Since product is small and exquisite, in terms of scalability,
Frequency range dilatation can be realized by way of simply increasing hardware mould group, realize the covering of multiband.Therefore, product can flexible root
According to practical application request, interfering channel needed for configuring avoids Redundancy Design.
(2) jammer volume, weight are reduced.By the scheme for the interference signal that radio frequency high speed D/A directly goes out, frequency conversion is eliminated
Module, product integrated level is higher, and structure is more compact, more miniaturization, lightweight.
(3) interference source signal quality is improved.Interference source uses the mentality of designing of advanced software radio framework, passes through height
Speed digital chip can effectively inhibit the spuious of output signal, reduce the requirement to signal output end filter.
Detailed description of the invention
Fig. 1 is that the present invention is based on the signal sources of DAC chip to generate system the general frame.
Fig. 2 is the structural schematic diagram of analog channel circuit of the present invention.
Fig. 3 is multipath DDS (Direct Digital Synthesis) signals composition principle in single carrier generating process of the present invention.
Fig. 4 is to make fft analysis frequency domain schematic diagram using Matlab tool in multicarrier generation method of the present invention.
Specific embodiment
The present invention is described further with reference to the accompanying drawing.
Embodiment 1: the signal source based on DAC chip generates system, comprising: FPGA module, DAC chip and channel electricity
Road, the FPGA module are connect with the first DAC chip, the second DAC chip, third DAC chip respectively, first DAC chip,
The different working frequency range that second DAC chip, third DAC chip are respectively allocated according to the actual situation.
According to DAC characteristic, which has two kinds of operating modes, 0 can be exported when work is in baseband mode~
In addition the signal of 1.425GHz, the signal of exportable 1.425GHz~4.2GHz when work is in mixed mode are raising signal
Quality avoids multi-carrier signal from generating excessive intermodulation signal in amplification, we divide output signal frequency range, this reality
Apply example frequency range output table such as the following table 1 according to the actual situation.
1 frequency range of table exports table
Pass through the first DAC filter, the 2nd DAC filter, the 3rd DAC filter by the radiofrequency signal obtained after DAC chip
Wave device filters out mirror image etc. with outer garbage signal, the first DAC filter, the 2nd DAC filter signal synthesis all the way, combining
Signal and another filtering signal later passes through 2 output ends respectively and exports 2 tunnel radiofrequency signals.
On the basis of embodiment 1: the group number in order to increase every road radiofrequency signal exports 4 group of 2 road multicarrier radio frequency letter
Number, 2 power splitters are set, power splitter is respectively set in 2 output ends, each output end is separated into 4 groups of radiofrequency signals.
As shown in Figure 1, being the Suresh Kumar signal source the general frame of DAC chip.Its hardware is related to including following sections.
(a) signal generating circuit
Signal generating circuit is realized by FPGA+DAC chip, realizes that the algorithm of arbitrary signal waveform is realized；Equipment DAC chip
14 RF digital analog converters (DAC) of high-performance are selected, support the data rate for being up to 2.85GSPS.DAC kernel is based on one
Four-way construction of switch enables double edge clocks effectively to run, when being configured to mixed-mode (Mix-Mode) or 2 times of interpolation,
DAC renewal rate can be improved to 5.7GSPS.Its high dynamic range and wide bandwidth characteristic may produce up to the overloading of 4.2GHz
Wave.Under baseband mode, 1 to 158 continuous carrier can be supported.Be also an option that two optional 2 times of interpolation filters, pass through by
DAC renewal rate improves twice to rebuild filter after simplifying.
DAC chip specific performance is as follows:
1) DAC renewal rate: up to 5.7GSPS；
2) directly RF frequency synthesis (2.85GSPS data rate)；
3) direct current is to 1.425GHz (baseband mode)；
4) direct current is to 1.0GHz (2 times of interpolative modes)；
5) 1.425GHz to 4.2GHz (mixed mode).
(b) analog channel circuit
After AD has obtained radiofrequency signal, it is also necessary to carry out a series of conditionings to signal, be primarily due to the spuious of DDS principle
Effect, in channel circuit, it is necessary to signal is filtered, band stray and image frequency signal are filtered out；To output signal
After filtering, in order to guarantee that signal transmits at a distance, to back end link indispensability driving capability, gain control circuit joined, close
Road device and 2 tunnel output signal of third filter by passing through 2 output end outputs again after gain control circuit.It is set according to this system
Meter requires, and also needs to carry out signal function point processing, is output to corresponding power amplification unit.
As shown in Fig. 2, being the block diagram of an analog channel circuit.First DAC chip, the second DAC chip, the 3rd DAC core
The output signal of DA1, DA2, DA3 of piece pass through attenuation equalization respectively, and the signal after the corresponding attenuation equalization of DA1, DA2 enters conjunction
Road device, then power splitter successively is reached by attenuation equalization, amplifier amplification, stepping decaying, amplifier amplification, form 4 groups of 1 tunnel letter
Number, the corresponding signal of DA3 after attenuation equalization twice, successively pass through amplifier amplification, stepping decaying, amplifier amplify,
Attenuation equalization reaches power splitter, re-forms 4 groups of 1 tunnel signal.SPI-FPGA controller stepping attenuation process.
(c) control circuit
Single chip machine controlling circuit: using ARM chip as master controller, design has Gigabit Ethernet (with upgrading, management system
Connection), serial ports, CAN interface etc., all related circuits in control periphery, including host computer protocol analysis, amplifying unit control
System, the setting of FPGA output signal pattern, equipment state reading report.
(d) power circuit
Use+12V power supply outside the signal source meets equipment work after being allocated by power circuit DC-DC module
Demand.
Suresh Kumar signal in the present invention generates design: the signal of different patterns can add carrier modulation to obtain by baseband signal
It arrives, but since the carrier frequency of interference signal is higher, is limited, cannot directly be generated by FPGA data processing clock speed, located
DDS signal multichannel synthetic method is used in reason.
A) single-carrier signal generates
Be illustrated by taking the first DAC chip DAC1 output single carrier as an example, DAC1 chip operation under baseband mode, in order to
Meet demand, digital renewal rate are at least 2.2Gbps.It is limited by FPGA module data processing Clock management speed, no
It can directly generate, therefore system, by the way of multichannel synthesis, the work of FPGA master clock is in 275M, to cooperate DAC chip
2.2Gbps conversion rate, the inside FPGA is synthesized using 8 tunnels, as shown in figure 3, frequency control word P inputs to phase accumulator, phase
Bit accumulator exports 8 road signals, and 8 DDS export the number of 1/8 phase accumulation value of same frequency (275M) but phase phase difference simultaneously
According to 14, the two channel Selectio eight tunnel parallel-serial conversions of progress that 8 circuit-switched datas are finally sequentially sent to DAC1 are fast at 2.2Gbps
Rate, thus the broadband signal of directly 0~1.1G of frequency synthesis.
DDS phase-accumulated bit wide is 48, and systematic sampling rate 275M, output frequency 800M are calculated according to formula (1)
The frequency control word P of DDS, and the phase difference of adjacent two-way DDS is
B) multi-carrier signal generates
The generation of multi-carrier signal is that multiple single-carrier signals are added to obtain in time domain.With 1600M, 1820M and 2300M
For three multi-carrier signals generate.Fig. 4 show the fft analysis frequency domain that three signals are made by Matlab tool.
The invention is not limited to specific embodiments above-mentioned.The present invention, which expands to, any in the present specification to be disclosed
New feature or any new combination, and disclose any new method or process the step of or any new combination.If this
Field technical staff is altered or modified not departing from the unsubstantiality that spirit of the invention is done, should belong to power of the present invention
The claimed range of benefit.
Claims (10)
1. the signal source based on DAC chip generates system characterized by comprising FPGA module, DAC chip and channel electricity
Road, the FPGA module are connect with the first DAC chip, the second DAC chip, third DAC chip respectively, and the channel circuit includes
First filter, second filter, third filter, combiner and 2 output ends, first DAC chip, the 2nd DAC core
Piece, third DAC chip are separately connected the first DAC filter, the 2nd DAC filter, third filter, the first filter,
Second filter is all connected with combiner, and the combiner and third filter pass through 2 output ends respectively and export 2 road radio frequencies letter
Number.
2. the signal source based on DAC chip generates system as described in claim 1, which is characterized in that the first DAC core
It is RF digital analog converter that piece, the second DAC chip, third DAC chip, which select 14, and kernel has four-way construction of switch.
3. the signal source based on DAC chip generates system as described in claim 1, which is characterized in that the first DAC core
Piece, the second DAC chip, the work of third DAC chip work in the signal of 0~1.425GHz of baseband mode output in mixed mode
Export the signal of 1.425GHz~4.2GHz.
4. the signal source based on DAC chip generates system as described in claim 1, which is characterized in that the channel circuit
Further include 2 power splitters, power splitter is respectively set in 2 output ends, each output end is separated into 4 groups of radiofrequency signals.
5. the signal source based on DAC chip generates system as claimed in claim 4, which is characterized in that the channel circuit
It further include gain control circuit, the combiner and third filter output signal by passing through 2 again after gain control circuit
Output end output.
6. the signal source based on DAC chip generates system as claimed in claim 5, which is characterized in that the gain control
Circuit includes MCU controller and 2 groups of concatenated attenuators and amplifier, and combiner and third filter are separately connected 1 decaying
Device, 2 amplifiers are connected with power splitter respectively, and the MCU controller is connected with FPGA, and controls attenuator.
7. the signal source based on DAC chip as described in claim 1 or 6 generates system, which is characterized in that the FPGA
Module is synthesized using 8 tunnels, and 8 road DDS export the data of 1/8 phase accumulation value of same frequency but phase phase difference, 8 tunnels output letter simultaneously
Number DAC chip parallel-serial conversion is inputed to, generates single-carrier signal after synthesis.
8. the signal source based on DAC chip generates system as claimed in claim 7, which is characterized in that multiple single carrier letters
It number is added to obtain multi-carrier signal in time domain.
9. the signal source based on DAC chip generates system as described in claim 1, which is characterized in that further include: single-chip microcontroller
Control circuit, single chip machine controlling circuit are connect with FPGA module.
10. the signal source based on DAC chip generates system as described in claim 1, which is characterized in that further include: power supply
Circuit, potential circuit use+12V power supply, is allocated by the DC-DC module of power circuit.
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| CN201910490059.6A CN110234119B (en) | 2019-06-06 | 2019-06-06 | Signal source generating system based on DAC chip |
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| CN201910490059.6A CN110234119B (en) | 2019-06-06 | 2019-06-06 | Signal source generating system based on DAC chip |
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