CN208752198U - A Multi-Channel Ultrasonic Arbitrary Waveform Signal Generator with Feedback Correction - Google Patents
A Multi-Channel Ultrasonic Arbitrary Waveform Signal Generator with Feedback Correction Download PDFInfo
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Abstract
本实用新型公开了一种带反馈校正的多通道超声波任意波形信号发生器，包括PC端、JTAG接口、FPGA、有源晶振、DAC模块、滤波模块、反馈模块和启动键；本实用新型采用DDS技术并行产生m路相位信号；并在滤波电路后加上反馈模块和反馈信号处理模块；其特点在于只用一个m路选择器和ADC模块对多路信号进行检测，大大降低了资源的消耗，使得结构更加紧凑；同时反馈信号处理模块能对多路信号实际初始相位进行检测，其仅用一个零点检测模块能依次得到所有通道初始相位，极大地减少了反馈信号处理所占的资源。
The utility model discloses a multi-channel ultrasonic arbitrary waveform signal generator with feedback correction, comprising a PC terminal, a JTAG interface, an FPGA, an active crystal oscillator, a DAC module, a filter module, a feedback module and a start key; the utility model adopts a DDS The technology generates m-channel phase signals in parallel; and a feedback module and a feedback signal processing module are added after the filter circuit; its characteristic is that only one m-channel selector and ADC module are used to detect multi-channel signals, which greatly reduces the consumption of resources. The structure is more compact; at the same time, the feedback signal processing module can detect the actual initial phase of the multi-channel signal, and only one zero point detection module can obtain the initial phase of all channels in turn, which greatly reduces the resources occupied by the feedback signal processing.
Description
Technical field
The utility model relates to a kind of multichannel DDS signal generator more particularly to a kind of multichannels with feedback compensation
Ultrasonic wave arbitrary waveform signal generator.
Background technique
Ultrasonic phased array technology forms focusing, the scanning of synthesis acoustic beam by the transmitting of control each array element of array energy transducer
Etc. various effects, to carry out ultrasonic imaging.Under phased array supersonic emission state, each array element is by centainly prolonging in array energy transducer
When rule sequence excite, the ultrasound emission beamlet of generation forms focus point and directive property in space combination.Change each array element to swash
The delay rule of hair, thus it is possible to vary focal position and beam position are formed in scanning focused within the scope of certain space.Ultrasonic phase
Key figure technology in control array 1 system is primarily referred to as the space-time control of wave beam, using advanced Digital Electronic Technique and micro- calculating
Machine technology accurately controls the phased wave beam of emission state, to obtain optimal launching beam characteristic.
Direct Digital Frequency Synthesizers (DDS) generate compared with traditional frequency synthesizer in frequency synthesis, random waveform
Aspect has many advantages, for example, frequency conversion is fast, output signal settling time is short, the purity of frequency spectrum is high, high frequency accuracy and
The advantages that resolution ratio and easily controllable various modulation systems.Field programmable gate array (Field-Programmable Gate
Array is referred to as FPGA) excellent solution party can be provided for a variety of circuits as a kind of high performance programmable logic device
Case, will be more flexible easily-controllable with FPGA realization for Digital Frequency Synthesize.It, can and since the integrated level of FPGA is especially high
Whole system is downloaded in same chip, realizes so-called system on chip (So C), so that the volume of miscellaneous goods significantly, is improved
The reliability of system.
Existing multichannel ultrasonic signal transmission technology, the basic structure in each channel is by phase accumulator (PD), wave
Shape memory (RAM), digital analog converter (DAC) and low-pass filter (LPF) composition, formed has certain phase difference independently of each other
Multi-channel signal generator.
Above-mentioned ultrasonic phased array lift-off technology has the disadvantage that one, due to the delay inequality between wiring and chip
The different phase error caused between actual phase and desired phase is big.Two, the Multi-channel signal generator with feedback is in multi-path
When need multiple phase accumulators (PD), wave memorizer (RAM), digital analog converter (DAC) and filter circuit and modulus to turn
Parallel operation (ADC) causes circuit complicated, it is difficult to realize.
Summary of the invention
The purpose of this utility model is that in view of the deficiencies of the prior art, providing a kind of channel ultrasonic with feedback compensation
Wave arbitrary waveform signal generator.
The purpose of this utility model is achieved through the following technical solutions: a kind of channel ultrasonic with feedback compensation
Wave arbitrary waveform signal generator, including the end PC, jtag interface, FPGA, DAC module, filter module, feedback module；
The end PC is connect with jtag interface, and the phase and amplitude of ultrasonic wave waveform is mapped data by jtag interface and is deposited
It stores up in m waveform look-up table RAM, the amplitude of ultrasonic wave waveform and phase mapping data is stored to two phase look-up tables
In RAM；
There is DDS and feedback signal processing module, FPGA is received in corresponding RAM by jtag interface inside the FPGA
Map data, channel control signals, frequency control signal and initial phase signal；The output end of the DDS of FPGA connects m DAC
Module, DDS form m channel according to channel control signals and frequency control signal, and the signal in m channel is successively from corresponding wave
In shape look-up table RAM, amplitude signal corresponding to phase is obtained, then send amplitude signal in DAC module and carry out digital-to-analogue turn
It changes；The output end of each DAC module connects a filter module, and the output of all filter modules connects feedback module；
The feedback module is made of a multiple selector and an ADC module；The output end of m filter module connects
The multiple selector is connect, the output end of multiple selector connects ADC module, the feedback of the output end connection FPGA of ADC module
Signal processing module；
The feedback signal processing module includes sequentially connected zero point detection module, state detection unit, phase compensation
Unit, phase difference calculating unit and phase only pupil filter unit；
The zero point detection module is made of comparator, the counter of m systems and memory, and the counter starts to count
When number, the amplitude signal sampled is compared by the comparator with the minimum amplitude signal in m channel, detects amplitude
Waveform signal is stored in memory when greater than minimum amplitude；
The state detection unit is to each previous amplitude signal in channel road and the latter amplitude taken out from memory
Signal is compared, by comparison result input phase compensating unit；
The testing result of phase compensation unit state detection unit based on the received, is obtained by phase look-up table RAM
It is compensated to the phase in each channel, and to each channel phases；
The phase difference calculating unit by the compensated phase value of phase compensation unit and preset initial phase signal into
Row subtracts each other to obtain each phase difference between channels, is input to phase only pupil filter unit modification initial phase signal, and feed back to DDS and repaired
Just.
It further, further include having source crystal oscillator, by there is source crystal oscillator to generate clock signal fcLk, and be connected respectively to FPGA,
In DAC module, the multiple selector and ADC module of feedback module.
Further, the FPGA receiving channel control signal and frequency control signal generation one are corresponding phase-accumulated
The data of phase accumulator output are sent into corresponding m adder and add up with received initial phase signal, obtain by device
To the address information in each channel, according to address information into its corresponding waveform look-up table RAM, the corresponding amplitude of phase is searched
Signal.
It further, further include start key, the FPGA receives data by jtag interface, after data are transmitted, presses
Lower start key, starting DDS work.
Further, phase is generated at the end PC using MATLAB turn the .mif file of amplitude and the .mif of amplitude phase inversion position
File；Data are passed in the development board of altera corp's fpga chip by jtag interface.
The beneficial effects of the utility model are: compared with prior art, the utility model generates m using DDS technology parallel
Road phase signal.And feedback module and feedback signal processing module are added after filter circuit.It is characterized in that only with a road m
Selector and ADC module detect multiple signals, greatly reduce the consumption of resource, so that structure is more compact.Simultaneously
Feedback signal processing module can detect the practical initial phase of multiple signals.Its only use a zero point detection module can according to
To all channel initial phases and the mode tabled look-up is combined to carry out the conversion of amplitude and phase, improves the precision of detection phase,
Considerably reduce the shared resource of feedback signal processing.
Detailed description of the invention
Fig. 1 is the integrally-built schematic diagram of the utility model；
Fig. 2 is the working principle diagram inside FPGA；
Fig. 3 is the working principle diagram of DDS；
Fig. 4 is the schematic block diagram of feedback module；
Fig. 5 is the schematic block diagram of feedback signal processing.
Specific embodiment
The utility model is described in further detail below in conjunction with the drawings and specific embodiments.
The utility model can use MATLAB PC (personal computer) hold generate phase turn the .mif file of amplitude with
And the .mif file of amplitude phase inversion position.IP kernel (intellectual property abundant in II software of Quartus provided by altera corp
Core) function, it generates RAM IP kernel and imports the .mif file data of generation wherein.Control program and emission parameter are write, is led to
It crosses jtag interface to be passed in the development board of altera corp FPGA (field programmable gate array) chip, makes its corresponding phase
Position and amplitude information are stored in corresponding waveform look-up table (RAM) and phase look-up table (RAM), and are formed inside FPGA dedicated
Circuit.
Fig. 1 is the utility model overall structure diagram, and the utility model mainly includes the end PC, jtag interface, FPGA, has
Source crystal oscillator, DAC module, filter module, feedback module and start key.Wherein the end PC passes through jtag interface for the phase of ultrasonic wave waveform
Into m waveform look-up table, wherein m indicates port number, and amplitude and phase mapping data are deposited for position and amplitude mapping data storage
Into two phase look-up tables, the phase of phase look-up table the storage first quartile and fourth quadrant of first amplitude and phase mapping
The phase information of phase look-up table storage the second quadrant and third quadrant of position information, second amplitude and phase mapping.And
Corresponding special circuit is formed inside FPGA.The clock signal f for thering is source crystal oscillator to generatecLkBe connected respectively to FPGA, DAC module and
On feedback module.
Fig. 2 gives the working principle diagram inside FPGA.FPGA receives the mapping number in corresponding RAM by jtag interface
According to, channel control signals, frequency control signal and initial phase signal；The channel control signals include the channel of user's selection
Serial number and port number m, the frequency control signal are the frequency signal of transmitting ultrasonic wave waveform set by user, the initial phase
Position signal is the initial phase signal of transmitting ultrasonic wave waveform set by user；After data are transmitted, start key is pressed；?
FPGA inner utilization DDS (Direct Digital Frequency Synthesizers) forms m according to channel control signals and frequency control signal and leads to
Road, the signal in m channel successively from corresponding waveform look-up table i, obtain amplitude signal corresponding to phase, then amplitude is believed
It number is connected in DAC (digital analog converter) module and to carry out digital-to-analogue conversion, output waveform is filtered later, it is filtered
Each channel is connected in feedback module, the feedback signal processing module being signally attached in FPGA that its feedback module is exported.
Fig. 3 gives the working principle diagram of DDS.FPGA receiving channel controls signal and frequency control signal generation one is right
The data of phase accumulator output are sent into corresponding m adder and are believed with received initial phase by the phase accumulator answered
It number adds up, obtains the address information in each channel, according to address information into its corresponding waveform look-up table i, search phase
The corresponding amplitude signal in position.
Fig. 4 gives the schematic block diagram of feedback module in the utility model.It is by a multiple selector and an ADC mould
Block composition.Multiple selector and ADC module use identical frequency fcLkClock signal.It successively samples each channel,
And the signal after sampling is transported in the feedback signal processing module in FPGA.
Fig. 5 gives the schematic block diagram of the utility model feedback signal processing.Zero point detection module is by a comparator and m
The counter composition of position system, the numerical value of m are determined by channel control signals.Its working principle is that counter starts counting, will adopt
Sample to amplitude signal be compared with the minimum amplitude signal in m channel.Then will if it is detected that amplitude is greater than the minimum value
Amplitude signal is denoted as wi, the channel position i corresponding to it is obtained as counter, is successively deposited into memory.To m-1 thereafter
A amplitude signal is denoted as: wi+1 wi+2 … wm w1 w2 … wi-1；Take value for counting each channel after the period: w ' according to this againi
′i+1 w′i+2 … w′m w′1 w′2 … w′i-1.Resulting data are sent in state detection unit, each channel is previous
Amplitude signal is subtracted each other with the latter amplitude signal, and the value of highest order (sign bit) is indicated with A.If previous amplitude signal
Amplitude be greater than the amplitude of the latter amplitude signal, then A=0, the A=1 if being less than.
Simultaneously by the road m amplitude signal wi wi+1 wi+2 … wm w1 w2 … wi-1It is sent into phase compensation unit, using looking into
Table method obtains corresponding phase value p from phase look-up tableiIf A=1, corresponding phase is inquired from first phase look-up table
Place value.If A=0, corresponding phase value is inquired from second phase look-up table.And the phase in each channel is compensated: i.e.
The phase of channel i is pi- 0, second channel phases is pi+1- 1, successively the phase in the last one channel is pi_1-(m-1)。
Compensated phase value and preset initial phase signal are subtracted each other to obtain respectively using phase difference calculating unit
The value of phase difference between channels, highest order (sign bit) is indicated with B.The B=if compensated phase value is greater than initial phase signal
0, the B=1 if being less than.Initial phase is modified according to phase difference calculating unit again.B=0 then indicates that phase is advanced；B=1 then table
Show delayed phase.The initial phase in channel subtracts the phase difference if advanced, if lag initial phase is plus the phase difference
Complement code is finally fed back to DDS and is modified.
In this description, it is noted that the signal generator of multichannel is provided in the utility model embodiment, only
It is a specific example of the utility model, it is clear that the technical solution of the utility model is not limited to the generation of signal described in example
Device, in fact, the technical solution of the utility model can also make various modifications, transformation and deformation.Therefore, specification and attached
Figure is regarded in an illustrative, rather than a restrictive.It is all that above embodiments are made according to the technical essence of the utility model
It is any it is simple modification and equivalent variations with modify, be considered as belonging to the protection scope of the utility model.
Claims (5)
1. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation, which is characterized in that including the end PC, JTAG
Interface, FPGA, DAC module, filter module, feedback module；
The end PC is connect with jtag interface, and the phase and amplitude of ultrasonic wave waveform is mapped data storage by jtag interface and is arrived
In m waveform look-up table RAM, by the amplitude of ultrasonic wave waveform and the storage of phase mapping data into two phase look-up table RAM；
There is DDS and feedback signal processing module, FPGA receives the mapping in corresponding RAM by jtag interface inside the FPGA
Data, channel control signals, frequency control signal and initial phase signal；The output end of the DDS of FPGA connects m DAC module,
DDS forms m channel according to channel control signals and frequency control signal, and the signal in m channel is successively looked into from corresponding waveform
It looks in table RAM, obtains amplitude signal corresponding to phase, then send amplitude signal in DAC module and carry out digital-to-analogue conversion；Often
The output end of a DAC module connects a filter module, and the output of all filter modules connects feedback module；
The feedback module is made of a multiple selector and an ADC module；The output end of m filter module is all connected with institute
Multiple selector is stated, the output end of multiple selector connects ADC module, the feedback signal of the output end connection FPGA of ADC module
Processing module；
The feedback signal processing module include sequentially connected zero point detection module, state detection unit, phase compensation unit,
Phase difference calculating unit and phase only pupil filter unit；
The zero point detection module is made of comparator, the counter of m systems and memory, and the counter starts counting
When, the amplitude signal sampled is compared by the comparator with the minimum amplitude signal in m channel, detects that amplitude is big
Waveform signal is stored in memory when minimum amplitude；
The state detection unit is to each previous amplitude signal in channel road and the latter amplitude signal taken out from memory
It is compared, by comparison result input phase compensating unit；
The testing result of phase compensation unit state detection unit based on the received, is obtained respectively by phase look-up table RAM
The phase in channel, and each channel phases are compensated；
The compensated phase value of phase compensation unit and preset initial phase signal are carried out phase by the phase difference calculating unit
Subtract to obtain each phase difference between channels, is input to phase only pupil filter unit modification initial phase signal, and feed back to DDS and be modified.
2. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is, further includes having source crystal oscillator, by there is source crystal oscillator to generate clock signal fcLk, and it is connected respectively to FPGA, DAC module, anti-
In the multiple selector and ADC module for presenting module.
3. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is that the FPGA receiving channel control signal and frequency control signal generate a corresponding phase accumulator, by phase
The data of accumulator output are sent into corresponding m adder to add up with received initial phase signal, obtains each logical
The address information in road searches the corresponding amplitude signal of phase according to address information into its corresponding waveform look-up table RAM.
4. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is, further includes start key, and the FPGA receives data by jtag interface, after data are transmitted, presses start key, opens
Dynamic DDS work.
5. a kind of multichannel ultrasonic arbitrary waveform signal generator with feedback compensation according to claim 1, special
Sign is, generates phase at the end PC using MATLAB and turns the .mif file of amplitude and the .mif file of amplitude phase inversion position；Pass through
Data are passed in the development board of altera corp's fpga chip by jtag interface.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110324051A (en) * | 2019-06-24 | 2019-10-11 | 成都振芯科技股份有限公司 | The adaptability Enhancement Method and device of sendaisle quadrature alignment |
| WO2022029125A1 (en) * | 2020-08-07 | 2022-02-10 | Comet Ag | Control unit, radio frequency power generator, and method for generating synchronized radio frequency output signals |
| CN116879911A (en) * | 2023-09-06 | 2023-10-13 | 成都量芯集成科技有限公司 | Device for improving laser ranging distance and implementation method thereof |
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2018
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110324051A (en) * | 2019-06-24 | 2019-10-11 | 成都振芯科技股份有限公司 | The adaptability Enhancement Method and device of sendaisle quadrature alignment |
| WO2022029125A1 (en) * | 2020-08-07 | 2022-02-10 | Comet Ag | Control unit, radio frequency power generator, and method for generating synchronized radio frequency output signals |
| US12126347B2 (en) | 2020-08-07 | 2024-10-22 | Comet Ag | Control unit, radio frequency power generator, and method for generating synchronized radio frequency output signals |
| CN116879911A (en) * | 2023-09-06 | 2023-10-13 | 成都量芯集成科技有限公司 | Device for improving laser ranging distance and implementation method thereof |
| CN116879911B (en) * | 2023-09-06 | 2023-12-05 | 成都量芯集成科技有限公司 | Device for improving laser ranging distance and implementation method thereof |
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