CN114499147A - Calibration circuit, calibration method, calibration device and medium of delay circuit - Google Patents
Calibration circuit, calibration method, calibration device and medium of delay circuit Download PDFInfo
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- CN114499147A CN114499147A CN202210176446.4A CN202210176446A CN114499147A CN 114499147 A CN114499147 A CN 114499147A CN 202210176446 A CN202210176446 A CN 202210176446A CN 114499147 A CN114499147 A CN 114499147A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
Abstract
The application discloses calibration circuit, calibration method, device and medium of delay circuit, be applied to communication technology field, in this calibration circuit, delay time memory circuit links to each other with difference acquisition circuit, difference acquisition circuit links to each other with control circuit, delay time memory circuit links to each other with delay circuit's input and output, difference acquisition circuit acquires the first length difference between the first length information that adjacent frequency control word corresponds, control circuit adjusts the corresponding relation of frequency control word and delay control word so that every two adjacent first length differences are equal, namely make frequency control word and delay time be the direct ratio relation. The delay time storage circuit is also used for storing second length information, and the difference value acquisition circuit acquires a second length difference value between the first length information and the second length information of the delay time corresponding to the maximum frequency control word; the control circuit adjusts the corresponding relation between the frequency control word and the delay control word in equal proportion to reduce the second length difference.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a calibration circuit, a calibration method, a calibration device, and a medium for a delay circuit.
Background
In a modern wireless communication system, when a radio frequency system needs a phase-locked loop to simultaneously output a clock with a frequency not having a common multiple relation, fractional frequency division needs to be carried out. One method of implementing fractional division is phase interpolation, which avoids phase errors and spurs by delaying the phase of the output clock to align it with the desired clock phase. The main way of phase interpolation is to use a delay circuit, such as a Digital-to-Time Converter (DTC), to make an absolute Time delay to the phase of the clock signal.
Due to the fluctuation of the chip manufacturing process and the uncertainty of the chip application environment, the frequency control word sent by the frequency division control circuit and the delay time generated by the delay circuit do not change linearly, i.e. the frequency control word cannot accurately and linearly control the delay time of the delay circuit. It is necessary to calibrate the linearity of the delay circuit.
Therefore, it is obvious that those skilled in the art need to solve the problem of how to calibrate the corresponding relationship between the delay time of the delay circuit and the frequency control word, so that the frequency control word can accurately and linearly control the delay time of the delay circuit.
Disclosure of Invention
The invention aims to provide a calibration circuit, a calibration method, a calibration device and a medium of a delay circuit, so as to calibrate the corresponding relation between the delay time of the delay circuit and a frequency control word, and enable the frequency control word to accurately and linearly control the delay time of the delay circuit.
To solve the above technical problem, the present application provides a calibration circuit of a delay circuit, including: the delay time acquisition circuit comprises a delay time storage circuit, a difference value acquisition circuit and a control circuit;
the delay time storage circuit is connected with the input end and the output end of the delay circuit and is used for storing first length information of delay time corresponding to a plurality of frequency control words with the same interval of the delay circuit and storing second length information obtained by adding the first length information of the delay time corresponding to a minimum frequency control word to a clock cycle of an input signal of the delay circuit, wherein the minimum frequency control word is the frequency control word corresponding to the minimum delay time of the delay circuit;
the difference obtaining circuit is connected to the delay time storage circuit, and is configured to receive the first length information and the second length information, obtain a first length difference between the first length information corresponding to adjacent frequency control words, and obtain a second length difference between the first length information and the second length information of the delay time corresponding to a maximum frequency control word, where the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit;
the control circuit is connected with the difference value acquisition circuit and used for adjusting the corresponding relation between the frequency control word and the delay control word according to the first length difference value so as to enable every two adjacent first length difference values to be equal, and adjusting the corresponding relation between the frequency control word and the delay control word according to the second length difference value in an equal proportion so as to reduce the second length difference value, wherein the delay control word is used for controlling the delay time of the delay circuit.
Preferably, the delay circuit is a DTC, and the delay time storage circuit includes: the system comprises a D trigger, a multi-channel selector, a pulse generating circuit and a charge pump circuit;
the input end of the DTC is directly connected with a first path of a first end of the multi-path check device, the input end of the DTC is also connected with a first end of the D trigger, a second path of the first end of the multi-path check device is connected with a second end of the D trigger, when the first path of the multi-path check device is selected to be switched on, the multi-path check device is used for receiving a plurality of input signals corresponding to the frequency control words at the same interval, when the second path of the multi-path check device is selected to be switched on, the check device is used for receiving the input signals corresponding to the minimum frequency control words passing through the D trigger, and the D trigger is used for adding the clock period of the input signals to the input signals corresponding to the minimum frequency control words;
the first path of the first end of the pulse generating circuit is connected with the second end of the multi-path check device, the second path of the first end of the pulse generating circuit is connected with the output end of the DTC, and the pulse generating circuit is used for converting the delay time between the input signal selected by the multi-path check device and the output signal of the DTC into pulse width;
and the first end of the charge pump circuit is connected with the second end of the pulse generation circuit and is used for converting the pulse width into a voltage value and storing the voltage value in the pulse generation circuit, wherein the voltage value is the first length information and the second length information.
Preferably, the difference acquisition circuit is an operational amplifier;
the first end of the operational amplifier is connected to the second end of the charge pump circuit, and is configured to receive the voltage value, obtain a first voltage difference value of the voltage value corresponding to the adjacent frequency control words, and obtain a second voltage difference value between the voltage value corresponding to the maximum frequency control word and the voltage value corresponding to the minimum frequency control word after passing through the D flip-flop.
Preferably, the control circuit includes: a comparator, a control coding circuit;
the first path of the first end of the comparator is connected with the second end of the operational amplifier, when the first path of the first end of the comparator receives the first output voltage, the second path of the first end of the comparator inputs a first reference voltage, the comparator is used for comparing the first output voltage with the first reference voltage to obtain a first comparison result, when the first path of the first end of the comparator receives the second output voltage, the second path of the first end of the comparator inputs a second reference voltage, and the comparator is used for comparing the second output voltage with the second reference voltage to obtain a second comparison result;
the control coding circuit is connected with the second end of the comparator and used for receiving the first comparison result and the second comparison result, the control coding circuit is further connected with a frequency division control circuit and the DTC and used for receiving the frequency control word sent by the frequency division control circuit and obtaining the corresponding delay control word according to the frequency control word to control the delay time of the DTC, the control coding circuit further adjusts the corresponding relation between the frequency control word and the delay control word according to the first comparison result so as to enable the first output voltage to be equal to the first reference voltage, and the control coding circuit further adjusts the corresponding relation between the frequency control word and the delay control word according to the second comparison result so as to enable the second output voltage to be equal to the second reference voltage.
Preferably, two capacitors are disposed inside the charge pump circuit, and are used for respectively storing the voltage values corresponding to two adjacent frequency control words, so that the operational amplifier can obtain the first voltage difference value; and the operational amplifier is further configured to store the voltage value corresponding to the maximum frequency control word and the voltage value corresponding to the minimum frequency control word after passing through the D flip-flop, so that the operational amplifier can obtain the second voltage difference.
Preferably, the multi-way checker is a two-way checker.
In order to solve the above technical problem, the present application further provides a calibration method for a delay circuit, which is applied to the calibration circuit for a delay circuit, and includes:
adjusting a corresponding relation between a frequency control word and a delay control word according to a first length difference value so as to enable every two adjacent first length difference values to be equal, wherein the delay time storage circuit is used for storing first length information of the delay time corresponding to a plurality of frequency control words at the same interval of the delay circuit, the first length difference value is a difference value between the first length information corresponding to the adjacent frequency control words acquired by the difference acquisition circuit, and the delay control word is used for controlling the delay time of the delay circuit;
and adjusting the correspondence between the frequency control word and the delay control word in an equal proportion according to a second length difference value to reduce the second length difference value, wherein the delay time storage circuit is further configured to store first length information of the delay time corresponding to a minimum frequency control word and second length information obtained by adding a clock period of an input signal of the delay circuit, the minimum frequency control word is the frequency control word corresponding to the minimum delay time of the delay circuit, the second length difference value is a difference value between the first length information and the second length information of the delay time corresponding to a maximum frequency control word obtained by the difference value obtaining circuit, and the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit.
In order to solve the above technical problem, the present application further provides a calibration apparatus for a delay circuit, which is applied to the calibration circuit for a delay circuit, and includes:
a first adjusting module, configured to adjust a correspondence between a frequency control word and a delay control word according to a first length difference value, so that each two adjacent first length difference values are equal, where the delay time storage circuit is configured to store first length information of the delay time corresponding to a plurality of frequency control words at the same interval in the delay circuit, the first length difference value is a difference value between the first length information corresponding to adjacent frequency control words acquired by the difference acquisition circuit, and the delay control word is used to control the delay time of the delay circuit;
a second adjusting module for adjusting the corresponding relationship between the frequency control word and the delay control word according to a second length difference in an equal proportion to reduce the second length difference, wherein the delay time storage circuit is further configured to store first length information of the delay time corresponding to a minimum frequency control word plus second length information obtained by adding a clock period of an input signal of the delay circuit, wherein the minimum frequency control word is the frequency control word corresponding to the delay time for which the delay circuit is minimum, the second length difference is a difference between the first length information and the second length information of the delay time corresponding to the maximum frequency control word acquired by the difference acquisition circuit, wherein the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit.
In order to solve the above technical problem, the present application further provides a calibration apparatus for a delay circuit, including: a memory for storing a computer program;
a processor for implementing the steps of the calibration method of the delay circuit when executing the computer program.
To solve the above technical problem, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the calibration method for the delay circuit.
In the calibration circuit of the delay circuit, the delay time storage circuit is connected with the difference value acquisition circuit, the difference value acquisition circuit is connected with the control circuit, the frequency control word and the delay control word are in a corresponding relation, the delay control word is used for controlling the delay time of the delay circuit, generally, the larger the frequency control word is, the larger the corresponding delay control word is, and the larger the delay time of the delay circuit controlled by the delay control word is; the delay time storage circuit is connected with the input end and the output end of the delay circuit and used for storing first length information of delay time corresponding to a plurality of frequency control words with the same interval in the delay circuit, the difference acquisition circuit acquires a first length difference between the first length information corresponding to adjacent frequency control words, and the control circuit is used for adjusting the corresponding relation between the frequency control words and the delay control words according to the first length difference so as to enable every two adjacent first length differences to be equal, namely, the frequency control words and the delay time are in a direct proportion relation. The delay circuit comprises a delay circuit input signal, a frequency control word and a delay time storage circuit, wherein the frequency control word comprises a maximum frequency control word and a minimum frequency control word, the maximum frequency control word is a frequency control word corresponding to the maximum delay time of the delay circuit, the minimum frequency control word is a frequency control word corresponding to the minimum delay time of the delay circuit, the delay time storage circuit is also used for storing second length information obtained by adding the clock period of the input signal of the delay circuit and first length information of the delay time corresponding to the minimum frequency control word, and the difference acquisition circuit is also used for acquiring a second length difference between the first length information and the second length information of the delay time corresponding to the maximum frequency control word; the control circuit is further configured to adjust a corresponding relationship between the frequency control word and the delay control word in an equal proportion according to the second length difference to reduce the second length difference, so that the first length information and the second length information of the delay time corresponding to the maximum frequency control word are equal, that is, on the basis of maintaining the proportional relationship between the frequency control word and the delay time unchanged, the delay time corresponding to the maximum frequency control word is equal to a standard time, where the standard time is a clock period of the input signal of the delay circuit plus the minimum delay time of the delay circuit. After two times of adjustment, the corresponding relation between the delay time of the delay circuit and the frequency control word can be calibrated, so that the frequency control word can accurately and linearly control the delay time of the delay circuit.
The application also provides a calibration method, a device and a medium of the delay circuit, which correspond to the calibration circuit, so that the calibration circuit has the same beneficial effects as the calibration circuit.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a block diagram of an open loop fractional divider circuit;
FIG. 2 is a schematic diagram of the linearity of the delay circuit;
fig. 3 is a block diagram of a calibration circuit according to an embodiment of the present disclosure;
fig. 4 is a flowchart of a calibration method for a delay circuit according to an embodiment of the present disclosure;
fig. 5 is a structural diagram of a calibration apparatus of a delay circuit according to an embodiment of the present application;
fig. 6 is a block diagram of a calibration apparatus for a delay circuit according to another embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without any creative effort belong to the protection scope of the present application.
The core of the application is to provide a calibration circuit, a calibration method, a device and a medium of a delay circuit.
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings.
The traditional fractional frequency division scheme is to modulate the frequency division ratio of the multi-mode frequency division circuit to obtain the effect of fractional frequency division. When the desired division ratio is a non-integer multiple of the period of the input clock signal of the multi-modulus divider circuit, e.g., 4.25, the actual division behavior of the multi-modulus divider circuit consists of 3 divisions by 4 and 1 division by 5, thus exhibiting an average division by 4.25 over 17 input signal periods. This way a phase difference exists between the phase of the resulting divided signal and the true divided-by 4.25 signal, which in turn results in a large deterministic clock jitter. The purpose of connecting the delay circuit behind the frequency dividing circuit is to eliminate the phase difference generated in the process, so that the phase of the output clock signal after frequency division is consistent with the phase of the ideal decimal frequency dividing signal, and the purpose of optimizing clock jitter is achieved. In order to ensure that the phase of the output clock signal is consistent with that of the ideal fractional division signal, the delay circuit is required to generate an accurately controllable delay between its input signal and its output signal. Because the chip manufacturing process fluctuates and the chip application environment is uncertain, the relationship between the delay time generated by the delay circuit and the control word of the delay circuit is not linearly changed, so a circuit is specially designed in the open-loop fractional frequency division circuit, the delay of the delay circuit can be adjusted while the delay circuit works, and the delay control word can accurately and linearly control the delay of the circuit.
Fig. 1 is a structural diagram of an open-loop fractional frequency division circuit, which includes a frequency division circuit 101, a delay circuit 102, a frequency division control circuit 103, and a delay calibration circuit 104, where the frequency division ratio of the input/output signal of the frequency division circuit 101 is controllable N frequency division and N +1 frequency division, and the implementation of the module is various, and will not be described in detail in this embodiment of the present application. The delay circuit 102 is a controllable delay circuit, and a DTC is shown as the delay circuit 102, which functions to convert the delay control word into an input-output delay time. The frequency division control signal FCW input by the frequency division control circuit 103, the derived output signal FCW _ INT controls the frequency division circuit 101 to select N frequency division or N +1 frequency division, and the derived output signal FCW _ FRAC controls the delay time of the delay circuit 102. The control word is divided into a frequency control word and a delay control word, which are in one-to-one correspondence, the frequency control word is an output signal FCW _ FRAC of the frequency division control circuit 103, and the delay control word DCW is a control word for actually controlling the delay time. The delay calibration circuit 104 is used to calibrate the correspondence between the frequency control word FCW _ FRAC and the delay control word DCW.
The input clock signal FIN to be divided is frequency-divided by the frequency dividing circuit 101, and the frequency-divided signal FDIV is input to the delay circuit 102 to generate an output clock signal FOUT meeting the frequency dividing ratio requirement. If the frequency of the input clock signal FIN is represented as f _ FIN, the period is represented as T _ FIN, the frequency of the signal FOUT is represented as f _ FOUT, and the period is represented as T _ FOUT, the frequency relationship between the signal FIN and the signal FOUT is f _ FIN ═ FCW ═ f _ FOUT, and the period relationship is T _ FOUT ═ FCW ═ T _ FIN. The frequency division control circuit 103 processes the frequency division ratio control signal FCW and outputs two signals, FCW _ INT and FCW _ FRAC. The FCW _ INT signal is input to the frequency dividing circuit 101, the frequency dividing ratio of the frequency dividing circuit 101 is controlled, and the FCW _ FRAC signal is input to the delay calibration circuit 104. The signal DCW generated after the processing of the delay calibration circuit 104 is output to the delay circuit 102, and controls the delay between the input signal FDIV and the output signal FOUT in the delay circuit 102. The frequency dividing circuit 101 is controlled by FCW _ INT, and the ratio of the frequencies of its input signal FIN and its output signal FDIV varies between an integer value FCW _ INT and an integer value FCW _ INT. The specific implementation of the frequency divider circuit 101 is not specifically described in the embodiments of the present application. The FDIV signal is delayed appropriately by the delay circuit to obtain a FOUT signal, and the phase of the FOUT signal is consistent with the phase of the actually required frequency division signal. Fig. 2 is a schematic diagram of the linearity of the delay circuit, and as shown in fig. 2, when the delay control word DCW is DCW1, the delay TD between the input signal and the output signal of the delay circuit is T0+ DCW1 Δ T, and when the delay control word DCW is n + DCW1, the delay TD between the input signal and the output signal of the delay circuit is T0+ n DCW1 Δ T, the relationship between DCW and TD is said to be linearly changed, and n is an integer greater than 1.
Wherein the delay calibration circuit 104 comprises: the delay time acquisition circuit comprises a delay time storage circuit, a difference value acquisition circuit and a control circuit; the delay time storage circuit is connected with the input end and the output end of the delay circuit and is used for storing first length information of delay time corresponding to a plurality of frequency control words with the same interval of the delay circuit and second length information obtained by adding the first length information of the delay time corresponding to the minimum frequency control word to the clock period of an input signal of the delay circuit, wherein the minimum frequency control word is the frequency control word corresponding to the minimum delay time of the delay circuit; the difference value acquisition circuit is connected with the delay time storage circuit and used for receiving the first length information and the second length information, acquiring a first length difference value between the first length information corresponding to adjacent frequency control words and acquiring a second length difference value between the first length information and the second length information of the delay time corresponding to the maximum frequency control word, wherein the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit; the control circuit is connected with the difference value acquisition circuit and used for adjusting the corresponding relation between the frequency control word and the delay control word according to the first length difference value so as to enable every two adjacent first length difference values to be equal, and adjusting the corresponding relation between the frequency control word and the delay control word in an equal proportion according to the second length difference value so as to reduce the second length difference value, wherein the delay control word is used for controlling the delay time of the delay circuit.
Fig. 3 is a block diagram of a calibration circuit according to an embodiment of the present disclosure; the figure includes a frequency division circuit 101, a delay circuit 102, a frequency division control circuit 103, and a delay calibration circuit 104, and the connection relationship has already been described in fig. 1 and will not be described again. Delay circuit 102 is a DTC and delay calibration circuit 104 includes: a TFIN generating circuit 201, a pulse generator circuit 202 (PG), a charge pump circuit 203, an operational amplifier 204, a comparator 205, and a control coding circuit 206, wherein the TFIN generating circuit 201 includes a D flip-flop DFF and a multi-way check MUX, that is, the delay time storage circuit includes: the TFIN generating circuit 201, the pulse generating circuit 202, the charge pump circuit 203, the difference value obtaining circuit is an operational amplifier 204, and the control circuit includes: comparator 205, control coding circuit 206. The device shown in fig. 3 is only one implementation manner provided by the embodiment of the present application, and does not limit other manners of the present application. The first step is to calibrate the delay variation caused by device mismatch, configure the TFIN generation circuit 201, select the input signal FDIV of the DTC as the input of the multiplexer MUX and input it to the pulse generation circuit 202, the output signal FOUT of the DTC as the other input of the pulse generation circuit 202, and the pulse generation circuit 202 converts the delay time between MUXOUT and FOUT generated by FDIV into a pulse width, where MUXOUT is the output of the multiplexer. FCW _ INT controls the frequency dividing circuit 101 to set its frequency dividing ratio to N, adjusts the fractional part of FCW according to a certain step length, and makes the frequency control word FCW _ FRAC increase linearly, the delay control word DCW increases linearly, and controls the input-output delay time of DTC to increase linearly, and the pulse generating circuit 202 can obtain the delay time corresponding to the frequency control word FCW _ FRAC of the same interval, and convert the delay time into the pulse width, which is equivalent to the first length information of the delay time corresponding to the plurality of frequency control words of the same interval. The delay control word DCW comprises DCW _ CT and DCW _ FT, wherein DCW _ CT is coarse adjustment and discrete adjustment and controls the number of accessed capacitors, and DCW _ FT is fine adjustment and continuous adjustment and controls the size of the accessed variable capacitor. The frequency control words of adjacent two cycles in the first step are changed at equal intervals, and it is assumed that, in the present cycle, switches before and after the charge pump circuit 203 are switched so that a voltage value generated by a delay time between MUXOUT and FOUT generated by FDIV is stored in the capacitor C1, and in the next cycle, switches before and after the charge pump circuit 203 are switched so that a voltage generated by a delay time between MUXOUT and FOUT generated by FDIV in the next cycle is stored in the capacitor C2. The operational amplifier obtains the output voltage according to the relationship between the two, and after comparing the output voltage with the reference voltage, the operational amplifier can adjust the corresponding relationship between the frequency control word and the delay control word according to the comparison result. The pulse width output by the pulse generating circuit 202 is converted into a voltage value by the charge pump circuit 203, further amplified by the operational amplifier 204 and generates an output voltage VTD (in this case, a first output voltage), the comparator 205 compares the first output voltage with a reference voltage VTD _0 (in this case, a first reference voltage), and the control encoding circuit 206 generates a feedback control signal to control the input-output delay of the DTC circuit. The corresponding relationship between the frequency control word and the delay control word is adjusted by the control encoding circuit 206, so that the delay time of the adjacent delay units is equal, i.e. the voltage of the VTD is equal to VTD _0, which is equivalent to the first output voltage being equal to the first reference voltage, and is also equivalent to the difference between the two adjacent first lengths being equal. Each two adjacent delay cells in the DTC are calibrated so that eventually each delay step of the DTC is equal. When the number of the frequency control words is larger, that is, the interval between each frequency control word is smaller, the calibration precision is higher, but the required calibration time is also longer, and when the number of the frequency control words is smaller, the interval is larger, the calibration precision is lower, the required calibration time is shorter, and how to take the value is based on the actual situation. In the second step, the full scale of the DTC is calibrated, the TFIN generating circuit 201 is configured, the output of the D flip-flop DFF is selected as the input of the multi-channel check MUX, the FCW _ INT controls the frequency dividing circuit 101, the frequency dividing ratio is set to N, and the frequency control word FCW _ FRAC is set to 0, i.e., the minimum frequency control word. The DTC now produces a signal delayed by only its own minimum delay T0, and MUXOUT is a TFIN-delayed signal of FDIV. At this time, the output VPULSE of the pulse generating circuit 202 is a pulse signal with a width of T0-TFIN, corresponding to the second length information. The switch and charge pump circuit 203 is controlled to first reduce the voltage on the capacitor C1 to 0V by the RST1 signal, and then convert the pulse width to a voltage value, which is stored on the capacitor C1 and is denoted as V1. In the next cycle, TFIN generation circuit 201 is configured to select FDIV as the input of MUX, FCW _ INT controls frequency divider circuit 101 to set its division ratio to N, so that frequency control word FCW _ FRAC is maximized, i.e., the maximum frequency control word, and DCW _ CT is maximized. The delay of the signal generated by the DTC is its own maximum delay TD _ MAX, and the pulse width of the VPULSE signal output by the pulse generating circuit 202 is T0-TD _ MAX, i.e. the first length information corresponding to the maximum frequency control word. The switch and charge pump circuit 203 is controlled to first reduce the voltage on the capacitor C2 to 0 by the RST2 signal, convert the pulse width to a voltage value, and store the voltage value in the capacitor C2 of the charge pump circuit, which is denoted as V2. At this time, the operational amplifier 204 generates the output voltage VTD (at this time, the second output voltage), the comparator 205 compares the second output voltage with the reference voltage VTD _0 (at this time, the second reference voltage), if V1 is not equal to V2, the second output voltage is different from the second reference voltage, the control encoding circuit 206 adjusts the correspondence relationship between the frequency control word and the delay control word, so that V1 is equal to V2, at this time, the second output voltage is equal to the reference voltage VTD _0 (at this time, the second reference voltage), at this time, the second output voltage is equal to the second reference voltage, which also corresponds to the second length difference being zero.
The two steps can be regarded as a foreground calibration stage, and in the background calibration stage, the value of the FCW is determined by the frequency dividing ratio, and the FCW cannot be controlled and calibrated any more. However, during the normal operation of the DTC, the FCW _ FRAC value changes linearly, so that the delay of the FOUT can be controlled to keep the signal delay of each adjacent period consistent by comparing and recording the change of the delay of each adjacent clock rising edge of the FOUT by a mechanism similar to the first step in the foreground calibration.
In the calibration circuit of the delay circuit, the delay time storage circuit is connected with the difference value acquisition circuit, the difference value acquisition circuit is connected with the control circuit, the frequency control word and the delay control word are in a corresponding relation, the delay control word is used for controlling the delay time of the delay circuit, generally, the larger the frequency control word is, the larger the corresponding delay control word is, and the larger the delay time of the delay circuit controlled by the delay control word is; the delay time storage circuit is connected with the input end and the output end of the delay circuit and used for storing first length information of delay time corresponding to a plurality of frequency control words with the same interval in the delay circuit, the difference acquisition circuit acquires a first length difference between the first length information corresponding to adjacent frequency control words, and the control circuit is used for adjusting the corresponding relation between the frequency control words and the delay control words according to the first length difference so as to enable every two adjacent first length differences to be equal, namely, the frequency control words and the delay time are in a direct proportion relation. The delay circuit comprises a delay circuit input signal, a frequency control word and a delay time storage circuit, wherein the frequency control word comprises a maximum frequency control word and a minimum frequency control word, the maximum frequency control word is a frequency control word corresponding to the maximum delay time of the delay circuit, the minimum frequency control word is a frequency control word corresponding to the minimum delay time of the delay circuit, the delay time storage circuit is also used for storing second length information obtained by adding the clock period of the input signal of the delay circuit and first length information of the delay time corresponding to the minimum frequency control word, and the difference acquisition circuit is also used for acquiring a second length difference between the first length information and the second length information of the delay time corresponding to the maximum frequency control word; the control circuit is further configured to adjust a corresponding relationship between the frequency control word and the delay control word in an equal proportion according to the second length difference to reduce the second length difference, so that the first length information and the second length information of the delay time corresponding to the maximum frequency control word are equal, that is, on the basis of maintaining the proportional relationship between the frequency control word and the delay time unchanged, the delay time corresponding to the maximum frequency control word is equal to a standard time, where the standard time is a clock period of the input signal of the delay circuit plus the minimum delay time of the delay circuit. After two times of adjustment, the corresponding relation between the delay time of the delay circuit and the frequency control word can be calibrated, so that the frequency control word can accurately and linearly control the delay time of the delay circuit.
In the above embodiment, what kind of specific devices are used for the delay time storage circuit, the difference obtaining circuit, and the control circuit is not limited, and in practical application, a better effect can be achieved by using a more appropriate device, so that the embodiment of the present application provides one of the solutions, taking fig. 3 as an example, where the delay circuit uses DTC, and the delay time storage circuit includes: d flip-flop, multichannel check, pulse generation circuit, charge pump circuit, difference acquisition circuit are operational amplifier, and control circuit includes: the comparator and the control coding circuit are not limited to the models of the devices, and the actual conditions are used as the standard.
The input end of the delay circuit is directly connected with a first path of a first end of a multi-path check device, the input end of the delay circuit is also connected with a first end of a D trigger, a second path of the first end of the multi-path check device is connected with a second end of the D trigger, when the first path of the multi-path check device is selected to be switched on, the multi-path check device is used for receiving input signals corresponding to a plurality of frequency control words with the same interval, when the second path of the multi-path check device is selected to be switched on, the multi-path check device is used for receiving input signals corresponding to the minimum frequency control words passing through the D trigger, and the D trigger is used for adding clock periods of the input signals to the input signals corresponding to the minimum frequency control words. The first path of the first end of the pulse generating circuit is connected with the second end of the multi-path check device, the second path of the first end of the pulse generating circuit is connected with the output end of the delay circuit, and the pulse generating circuit is used for converting the delay time between the input signal selected by the multi-path check device and the output signal of the delay circuit into pulse width. The first end of the charge pump circuit is connected with the second end of the pulse generating circuit, and the charge pump circuit is used for converting the pulse width into a voltage value and storing the voltage value in the pulse generating circuit, wherein the voltage value is the first length information and the second length information.
The multi-channel check device is not limited to several channels, wherein the first channel may be multiple channels, and is respectively used for receiving input signals corresponding to different frequency control words. The internal structure of the charge pump circuit is not limited, and the charge pump circuit may have a plurality of capacitors therein to store a plurality of voltage values, and then the voltage values are transmitted to the operational amplifier to calculate the difference values respectively.
The first end of the operational amplifier is connected with the second end of the charge pump circuit, and is used for receiving the voltage value and obtaining a first voltage difference value of the corresponding voltage value between the adjacent frequency control words, and is also used for obtaining a second voltage difference value between the voltage value corresponding to the maximum frequency control word and the voltage value corresponding to the minimum frequency control word after the D trigger, when the adjacent first voltage difference values are equal, the first output voltage of the operational amplifier is equal to the first reference voltage, and when the second voltage difference value is zero, the second output voltage is equal to the second reference voltage.
The first end of the operational amplifier is connected with the second end of the charge pump circuit and used for receiving the voltage value sent by the charge pump circuit, when calculating the difference, a plurality of first voltage difference values can be calculated at the same time and also one first voltage difference value can be calculated at each time, the operational amplifier is related to the structure of the charge pump circuit in practical application, when only one first voltage difference value is calculated at each time, two capacitors can be arranged in the charge pump circuit and respectively store two adjacent voltage values, and after the first voltage difference value is calculated, one voltage value can be stored, only the other voltage value adjacent to the stored voltage value needs to be stored in the charge pump circuit, namely the charge pump circuit can alternately store two voltage values so that the operational amplifier can calculate the difference value.
The first path of the first end of the comparator is connected with the second end of the operational amplifier, when the first path of the first end of the comparator receives a first output voltage, the second path of the first end of the comparator inputs a first reference voltage, the comparator is used for comparing the first output voltage with the first reference voltage to obtain a first comparison result, when the first path of the first end of the comparator receives a second output voltage, the second path of the first end of the comparator inputs a second reference voltage, and the comparator is used for comparing the second output voltage with the second reference voltage to obtain a second comparison result. The control coding circuit is connected with the second end of the comparator and used for receiving the first comparison result and the second comparison result, the control coding circuit is further connected with the frequency division control circuit and the delay circuit and used for receiving the frequency control word sent by the frequency division control circuit and obtaining the corresponding delay control word according to the frequency control word so as to control the delay time of the delay circuit, the control coding circuit further adjusts the corresponding relation between the frequency control word and the delay control word according to the first comparison result so that the first output voltage is equal to the first reference voltage, and the control coding circuit further adjusts the corresponding relation between the frequency control word and the delay control word according to the second comparison result so that the second output voltage is equal to the second reference voltage.
The voltage value is the first length information and the second length information mentioned in the above example, which represent the length of the DTC delay time, and during the first stage calibration, the control encoding circuit adjusts the corresponding relationship between the frequency control word and the delay control word according to the first comparison result, so that the first output voltage is equal to the first reference voltage, that is, the difference between the delay times corresponding to every two adjacent frequency control words is the same, and the length of the delay time is changed in equal proportion to the length of the frequency control word. And after the first-stage calibration is finished, the second-stage calibration is carried out, the control coding circuit adjusts the corresponding relation between the frequency control word and the delay control word in an equal proportion according to a second comparison result so as to enable the first output voltage to be equal to the first reference voltage, namely the delay time corresponding to the maximum frequency control word is equal to the standard time, and the standard time is the clock period of the input signal of the delay circuit plus the minimum delay time of the delay circuit.
The embodiment of the application provides specific devices of a delay time storage circuit, a difference value acquisition circuit and a control circuit, and provides specific connection modes of various devices, in specific implementation, other devices can be used for replacing the devices, and other connection modes can also be adopted for realizing the adjustment process. The scheme can be calibrated by using only one DTC, and other auxiliary DTCs are not needed to assist in calibration, so that power consumption can be saved.
In the above embodiment, the specific structure of the charge pump circuit is not limited, and only the charge pump circuit needs to store a voltage value, and in order to avoid the power consumption of the circuit being too high, only two capacitors are arranged inside the charge pump circuit and used for respectively storing the voltage values corresponding to two adjacent frequency control words, so that the operational amplifier can obtain the first voltage difference value; and the D flip-flop is further used for respectively storing the voltage value corresponding to the maximum frequency control word and the voltage value corresponding to the minimum frequency control word after passing through the D flip-flop so that the operational amplifier can obtain a second voltage difference value. After the difference between the voltage values corresponding to two adjacent frequency control words is calculated, the smaller voltage value is removed, the larger voltage value is reserved, the other adjacent voltage value with the larger voltage value is stored in the charge pump circuit so as to be convenient for the calculation of the operational amplifier, the first voltage difference is calculated according to the step, and finally the second voltage difference is calculated. According to the scheme provided by the embodiment of the application, the operational amplifier only carries out calculation once at a time, and a simpler structure is adopted to realize more efficient calculation.
In the above embodiments, it is not limited that the multi-way checkers are specifically several ways, but in practical applications, the multi-way checkers may select two ways of checkers, that is, the first way mentioned in the above embodiments is one way for receiving input signals corresponding to a plurality of frequency control words at the same interval, and the second way is also one way for receiving an input signal corresponding to a minimum frequency control word passing through the D flip-flop. According to the scheme provided by the embodiment of the application, a complex circuit structure is not needed, and only the first path of input signals corresponding to the frequency control words which are increased according to the same interval are received at each preset time interval.
Fig. 4 is a flowchart of a calibration method for a delay circuit according to an embodiment of the present application, which is applied to the calibration circuit for a delay circuit, and the method includes the following steps:
s10: and adjusting the corresponding relation between the frequency control word and the delay control word according to the first length difference value so as to enable every two adjacent first length difference values to be equal.
The delay time storage circuit is used for storing first length information of delay time corresponding to a plurality of frequency control words with the same interval of the delay circuit, the first length difference is the difference between the first length information corresponding to adjacent frequency control words acquired by the difference acquisition circuit, and the delay control words are used for controlling the delay time of the delay circuit;
s11: and according to the second length difference value, the corresponding relation between the frequency control word and the delay control word is adjusted in an equal proportion so as to reduce the second length difference value.
The delay time storage circuit is further configured to store first length information of delay time corresponding to a minimum frequency control word, which is a frequency control word corresponding to a minimum delay time of the delay circuit, and second length information obtained by adding a clock period of an input signal of the delay circuit to the first length information of delay time corresponding to a maximum frequency control word obtained by the difference obtaining circuit, where the second length difference is a difference between the first length information of delay time corresponding to the maximum frequency control word obtained by the difference obtaining circuit and the second length information, and the maximum frequency control word is a frequency control word corresponding to a maximum delay time of the delay circuit.
Since the embodiment of the method portion corresponds to the embodiment of the calibration circuit portion of the delay circuit, please refer to the description of the embodiment of the calibration circuit portion of the delay circuit for the embodiment of the method portion, which is not repeated here.
The calibration method of the delay circuit provided by the embodiment corresponds to the calibration of the delay circuit, and therefore has the same beneficial effects as the calibration of the delay circuit.
In the foregoing embodiments, the calibration method of the delay circuit is described in detail, and the present application also provides embodiments corresponding to the calibration apparatus of the delay circuit. It should be noted that the present application describes the embodiments of the apparatus portion from two perspectives, one from the perspective of the function module and the other from the perspective of the hardware.
Based on the angle of the functional module, this embodiment provides a calibration apparatus for a delay circuit, fig. 5 is a structural diagram of the calibration apparatus for a delay circuit provided in this embodiment of the present application, and as shown in fig. 5, the apparatus includes:
a first adjusting module 30, configured to adjust a correspondence between the frequency control word and the delay control word according to a first length difference value, so that each two adjacent first length difference values are equal, where the delay time storage circuit is configured to store first length information of delay times corresponding to multiple frequency control words at the same interval in the delay circuit, the first length difference value is a difference value between the first length information corresponding to adjacent frequency control words obtained by the difference obtaining circuit, and the delay control word is used to control the delay time of the delay circuit;
the second adjusting module 31 is configured to adjust a corresponding relationship between the frequency control word and the delay control word in an equal proportion according to the second length difference to reduce the second length difference, where the delay time storage circuit is further configured to store first length information of a delay time corresponding to a minimum frequency control word and second length information obtained by adding a clock period of an input signal of the delay circuit to the first length information of the delay time corresponding to a minimum frequency control word of the delay circuit, the second length difference is a difference between the first length information of the delay time corresponding to a maximum frequency control word obtained by the difference obtaining circuit and the second length information of the delay time corresponding to the maximum frequency control word of the delay circuit, and the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit.
Since the embodiments of the apparatus portion and the method portion correspond to each other, please refer to the description of the embodiments of the method portion for the embodiments of the apparatus portion, which is not repeated here.
The calibration apparatus for a delay circuit provided in this embodiment corresponds to the above method, and therefore has the same advantages as the above method.
Based on the hardware perspective, this embodiment provides another calibration apparatus for a delay circuit, fig. 6 is a structural diagram of the calibration apparatus for a delay circuit provided in another embodiment of the present application, and as shown in fig. 6, the calibration apparatus for a delay circuit includes: a memory 40 for storing a computer program;
a processor 41 for implementing the steps of the calibration method of the delay circuit as mentioned in the above embodiments when executing the computer program.
The calibration device of the delay circuit provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, or a desktop computer.
Processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, and so forth. The Processor 41 may be implemented in hardware using at least one of a Digital Signal Processor (DSP), a Field-Programmable Gate Array (FPGA), and a Programmable Logic Array (PLA). The processor 41 may also include a main processor and a coprocessor, where the main processor is a processor for Processing data in an awake state, and is also called a Central Processing Unit (CPU); a coprocessor is a low power processor for processing data in a standby state. In some embodiments, the processor 41 may be integrated with a Graphics Processing Unit (GPU) which is responsible for rendering and drawing the content required to be displayed on the display screen. In some embodiments, processor 41 may also include an Artificial Intelligence (AI) processor for processing computational operations related to machine learning.
Memory 40 may include one or more computer-readable storage media, which may be non-transitory. Memory 40 may also include high speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 40 is at least used for storing a computer program 401, wherein after being loaded and executed by the processor 41, the computer program can implement the relevant steps of the calibration method of the delay circuit disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 40 may also include an operating system 402, data 403, and the like, and the storage manner may be a transient storage or a permanent storage. Operating system 402 may include, among other things, Windows, Unix, Linux, and the like. The data 403 may include, but is not limited to, data related to a calibration method of the delay circuit, and the like.
In some embodiments, the calibration device of the delay circuit may further include a display 42, an input/output interface 43, a communication interface 44, a power supply 45, and a communication bus 46.
It will be appreciated by those skilled in the art that the arrangement shown in the figures does not constitute a limitation of the calibration means of the delay circuit and may comprise more or less components than those shown.
The calibration device for the delay circuit provided by the embodiment of the application comprises a memory and a processor, wherein when the processor executes a program stored in the memory, the following method can be realized: a calibration method for a delay circuit.
The calibration apparatus for a delay circuit provided in this embodiment corresponds to the above method, and therefore has the same advantages as the above method.
Finally, the application also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, carries out the steps as set forth in the above-mentioned method embodiments.
It is to be understood that if the method in the above embodiments is implemented in the form of software functional units and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially or partially implemented in the form of a software product, which is stored in a storage medium and performs all or part of the steps of the methods described in the embodiments of the present application, or all or part of the technical solution. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The computer-readable storage medium provided by the embodiment corresponds to the method, and therefore has the same beneficial effects as the method.
The calibration circuit, the calibration method, the calibration apparatus, and the medium of the delay circuit provided in the present application are described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the same element.
Claims (10)
1. A calibration circuit for a delay circuit, comprising: the delay time storage circuit, the difference value acquisition circuit and the control circuit are arranged in the circuit;
the delay time storage circuit is connected with the input end and the output end of the delay circuit and is used for storing first length information of delay time corresponding to a plurality of frequency control words with the same interval of the delay circuit and storing second length information obtained by adding the first length information of the delay time corresponding to a minimum frequency control word to a clock cycle of an input signal of the delay circuit, wherein the minimum frequency control word is the frequency control word corresponding to the minimum delay time of the delay circuit;
the difference obtaining circuit is connected to the delay time storage circuit, and is configured to receive the first length information and the second length information, obtain a first length difference between the first length information corresponding to adjacent frequency control words, and obtain a second length difference between the first length information and the second length information of the delay time corresponding to a maximum frequency control word, where the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit;
the control circuit is connected with the difference value acquisition circuit and used for adjusting the corresponding relation between the frequency control word and the delay control word according to the first length difference value so as to enable every two adjacent first length difference values to be equal, and adjusting the corresponding relation between the frequency control word and the delay control word according to the second length difference value in an equal proportion so as to reduce the second length difference value, wherein the delay control word is used for controlling the delay time of the delay circuit.
2. The calibration circuit for a delay circuit according to claim 1, wherein the delay circuit is a DTC, and the delay time storage circuit comprises: the device comprises a D trigger, a multi-channel selector, a pulse generating circuit and a charge pump circuit;
the input end of the DTC is directly connected with a first path of a first end of the multi-path check device, the input end of the DTC is also connected with a first end of the D trigger, a second path of the first end of the multi-path check device is connected with a second end of the D trigger, when the first path of the multi-path check device is selected to be switched on, the multi-path check device is used for receiving a plurality of input signals corresponding to the frequency control words at the same interval, when the second path of the multi-path check device is selected to be switched on, the check device is used for receiving the input signals corresponding to the minimum frequency control words passing through the D trigger, and the D trigger is used for adding the clock period of the input signals to the input signals corresponding to the minimum frequency control words;
the first path of the first end of the pulse generating circuit is connected with the second end of the multi-path check device, the second path of the first end of the pulse generating circuit is connected with the output end of the DTC, and the pulse generating circuit is used for converting the delay time between the input signal selected by the multi-path check device and the output signal of the DTC into pulse width;
and the first end of the charge pump circuit is connected with the second end of the pulse generation circuit and is used for converting the pulse width into a voltage value and storing the voltage value in the pulse generation circuit, wherein the voltage value is the first length information and the second length information.
3. The calibration circuit of the delay circuit according to claim 2, wherein the difference acquisition circuit is an operational amplifier;
the first end of the operational amplifier is connected to the second end of the charge pump circuit, and is configured to receive the voltage value, obtain a first voltage difference value of the voltage value corresponding to the adjacent frequency control words, and obtain a second voltage difference value between the voltage value corresponding to the maximum frequency control word and the voltage value corresponding to the minimum frequency control word after passing through the D flip-flop.
4. The calibration circuit for a delay circuit according to claim 3, wherein the control circuit comprises: a comparator, a control coding circuit;
the first path of the first end of the comparator is connected with the second end of the operational amplifier, when the first path of the first end of the comparator receives the first output voltage, the second path of the first end of the comparator inputs a first reference voltage, the comparator is used for comparing the first output voltage with the first reference voltage to obtain a first comparison result, when the first path of the first end of the comparator receives the second output voltage, the second path of the first end of the comparator inputs a second reference voltage, and the comparator is used for comparing the second output voltage with the second reference voltage to obtain a second comparison result;
the control coding circuit is connected with the second end of the comparator and used for receiving the first comparison result and the second comparison result, the control coding circuit is further connected with a frequency division control circuit and the DTC and used for receiving the frequency control word sent by the frequency division control circuit and obtaining the corresponding delay control word according to the frequency control word to control the delay time of the DTC, the control coding circuit further adjusts the corresponding relation between the frequency control word and the delay control word according to the first comparison result so as to enable the first output voltage to be equal to the first reference voltage, and the control coding circuit further adjusts the corresponding relation between the frequency control word and the delay control word according to the second comparison result so as to enable the second output voltage to be equal to the second reference voltage.
5. The calibration circuit of claim 4, wherein two capacitors are disposed inside the charge pump circuit for storing the voltage values corresponding to two adjacent frequency control words respectively so that the operational amplifier can obtain the first voltage difference; and the operational amplifier is further configured to store the voltage value corresponding to the maximum frequency control word and the voltage value corresponding to the minimum frequency control word after passing through the D flip-flop, so that the operational amplifier can obtain the second voltage difference.
6. The calibration circuit of the delay circuit according to any one of claims 2 to 5, wherein the multi-way check is a two-way check.
7. A calibration method of a delay circuit, which is applied to the delay circuit according to any one of claims 1 to 6, comprising:
adjusting a corresponding relation between a frequency control word and a delay control word according to a first length difference value so as to enable every two adjacent first length difference values to be equal, wherein the delay time storage circuit is used for storing first length information of the delay time corresponding to a plurality of frequency control words at the same interval of the delay circuit, the first length difference value is a difference value between the first length information corresponding to the adjacent frequency control words acquired by the difference acquisition circuit, and the delay control word is used for controlling the delay time of the delay circuit;
and adjusting the correspondence between the frequency control word and the delay control word in an equal proportion according to a second length difference value to reduce the second length difference value, wherein the delay time storage circuit is further configured to store first length information of the delay time corresponding to a minimum frequency control word and second length information obtained by adding a clock period of an input signal of the delay circuit, the minimum frequency control word is the frequency control word corresponding to the minimum delay time of the delay circuit, the second length difference value is a difference value between the first length information and the second length information of the delay time corresponding to a maximum frequency control word obtained by the difference value obtaining circuit, and the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit.
8. A calibration device for a delay circuit, which is applied to the delay circuit according to any one of claims 1 to 6, comprising:
a first adjusting module, configured to adjust a correspondence between a frequency control word and a delay control word according to a first length difference value, so that each two adjacent first length difference values are equal, where the delay time storage circuit is configured to store first length information of the delay time corresponding to a plurality of frequency control words at the same interval in the delay circuit, the first length difference value is a difference value between the first length information corresponding to adjacent frequency control words acquired by the difference acquisition circuit, and the delay control word is used to control the delay time of the delay circuit;
a second adjusting module for adjusting the corresponding relationship between the frequency control word and the delay control word according to a second length difference in an equal proportion to reduce the second length difference, wherein the delay time storage circuit is further configured to store first length information of the delay time corresponding to a minimum frequency control word plus second length information obtained by adding a clock period of an input signal of the delay circuit, wherein the minimum frequency control word is the frequency control word corresponding to the delay time for which the delay circuit is minimum, the second length difference is a difference between the first length information and the second length information of the delay time corresponding to the maximum frequency control word acquired by the difference acquisition circuit, wherein the maximum frequency control word is the frequency control word corresponding to the maximum delay time of the delay circuit.
9. A calibration arrangement for a delay circuit, comprising a memory for storing a computer program;
a processor for implementing the steps of the calibration method of the delay circuit as claimed in claim 7 when executing said computer program.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the steps of the calibration method of a delay circuit according to claim 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116112005A (en) * | 2022-12-30 | 2023-05-12 | 成都电科星拓科技有限公司 | Delay measurement method, equipment and storage medium of DTC delay unit |
| CN116192125A (en) * | 2022-12-31 | 2023-05-30 | 成都电科星拓科技有限公司 | Method and device for correcting DTC delay stepping based on stepping LDO |
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2022
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116112005A (en) * | 2022-12-30 | 2023-05-12 | 成都电科星拓科技有限公司 | Delay measurement method, equipment and storage medium of DTC delay unit |
| CN116112005B (en) * | 2022-12-30 | 2024-02-13 | 成都电科星拓科技有限公司 | Delay measurement method, equipment and storage medium of DTC delay unit |
| CN116192125A (en) * | 2022-12-31 | 2023-05-30 | 成都电科星拓科技有限公司 | Method and device for correcting DTC delay stepping based on stepping LDO |
| CN116192125B (en) * | 2022-12-31 | 2024-02-13 | 成都电科星拓科技有限公司 | Method and device for correcting DTC delay stepping based on stepping LDO |
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