CN112803944A - Digital time converter calibration method and device, digital phase-locked loop and electronic equipment - Google Patents
Digital time converter calibration method and device, digital phase-locked loop and electronic equipment Download PDFInfo
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- CN112803944A CN112803944A CN202011607867.5A CN202011607867A CN112803944A CN 112803944 A CN112803944 A CN 112803944A CN 202011607867 A CN202011607867 A CN 202011607867A CN 112803944 A CN112803944 A CN 112803944A
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- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
Abstract
The present invention relates to the field of digital circuit technologies, and in particular, to a method and an apparatus for calibrating a digital-to-time converter, a digital phase-locked loop, and an electronic device. According to the digital time converter calibration method, the digital time converter calibration device, the digital phase-locked loop and the electronic equipment, resolution deviation is obtained according to the fractional part of the reference phase and the fractional phase error; acquiring a gain factor according to the resolution deviation; performing gain processing on the decimal part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter; by the mode, on the basis of eliminating the noise of other devices of the digital phase-locked loop, the noise of the time-to-digital converter and the noise of the digital-to-time converter are further eliminated, and the calibration precision of the digital-to-time converter is improved; high-precision gain calibration of the digital-to-time converter is realized, and power consumption is greatly reduced.
Description
[ technical field ] A method for producing a semiconductor device
The present invention relates to the field of digital circuit technologies, and in particular, to a method and an apparatus for calibrating a digital-to-time converter, a digital phase-locked loop, and an electronic device.
[ background of the invention ]
In an All-Digital phase-locked loop (ADPLL), a Time-to-Digital Converter (TDC) is used as a fractional phase detector, quantization noise of the TDC greatly affects final phase noise performance of the ADPLL, and improving resolution of the TDC becomes an effective method for improving performance of the ADPLL; a Digital-to-Time-Converter (DTC) assisted TDC helps to reduce the power consumption of the adpll. The DTC appropriately delays the input reference clock by a time when the time difference between the delayed reference clock and the output clock of the phase locked loop is within the dynamic range of the TDC.
However, the resolution of the DTC is affected by non-idealities such as process, power supply, temperature (PVT) variation, or non-linearity, resulting in the actual amount of delay of the reference clock being different from what was expected, and thus being noise contributed by the DTC. The calibration device in the prior art does not consider noise elimination of the DTC, so that the calibration precision is low, high-precision gain calibration of the time converter cannot be realized, and the effect of reducing power consumption is poor.
[ summary of the invention ]
The invention aims to provide a method and a device for calibrating a digital time converter, a digital phase-locked loop and electronic equipment, and aims to solve the technical problems of low calibration precision and poor effect of reducing power consumption in the prior art.
The technical scheme of the invention is as follows: the digital time converter calibration method is applied to a digital phase-locked loop, wherein the digital phase-locked loop comprises a digital time converter and a time-to-digital converter, and the digital time converter is used for delaying a reference clock signal according to a delay control signal and generating a delayed reference clock signal; the time-to-digital converter is configured to generate a fractional phase error from the delayed reference clock signal and an output clock signal of a digital phase-locked loop, wherein the fractional phase error is indicative of a phase difference between the delayed reference clock signal and the output clock signal, and comprises:
respectively acquiring a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, wherein the reference phase is generated according to a reference clock signal, the reference phase is used for indicating phase information of the reference clock signal, and the reference phase comprises an integer part and a fractional part;
acquiring a resolution deviation according to the fractional part of the reference phase and the fractional phase error;
acquiring a gain factor according to the resolution deviation;
and performing gain processing on the decimal part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter.
Preferably, the obtaining a resolution deviation from the fractional part of the reference phase and the fractional phase error comprises:
filtering the fractional phase error to obtain the filtered fractional phase error;
negating the decimal part of the reference phase, and summing the negated decimal part of the reference phase and the first parameter to obtain a first calculated value;
and dividing the filtered fractional phase error by the first calculated value to obtain a resolution deviation.
Preferably, the obtaining a gain factor according to the resolution deviation includes:
multiplying the resolution deviation by a second parameter to obtain a third calculated value;
and accumulating the third calculation value to obtain the gain factor.
Preferably, the performing gain processing on the fractional part of the reference phase according to the gain factor to generate the delay control signal includes:
negating the decimal part of the reference phase, and summing the negated decimal part of the reference phase and a second parameter to obtain a second calculated value;
and dividing the second calculation value by the gain factor to obtain a third calculation value, and generating the delay control signal according to the third calculation value.
The other technical scheme of the invention is as follows: the digital time converter calibration device is applied to a digital phase-locked loop, wherein the digital phase-locked loop comprises a digital time converter and a time-to-digital converter, and the digital time converter is used for delaying a reference clock signal according to a delay control signal and generating a delayed reference clock signal; the time-to-digital converter is configured to generate a fractional phase error from the delayed reference clock signal and an output clock signal of a digital phase-locked loop, wherein the fractional phase error is indicative of a phase difference between the delayed reference clock signal and the output clock signal, the calibration apparatus comprising:
an error detection module, configured to obtain a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, respectively, and obtain a resolution deviation according to the fractional part of the reference phase and the fractional phase error, where the reference phase is generated according to a reference clock signal, the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part;
the calculation module is used for acquiring a gain factor according to the resolution deviation;
and the gain module is used for performing gain processing on the decimal part of the reference phase according to the gain factor to generate the delay control signal and outputting the delay control signal to the digital time converter.
Preferably, the error detection module includes:
the filter is used for filtering the fractional phase error to obtain the filtered fractional phase error;
the first adder is used for summing the fraction part of the inverted reference phase and the first parameter to obtain a first calculated value;
a first divider configured to divide the filtered fractional phase error by the first calculated value to obtain a resolution deviation.
Preferably, the calculation module comprises a multiplier and an accumulator, wherein,
the multiplier is used for multiplying the resolution deviation by a second parameter to obtain a third calculated value;
and the accumulator is used for accumulating the third calculation value to obtain the gain factor and outputting the gain factor.
Preferably, the gain module comprises:
the third adder is used for summing the fraction part of the inverted reference phase and the second parameter to obtain a second calculated value;
and the second divider is used for dividing the second calculation value by the gain factor to obtain a third calculation value, and outputting the third calculation value serving as the delay control signal to the digital-to-time converter.
The other technical scheme of the invention is as follows: there is provided a digital phase locked loop comprising:
the digital-to-time converter calibration apparatus described above;
a first counter for generating a reference phase from a reference clock signal, wherein the reference phase is used to indicate phase information of the reference clock signal, and the reference phase comprises an integer part and a fractional part;
a second counter for generating a variable phase from the output clock signal, wherein the variable phase is indicative of phase information of the output clock signal;
a digital-to-time converter for delaying the reference clock signal according to a delay control signal to generate a delayed reference clock signal;
a time-to-digital converter for generating a fractional phase error from the delayed reference clock signal and an output clock signal, wherein the fractional phase error is indicative of a phase difference between the delayed reference clock signal and the output clock signal;
a phase detector to generate a phase error from an integer portion of the reference phase, the fractional phase error, and the variable phase;
a digital loop filter for smoothing the phase error;
and the numerically controlled oscillator is used for generating an adjusting value of a frequency control word according to the phase error after the smoothing processing, and generating the output clock signal according to the adjusting value of the frequency control word.
The other technical scheme of the invention is as follows: there is provided an electronic device comprising a chip comprising a digital phase locked loop as described above.
The invention has the beneficial effects that: according to the digital time converter calibration method, the digital time converter calibration device, the digital phase-locked loop and the electronic equipment, resolution deviation is obtained according to the fractional part of the reference phase and the fractional phase error; acquiring a gain factor according to the resolution deviation; performing gain processing on the decimal part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter; by the mode, on the basis of eliminating the noise of other devices of the digital phase-locked loop, the noise of the time-to-digital converter and the noise of the digital-to-time converter are further eliminated, and the calibration precision of the digital-to-time converter is improved; high-precision gain calibration of the digital-to-time converter is realized, and power consumption is greatly reduced.
[ description of the drawings ]
FIG. 1 is a circuit diagram of a digital phase locked loop according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram of a digital-to-time converter calibration apparatus according to a second embodiment of the present invention;
FIG. 3 is a flowchart illustrating a method for calibrating a digital-to-time converter according to a third embodiment of the present invention;
FIG. 4 is a graph comparing phase error results for comparative and application examples of the present invention;
FIG. 5 is a graph comparing the results of gain factors for comparative and application examples of the present invention;
fig. 6 is a block diagram of an electronic device according to a fourth embodiment of the present invention.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first", "second" and "third" in the present invention are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise. All directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are only used to explain the relative positional relationship between the components, the movement, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
For ease of understanding, the digital phase locked loop provided by the present invention will first be described.
Referring to fig. 1, a digital phase-locked loop 100 according to a first embodiment of the present invention includes a first counter 21, a second counter 22, a digital-to-time converter 23, a time-to-digital converter 24, a phase detector 25, a digital loop filter 26, a digital controlled oscillator 27, and a digital-to-time converter calibration apparatus 10.
The digital phase-locked loop 100 of the present embodiment is an all-digital phase-locked loop assisted by a digital-to-time converter, and in the digital phase-locked loop 100, the digital phase-locked loop operates in a manner that the Frequency of the output clock signal CKV of the digital phase-locked loop is a preset multiplying factor of the Frequency of the reference clock signal FREF, where the preset multiplying factor is referred to as a Frequency control word FCW (Frequency command word, FCW). In this embodiment, the frequency control word FCW is not an integer but includes an integer part and a fractional part, and for example, when the frequency of the reference clock signal FREF is 100MHz, the frequency control word FCW may be set to 2.25 in order to obtain the output clock signal CKV of 225 MHz.
The first counter 21 receives a reference clock signal FREF and generates a reference phase PHR according to the reference clock signal FREF, wherein the reference phase PHR is used for indicating phase information of the reference clock signal, and the reference phase PHR includes an integer part PHRiAnd the fractional part PHRF. Specifically, the first counter 21 accumulates the first preset value according to the frequency of the reference clock signal FREF to generate the reference phase PHR.
The second counter 22 is configured to generate a variable phase PHV _ INT according to the output clock signal CKV, wherein the variable phase PHV _ INT is used to indicate phase information of the output clock signal. Specifically, the second counter 22 accumulates a second preset value according to the frequency of the output clock signal CKV to generate the variable phase PHV _ INT.
In this embodiment, the first preset value may be set as the frequency control word FCW, and the second preset value may be set as 1. That is, in this embodiment, the first counter 21 accumulates the frequency control word FCW according to the frequency of the reference clock signal FREF to generate the reference phase PHR; the second counter 22 accumulates 1 according to the frequency of the output clock signal CKV to generate the variable phase PHV _ INT.
The digital-to-time converter 23 is configured to delay the reference clock signal FREF according to the delay control signal, and generate a delayed reference clock signal.
The time-to-digital converter 24 is arranged to generate a fractional phase error PHE from the delayed reference clock signal and the output clock signal CKVFWherein the fractional phase error PHEFFor indicating a phase difference between the delayed reference clock signal and the output clock signal CKV.
The phase detector 25 is arranged to determine the integer part PHR of the reference phaseiThe fractional phase error PHEFAnd the variable phase PHV _ INT generates a phase error. Further, the phase detector 25 comprises a fourth adder that combines the integer part of the reference phase PHRiFractional phase error PHEFAnd the negation of (d) and the negation of the variable phase PHV _ INT are added to obtain the phase error.
A Digital Loop Filter (DLF)26 is used to smooth the phase error.
The Digitally Controlled Oscillator (DCO)27 is configured to generate an adjustment value of a frequency control word according to the smoothed phase error, and generate the output clock signal CKV according to the adjustment value of the frequency control word.
The digital-to-time converter calibration apparatus 10 is used for gain calibration of the digital-to-time converter 23, controlling the delay amount of the digital-to-time converter 23, changing the correspondence between the frequency control word FCW and the delay amount of the digital-to-time converter 23, and calibrating the digital-to-time converterThe device 10 receives the fractional part PHR of the reference phase output by the first counter 21FAnd fractional phase error PHE output by time-to-digital converter 24FThe digital-to-time converter calibration device 10 outputs a delay control signal DTCctrlTo said digital-to-time converter 23. The structure and operation of the digital-to-time converter calibration apparatus 10 will be described in detail with reference to the second embodiment.
Referring to fig. 2, a digital-to-time converter calibration apparatus 10 according to a second embodiment of the present invention is applied to the digital phase locked loop of the first embodiment, and the digital-to-time converter calibration apparatus 10 includes: an error detection module 11, a calculation module 12 and a gain module 13, wherein the error detection module 11 is configured to receive fractional parts PHR of the reference phases output by the first counter 21 respectivelyFAnd fractional phase error PHE output by time-to-digital converter 24FAccording to the fractional part PHR of the reference phaseFAnd the fractional phase error PHEFAcquiring a resolution deviation, and outputting the resolution deviation to the calculation module 12; the calculating module 12 is used for calculating the gain factor K according to the resolution deviation output by the error detecting module 11dtcA gain factor KdtcOutput to the gain module 13; a gain module 13 for determining a gain factor K according to the gain factor KdtcFor the fractional part PHR of the reference phase output by the first counter 21FGain processing is carried out to generate a delay control signal DTCctrlSaid delay control signal DTCctrlAnd outputting the signal to the digital-to-time converter 23 to realize gain calibration of the digital-to-time converter 23.
In an alternative embodiment, the error detection module 11 includes a filter 111, a first adder 112, and a first divider 113.
Wherein the filter 111 receives the fractional phase error PHE output by the time-to-digital converter 24FThe fractional phase error PHEFPerforming a filtering process to obtain a filtered fractional phase error, which is specifically a phase error contributed by a resolution deviation of the digital-to-time converter 23; the filter 111 is a band-pass filterThe passband frequency is centered at fr × min (FCW _ F,1-FCW _ F), and can be modified to a suitable passband frequency with different FCW _ F, so that the filter can work normally at any frequency. Since the error signal for the iterative calculation will repeatedly appear in the ADPLL at a certain frequency (first frequency) and the frequency (first frequency) will vary from one frequency control word to another, the use of the bandpass filter of the preferred embodiment can avoid the situation of the calibration algorithm not converging due to the use of the fixed frequency IIR filter.
Wherein, the first adder 112 is used to invert the decimal part PHR of the inverted reference phase and input the inverted reference phase to the first adder 112 and the gain module 13 respectivelyFAnd summing the first parameter to obtain a first calculated value. In this embodiment, the first parameter is 1, and the first calculated value is 1-PHRF。
The first divider 113 receives the filtered fractional phase error output by the filter 111 and the first calculated value output by the first adder 112, divides the filtered fractional phase error by the first calculated value to obtain a resolution deviation, and outputs the resolution deviation to the calculating module 12.
In an alternative embodiment, the calculating module 12 includes a multiplier 121 and an accumulator 122, wherein the multiplier 121 receives the resolution deviation output by the error detecting module 11, multiplies the resolution deviation by the second parameter μ to obtain a third calculated value, and outputs the third calculated value to the accumulator 122; the accumulator 122 receives the third calculated value output by the multiplier 121 and accumulates the third calculated value to obtain an accumulation result, i.e. the gain factor Kdtc. Further, the value of the second parameter μ is preferably 10-3I.e. 0.001, when the gain factor K is applied in practicedtcWhen the speed of convergence to a stable value is slow, the value of the second parameter mu can be increased; when calculating the gain factor KdtcThe value of the second parameter mu can be reduced when oscillation occurs.
In an alternative embodiment, the gain module 13 comprises a third adder 131 and a second divider 132, wherein the third adder 131 is usedIn the fractional part PHR of the reference phase to be invertedFAnd summing the second parameter to obtain a second calculated value. In this embodiment, the second parameter is 1, and the second calculated value is 1-PHRF. A second divider 132 divides the second calculated value by the gain factor KdtcObtaining a third calculated value, and using the third calculated value as the delay control signal DTCctrlAnd outputting the signal to the digital-to-time converter 23 to realize gain calibration of the digital-to-time converter 23.
The digital phase-locked loop 100 of the first embodiment and the digital time converter calibration apparatus 10 of the second embodiment of the present invention may be applied to a cellular communication system, for example, the digital phase-locked loop 100 is applied to an integrated circuit of a vehicle-mounted radar, and the digital phase-locked loop 100 provides an intrinsic electrical signal for the vehicle-mounted radar, so as to better help the integrated circuit process electrical signals received and transmitted by an antenna.
A third embodiment of the present invention provides a digital-to-time converter calibration method, which is applied to the digital phase-locked loop of the first embodiment and implemented by using the digital-to-time converter calibration apparatus 10 of the second embodiment, and fig. 3 is a flowchart illustrating the digital-to-time converter calibration method of the third embodiment of the present invention. It should be noted that the method of the present invention is not limited to the flow sequence shown in fig. 3 if the results are substantially the same. As shown in fig. 3, the digital-to-time converter calibration method includes the steps of:
s301, respectively obtaining a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, wherein the reference phase is generated according to a reference clock signal, the reference phase is used for indicating phase information of the reference clock signal, and the reference phase comprises an integer part and a fractional part.
Where the reference phase PHR is generated by the first counter 21 and the fractional phase error is generated by the time-to-digital converter 24 based on the phase difference of the delayed reference clock signal and the output clock signal CKV.
S302, obtaining resolution deviation according to the fractional part of the reference phase and the fractional phase error.
Firstly, filtering the fractional phase error to obtain the filtered fractional phase error; then, negating the decimal part of the reference phase, and summing the negated decimal part of the reference phase and the first parameter to obtain a first calculated value; then, the filtered fractional phase error is divided by the first calculated value to obtain a resolution offset.
And S303, acquiring a gain factor according to the resolution deviation.
Firstly, multiplying the resolution deviation by a second parameter to obtain a third calculated value, and inputting the third calculated value into an accumulator; then, the accumulator accumulates the third calculation value to obtain the gain factor and outputs the gain factor.
S304, performing gain processing on the decimal part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter.
Firstly, negating the decimal part of the reference phase, and summing the negated decimal part of the reference phase and a second parameter to obtain a second calculated value; then, the second calculation value is divided by the gain factor to obtain a third calculation value, and the delay control signal is generated according to the third calculation value.
It should be noted that the implementation of the digital-to-time converter calibration method according to the third embodiment of the present invention is similar to that of the digital-to-time converter calibration apparatus according to the second embodiment, so that the description is simple, and the relevant points can be referred to the partial description of the second embodiment.
Application example
By applying the digital phase-locked loop of the first embodiment of the present invention, the calibration apparatus 10 for the digital-to-time converter in the digital phase-locked loop is turned on, the reference clock signal is subjected to a predetermined multiplying factor to obtain an output clock signal and output the output clock signal, the phase error detected by the phase detector 25 in the digital phase-locked loop is monitored, and the gain factor K output by the calculation module 12 in the digital phase-locked loop is monitoreddtcThe monitoring was carried out, the results of which are shown in fig. 4 and 5.
Comparative example
By applying the digital phase-locked loop of the first embodiment of the present invention, the calibration device 10 of the digital-to-time converter in the digital phase-locked loop is turned on, the connection between the calibration device 10 of the digital-to-time converter in the digital phase-locked loop and the digital-to-time converter 23 is cut off, the reference clock signal is multiplied by a predetermined ratio to obtain the output clock signal and output the output clock signal, the phase error detected by the phase detector 25 in the digital phase-locked loop is monitored, and the gain factor K output by the calculation module 12 in the digital phase-locked loop is monitoreddtcThe monitoring was carried out, the results of which are shown in fig. 4 and 5.
In the application example, the digital-to-time converter calibration apparatus 10 performs gain calibration on the digital-to-time converter 23; in the comparative example, since the connection between the digital-to-time converter calibration apparatus 10 and the digital-to-time converter 23 is disconnected, the gain calibration is not performed on the digital-to-time converter 23. Referring to fig. 4, compared with the comparative example, the dynamic range of the phase error detected by the phase detector 25 of the application example is greatly reduced, and the power consumption of the phase detector 25 is greatly reduced. Referring to fig. 4 and 5, in the comparative example, the digital-to-time converter 23 is not gain-calibrated, the gain factor is greatly biased, resulting in a phase error distribution of [ -0.050.05 ]; in an application example, after the digital-to-time converter 23 is gain-calibrated, the gain factor may be automatically adjusted to a stable value, so that the phase error approaches 0.
Referring to fig. 6, the electronic device 40 includes a chip 41, where the chip 41 includes a digital phase-locked loop 100, and the structure, the operation mode, and the application effect of the digital phase-locked loop 100 are described in detail with reference to the first embodiment, the second embodiment, and the third embodiment.
While the foregoing is directed to embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made without departing from the spirit and scope of the invention.
Claims (10)
1. A digital time converter calibration method is applied to a digital phase-locked loop, the digital phase-locked loop comprises a digital time converter and a time-to-digital converter, and the digital time converter is used for delaying a reference clock signal according to a delay control signal and generating a delayed reference clock signal; the time-to-digital converter is configured to generate a fractional phase error from the delayed reference clock signal and an output clock signal of a digital phase-locked loop, wherein the fractional phase error is indicative of a phase difference between the delayed reference clock signal and the output clock signal, and comprises:
respectively acquiring a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, wherein the reference phase is generated according to a reference clock signal, the reference phase is used for indicating phase information of the reference clock signal, and the reference phase comprises an integer part and a fractional part;
acquiring a resolution deviation according to the fractional part of the reference phase and the fractional phase error;
acquiring a gain factor according to the resolution deviation;
and performing gain processing on the decimal part of the reference phase according to the gain factor to generate the delay control signal, and outputting the delay control signal to the digital-to-time converter.
2. The digital to time converter calibration method of claim 1, wherein said obtaining a resolution offset from said fractional part of said reference phase and said fractional phase error comprises:
filtering the fractional phase error to obtain the filtered fractional phase error;
negating the decimal part of the reference phase, and summing the negated decimal part of the reference phase and the first parameter to obtain a first calculated value;
and dividing the filtered fractional phase error by the first calculated value to obtain a resolution deviation.
3. The digital to time converter calibration method of claim 1 or 2, wherein said obtaining a gain factor based on said resolution offset comprises:
multiplying the resolution deviation by a second parameter to obtain a third calculated value;
and accumulating the third calculation value to obtain the gain factor.
4. The digital to time converter calibration method of claim 3, wherein said gain processing the fractional part of the reference phase according to the gain factor to generate the delay control signal comprises:
negating the decimal part of the reference phase, and summing the negated decimal part of the reference phase and a second parameter to obtain a second calculated value;
and dividing the second calculation value by the gain factor to obtain a third calculation value, and generating the delay control signal according to the third calculation value.
5. A digital time converter calibration device is applied to a digital phase-locked loop, wherein the digital phase-locked loop comprises a digital time converter and a time-to-digital converter, and the digital time converter is used for delaying a reference clock signal according to a delay control signal and generating a delayed reference clock signal; the time-to-digital converter is configured to generate a fractional phase error from the delayed reference clock signal and an output clock signal of a digital phase-locked loop, wherein the fractional phase error is indicative of a phase difference between the delayed reference clock signal and the output clock signal, and the calibration apparatus comprises:
an error detection module, configured to obtain a fractional part of a reference phase and the fractional phase error output by the time-to-digital converter, respectively, and obtain a resolution deviation according to the fractional part of the reference phase and the fractional phase error, where the reference phase is generated according to a reference clock signal, the reference phase is used to indicate phase information of the reference clock signal, and the reference phase includes an integer part and a fractional part;
the calculation module is used for acquiring a gain factor according to the resolution deviation;
and the gain module is used for performing gain processing on the decimal part of the reference phase according to the gain factor to generate the delay control signal and outputting the delay control signal to the digital time converter.
6. The digital to time converter calibration apparatus of claim 5, wherein said error detection module comprises:
the filter is used for filtering the fractional phase error to obtain the filtered fractional phase error;
the first adder is used for summing the fraction part of the inverted reference phase and the first parameter to obtain a first calculated value;
a first divider configured to divide the filtered fractional phase error by the first calculated value to obtain a resolution deviation.
7. The digital to time converter calibration apparatus of claim 5, wherein said calculation module comprises a multiplier and an accumulator, wherein,
the multiplier is used for multiplying the resolution deviation by a second parameter to obtain a third calculated value;
and the accumulator is used for accumulating the third calculation value to obtain the gain factor and outputting the gain factor.
8. The digital to time converter calibration apparatus of claim 5, wherein the gain module comprises:
the third adder is used for summing the fraction part of the inverted reference phase and the second parameter to obtain a second calculated value;
and the second divider is used for dividing the second calculation value by the gain factor to obtain a third calculation value, and outputting the third calculation value serving as the delay control signal to the digital-to-time converter.
9. A digital phase locked loop, comprising:
a digital to time converter calibration apparatus as claimed in any one of claims 5 to 8;
a first counter for generating a reference phase from a reference clock signal, wherein the reference phase is used to indicate phase information of the reference clock signal, and the reference phase comprises an integer part and a fractional part;
a second counter for generating a variable phase from the output clock signal, wherein the variable phase is indicative of phase information of the output clock signal;
a digital-to-time converter for delaying the reference clock signal according to a delay control signal to generate a delayed reference clock signal;
a time-to-digital converter for generating a fractional phase error from the delayed reference clock signal and an output clock signal, wherein the fractional phase error is indicative of a phase difference between the delayed reference clock signal and the output clock signal;
a phase detector to generate a phase error from an integer portion of the reference phase, the fractional phase error, and the variable phase;
a digital loop filter for smoothing the phase error;
and the numerically controlled oscillator is used for generating an adjusting value of a frequency control word according to the phase error after the smoothing processing, and generating the output clock signal according to the adjusting value of the frequency control word.
10. An electronic device, characterized in that it comprises a chip comprising the digital phase locked loop according to claim 9.
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| CN202011607867.5A CN112803944A (en) | 2020-12-30 | 2020-12-30 | Digital time converter calibration method and device, digital phase-locked loop and electronic equipment |
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| CN114710154A (en) * | 2022-06-07 | 2022-07-05 | 绍兴圆方半导体有限公司 | Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration |
| CN114967409A (en) * | 2022-03-28 | 2022-08-30 | 中山大学 | High-precision time-to-digital converter resisting PVT change and implementation method thereof |
| CN115343937A (en) * | 2022-08-19 | 2022-11-15 | 苏州聚元微电子股份有限公司 | Calibration method of time-to-digital converter applied to digital phase-locked loop |
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| CN116192125A (en) * | 2022-12-31 | 2023-05-30 | 成都电科星拓科技有限公司 | Method and device for correcting DTC delay stepping based on stepping LDO |
| CN117092444A (en) * | 2023-10-19 | 2023-11-21 | 成都电科星拓科技有限公司 | Method, system, equipment and medium for indirectly measuring DTC stepping without depending on instrument |
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| WO2023051291A1 (en) * | 2021-09-28 | 2023-04-06 | 中兴通讯股份有限公司 | Linearity calibration method and apparatus for dtc, and digital phase lock loop |
| CN114967409A (en) * | 2022-03-28 | 2022-08-30 | 中山大学 | High-precision time-to-digital converter resisting PVT change and implementation method thereof |
| CN114710154A (en) * | 2022-06-07 | 2022-07-05 | 绍兴圆方半导体有限公司 | Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration |
| CN115421367A (en) * | 2022-08-10 | 2022-12-02 | 麦斯塔微电子(深圳)有限公司 | Calibration method and system |
| CN115421367B (en) * | 2022-08-10 | 2024-02-27 | 麦斯塔微电子(深圳)有限公司 | Calibration method and system |
| CN115343937A (en) * | 2022-08-19 | 2022-11-15 | 苏州聚元微电子股份有限公司 | Calibration method of time-to-digital converter applied to digital phase-locked loop |
| CN115343937B (en) * | 2022-08-19 | 2023-09-01 | 苏州聚元微电子股份有限公司 | Calibration method of time-to-digital converter applied to digital phase-locked loop |
| CN116192125A (en) * | 2022-12-31 | 2023-05-30 | 成都电科星拓科技有限公司 | Method and device for correcting DTC delay stepping based on stepping LDO |
| CN116192125B (en) * | 2022-12-31 | 2024-02-13 | 成都电科星拓科技有限公司 | Method and device for correcting DTC delay stepping based on stepping LDO |
| CN117092444A (en) * | 2023-10-19 | 2023-11-21 | 成都电科星拓科技有限公司 | Method, system, equipment and medium for indirectly measuring DTC stepping without depending on instrument |
| CN117092444B (en) * | 2023-10-19 | 2023-12-29 | 成都电科星拓科技有限公司 | Method, system, equipment and medium for indirectly measuring DTC stepping without depending on instrument |
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