CN114710154A - Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration - Google Patents

Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration Download PDF

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Publication number
CN114710154A
CN114710154A CN202210632259.2A CN202210632259A CN114710154A CN 114710154 A CN114710154 A CN 114710154A CN 202210632259 A CN202210632259 A CN 202210632259A CN 114710154 A CN114710154 A CN 114710154A
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delay
clock
module
gain
digital
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CN114710154B (en
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史明甫
许长喜
杨锦城
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Shaoxing Yuanfang Semiconductor Co Ltd
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Shaoxing Yuanfang Semiconductor Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error

Abstract

The embodiment of the invention relates to the field of electronic circuits, and discloses an open-loop fractional frequency divider and a clock system based on time division multiplexing gain calibration. The method comprises the steps of utilizing a first gain adjustment quantity or a second gain adjustment quantity generated by the phase difference of two rising edges in a calibratable rising edge pair extracted from a first delay clock and a second delay clock, calibrating the delay gain of a first delay frequency division module by utilizing the first gain adjustment quantity to enable the delay gain to be equivalent to the difference of fixed delay time between the first delay frequency division module and the second delay frequency division module, then adding a period delay of an input clock on a delay path of the first delay frequency division module, and calibrating the delay gain of the second delay frequency division module by adjusting the second gain adjustment quantity to enable the delay gain to approach the period of the input clock, namely a target gain. The gain of the DTC does not need to be changed according to the change of the PVT, so that the design difficulty of the open-loop fractional frequency divider is greatly reduced.

Description

Open-loop fractional frequency divider and clock system based on time division multiplexing gain calibration
Technical Field
The embodiment of the invention relates to the field of electronic circuits, in particular to an open-loop fractional frequency divider and a clock system based on time division multiplexing gain calibration.
Background
In many applications, a compact, low-power, low-jitter, multi-fractional output frequency clock system is required, and a conventional solution of such a clock system is implemented by using a plurality of fractional Phase-Locked loops (PLLs), but the solution consumes a large amount of power and chip area.
One solution to low power consumption and low cost is to use an open-loop fractional divider, so that one integer PLL can be connected to multiple open-loop fractional dividers to support multiple fractional clocks. A general open-loop fractional frequency Divider structure based on a Digital-to-Time Converter is mainly composed of a Multi-Modulus Divider (MMD), a Digital-to-Time Converter (DTC), and a Δ Σ modulator, as shown in fig. 1, where the Δ Σ modulator controls the MMD to switch between N/N +1 division ratios, so that the average division ratio of the output clock of the MMD is N + α (N is an integer division coefficient, and α is a fractional division coefficient). However, the output clock jitter of MMD is large and the quantization noise term e of the delta-sigma modulator is necessaryqThe DTC is controlled to eliminate the jitter, but the gain of the DTC is severely changed along with Process, Voltage and Temperature (PVT), so that the gain of the DTC needs to be adjusted in real time according to the change of the PVT in the existing structure, and the gain of the DTC needs to be changed according to the change of the PVT, thereby increasing the design difficulty.
Disclosure of Invention
An object of an embodiment of the present invention is to provide an open-loop fractional frequency divider and a clock system based on time division multiplexing gain calibration, which are used to solve the problem of great design difficulty caused by the fact that the gain of a DTC in the existing open-loop fractional frequency divider structure needs to be changed according to the change of PVT.
To solve the above technical problem, an embodiment of the present invention provides an open-loop fractional frequency divider based on time division multiplexing gain calibration, including: the device comprises a modulation module, a multi-mode frequency divider, a first delay frequency dividing module, a second delay frequency dividing module and a gain calibration module;
the modulation module is used for generating an output bit and a quantization error according to the decimal frequency division coefficient and generating a frequency division control signal by adding the output bit and the integer frequency division coefficient;
the multi-mode frequency divider is connected with the output end of the modulation module and used for switching between N/N +1 frequency division ratios according to the frequency division control signal and dividing an input clock to output a multi-mode frequency division clock;
the first delay frequency division module is connected with the output end of the multi-mode frequency divider and used for delaying the multi-mode frequency division clock to generate a first delay clock and dividing the frequency of the first delay clock to generate a first frequency division clock;
the second delay frequency division module is connected with the output end of the modulation module and the output end of the multi-mode frequency divider, and is used for delaying the multi-mode frequency division clock according to the quantization error to generate a second delay clock and dividing the second delay clock to generate a second frequency division clock;
the gain calibration module is connected with the output end of the first delay frequency division module and the output end of the second delay frequency division module, and is used for extracting a calibratable rising edge pair corresponding to the rising edge of the same multi-mode frequency division clock from the first delay clock and the second delay clock, and generating a first gain adjustment amount or a second gain adjustment amount according to the phase difference of two rising edges in the rising edge pair;
the first gain adjustment amount is used for calibrating the delay gain of the first delay division module under the condition that the quantization error is set to be a fixed value 0 and the multi-modulus frequency division clock respectively enters the first delay division module and the second delay division module without delay difference so as to lead the total delay time from the multi-modulus frequency division clock to the formation of the rising edge pair to be the same;
the second gain adjustment amount is used for calibrating the delay gain of the second delay-and-divide module so that the total delay time from the multi-modulus frequency-division clock to the formation of the rising edge pair is the same when the quantization error is set to be a fixed value of 1 and the entry of the multi-modulus frequency-division clock into the first delay-and-divide module is delayed by one period of the input clock compared with the entry of the multi-modulus frequency-division clock into the second delay-and-divide module;
and N is the integer frequency division coefficient and is a positive integer greater than or equal to 1.
Embodiments of the present invention also provide a clock system, which includes the above-described open-loop fractional frequency divider based on time division multiplexing gain calibration.
Compared with the related art, the embodiment of the invention generates the output bit and the quantization error according to the decimal frequency division coefficient through the modulation module, and generates the frequency division control signal by adding the output bit and the integer frequency division coefficient; the multi-mode frequency divider switches between N/N +1 frequency division ratios according to the frequency division control signal and divides the frequency of the input clock to output a multi-mode frequency division clock; the first delay frequency division module delays the multi-mode frequency division clock to generate a first delay clock, and divides the frequency of the first delay clock to generate a first frequency division clock; the second delay frequency division module delays the multi-mode frequency division clock according to the quantization error to generate a second delay clock, and divides the frequency of the second delay clock to generate a second frequency division clock; the gain calibration module extracts a calibratable rising edge pair corresponding to the rising edge of the same multi-modulus frequency division clock from the first delay clock and the second delay clock, and generates a first gain adjustment amount or a second gain adjustment amount according to the phase difference of two rising edges in the rising edge pair; wherein the first gain adjustment amount is used for calibrating the delay gain of the first delay division module under the condition that the quantization error is set to be a fixed value 0 and the multi-mode frequency division clock respectively enters the first delay division module and the second delay division module without delay difference, so that the total delay time from the multi-mode frequency division clock to the formation of the rising edge pair is the same; and a second gain adjustment amount for calibrating the delay gain of the second delay-and-divide block so that the total delay time from the multi-modulus divider clock to the rising edge pair is the same, in a case where the quantization error is set to a fixed value of 1 and the entry of the multi-modulus divider clock into the first delay-and-divide block is delayed by one period of the input clock compared to the entry into the second delay-and-divide block. According to the scheme, a first gain adjustment quantity or a second gain adjustment quantity generated by the phase difference of two rising edges in a calibratable rising edge pair extracted from a first delay clock and a second delay clock is used, the first gain adjustment quantity is used for calibrating the delay gain of a first delay frequency division module to enable the delay gain to be equivalent to the difference of fixed delay time between the first delay frequency division module and a second delay frequency division module, then, a period delay of an input clock is added to a delay path of the first delay frequency division module, and the second gain adjustment quantity is adjusted to calibrate the delay gain of the second delay frequency division module to enable the delay gain to approach the period of the input clock, namely the target gain. The gain of the DTC does not need to be changed according to the change of the PVT, so that the design difficulty of the open-loop fractional frequency divider is greatly reduced.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic diagram of an open-loop fractional divider architecture in the prior art;
FIG. 2 is a block diagram of an open-loop fractional divider based on time division multiplexed gain calibration according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a delta-sigma modulator in a modulation module according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a delay section of a digital-to-time converter according to an embodiment of the present invention;
FIG. 5 is a timing diagram of time-multiplexed phase detection according to an embodiment of the invention;
FIG. 6 is a block diagram of a first divide-by-two module and a second divide-by-two module according to an embodiment of the present invention;
fig. 7a is a block diagram of a phase detector according to an embodiment of the present invention;
fig. 7b is a block diagram of a phase detector according to an embodiment of the present invention;
FIG. 8 is a circuit configuration diagram of a second logic separation block according to an embodiment of the present invention;
FIG. 9 is a flow chart of the operation of a digital calibration module according to an embodiment of the present invention;
FIG. 10 is a block diagram of a digital-to-analog converter and a linear regulator according to an embodiment of the present invention;
fig. 11 is a structural diagram of a multiplier according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
One embodiment of the present invention relates to an open-loop fractional frequency divider based on time division multiplexing gain calibration, as shown in fig. 2, the open-loop fractional frequency divider based on time division multiplexing gain calibration includes: the device comprises a modulation module 1, a multi-modulus frequency divider 2, a first delay frequency dividing module 3, a second delay frequency dividing module 4 and a gain calibration module 5.
The modulation module 1 is used for generating an output bit Y and a quantization error e according to the fractional frequency division coefficient alphaqAnd generates a frequency division control signal N + Y by adding the output bit Y to an integer frequency division coefficient N.
Specifically, the modulation module 1 may include: a delta-sigma modulator 11 and a first adder 12; the input terminal of the delta-sigma modulator 11 is connected to the fractional division coefficient α, the first output terminal generates the output bit Y (i.e., delta-sigma out), and the second output terminal generates the quantization error eq(ii) a A first input terminal of the first adder 12 is connected to the integer frequency division coefficient N, a second input terminal is connected to a first output terminal of the delta-sigma modulator 11 to be connected to the output bit Y, and an output terminal generates the frequency division control signal NF.
More particularly, as shown in FIG. 3As shown, the delta-sigma modulator 11 may be a first order delta-sigma modulator; the first-order delta-sigma modulator can comprise an adder and a digital integrator, wherein the first input end of the adder is connected with a fractional frequency division coefficient alpha, the second input end of the adder is connected with the highest bit output by the digital integrator, and the output end of the adder is connected with the input end of the digital integrator; the Most Significant Bit (MSB) of the digital integrator output is taken as the output bit Y (i.e., Δ Σ out), and the remaining low bits (LSB) are taken as the quantization error eq。
In practical applications, the driving clock of the Δ Σ modulator 11 can be provided by the output clock of the multi-modulus divider 2, and the fractional division coefficient α can be determined by an M-bit input control code, where if the data bit width of the input control code is 12 bits and the size is 1024, the fractional division coefficient α =1024/4096, the data bit width of the output bit Y is 1bit, and the quantization error e isqThe data bit width of (a) is consistent with the data bit width of the fractional division coefficient alpha.
In this embodiment, the adder subtracts the decimal frequency division coefficient α from the most significant bit MSB output by the digital integrator, and adds the subtracted result by the digital integrator to obtain a final output; the most significant bit of the output is the output bit Y, and the other lower bits are the quantization error eq. When the output bit Y is "0", the result obtained by adding the integer frequency division coefficient N to the output bit Y is N, that is, the frequency division control signal NF generated by the modulation module 1 is N, so as to control the frequency division ratio of the multi-mode frequency divider 2 to be N, and when the output bit Y is "1", the result obtained by adding the output bit Y to the integer frequency division coefficient N is N +1, that is, the frequency division control signal NF generated by the modulation module 1 is N +1, so as to control the frequency division ratio of the multi-mode frequency divider 2 to be N + 1.
The multi-mode frequency divider 2 is connected with the output end of the modulation module 1, and is used for switching between N/N +1 frequency division ratios according to the frequency division control signal, and dividing the frequency of the input clock ck _ in to output the multi-mode frequency division clock ck _ mmd. Wherein, N is an integer frequency division coefficient and is a positive integer greater than or equal to 1.
Specifically, the multi-modulus frequency divider 2 may be formed by cascading N programmable divide-by-2/divide-by-3 frequency dividers.
In this embodiment, when the frequency division control signal NF output by the modulation module 1 is N, the frequency division ratio of the multi-mode frequency divider 2 is N; and when the frequency division control signal NF output by the modulation module 1 is N +1, the frequency division ratio of the multi-modulus frequency divider 2 is N + 1.
The first delay frequency division module 3 is connected to the output end of the frequency division module 2, and is configured to delay the multi-modulus frequency division clock ck _ mmd, generate a first delay clock cko _ dtcof, and divide the first delay clock cko _ dtcof, so as to generate a first frequency division clock ck _ dummy.
As shown in fig. 2, the first delay-and-divide module 3 includes a first digital-to-time converter 31 and a first post-divider 32.
The first digital-to-time converter 31 is connected to the output of the multi-modulus divider 2, and is configured to delay the multi-modulus divided clock ck _ mmd to generate a first delayed clock cko _ dtcof.
Specifically, the first digital-to-time converter 31 may be formed by cascading a plurality of delay units. As shown in fig. 4, each delay unit may include a PMOS transistor MP, an NMOS transistor MN, and an adjustable capacitor C. The gate end of the PMOS tube MP is connected with the gate end of the NMOS tube MN and is connected with a clock to be input (such as the multi-mode frequency division clock ck _ mmd), the source end of the PMOS tube MP is connected with working voltage, the drain end of the PMOS tube MP is connected with the drain end of the NMOS tube MN and one end of the adjustable capacitor C, the source end of the NMOS tube MN is grounded, and the other end of the adjustable capacitor C is grounded.
In practical applications, the first digital-to-time converter 31 may also be implemented by other structures, which has no substantial effect on the embodiment. In this embodiment, the delay time of the corresponding first digital-to-time converter 31 is adjusted by adjusting the capacitance value of the corresponding adjustable capacitor C through the corresponding control code, so as to implement delay control on the clock to be input.
The first post-divider 32 is connected to the output of the first digital-to-time converter 31, and is configured to divide the first delayed clock cko _ DTCoff to generate a first divided clock ck _ dummy.
In particular, the division ratio of the first post-divider 32 determines the state and operating speed of the subsequent gain calibration module 5, and may be determined according to a specific algorithm of time division multiplexing. The division ratio here may be selected from divide-by-two, divide-by-four, divide-by-eight, and the like.
A second delay frequency division module 4 connected with the output end of the modulation module 1 and the output end of the multi-mode frequency divider 2 and used for determining the quantization error eqThe multi-modulus divided clock ck _ mmd is delayed to generate a second delayed clock cko _ DTCm, and the second delayed clock cko _ DTCm is divided to generate a second divided clock (also an output clock ck _ out).
As shown in fig. 2, the second delay-and-divide module 4 includes a second digital-to-time converter 41 and a second post-divider 42.
A second digital-to-time converter 41 connected between the output of the modulation module 1 and the output of the multi-modulus divider 2 and adapted to determine the quantization error eqThe multi-modulus divided clock is delayed to generate a second delayed clock cko _ DTCm.
Specifically, the second digital-to-time converter 41 may be formed by cascading a plurality of delay units. Each delay unit may also include a PMOS transistor MP, an NMOS transistor MN, and an adjustable capacitor C as shown in fig. 4, which are not described herein again.
The second post-divider 42 is connected to the output of the second digital-to-time converter 41, and is configured to divide the second delayed clock cko _ DTCm to generate a second divided clock, i.e., an output clock ck _ out.
Specifically, the dividing ratio of the second post-divider 42 is determined according to the frequency of the output clock ck _ out required by the specific application. The division ratio here may be selected from divide-by-two, divide-by-four, divide-by-eight, and the like. It should be noted that the division ratio of the second post-divider 42 is the same as that of the first post-divider 32 by default, so that the same multi-modulus division clock ck _ mmd is divided by the same division ratio to generate divided clock signals having the same clock cycle.
The Gain calibration module 5 is connected to the output of the first delay-and-divide module 3 and the output of the second delay-and-divide module 4, and is configured to extract a pair of calibratable rising edges (ck _ ref and ck _ fb) corresponding to a rising edge of the same multi-modulus divided clock ck _ mmd from the first delay clock cko _ dtcof and the second delay clock cko _ DTCm, and generate a first Gain adjustment dtcof _ Gain _ out or a second Gain adjustment DTCm _ Gain _ out according to a phase difference between two rising edges in the pair of rising edges.
Wherein a first Gain adjustment DTCOff _ Gain _ out is used for the quantization error eqSet to a fixed value of 0, the multi-modulus divided clock ck _ mmd calibrates the delay gain of the first delay-dividing block 3 so that the total delay time from the multi-modulus divided clock ck _ mmd to the formation of the pair of rising edges (ck _ ref and ck _ fb) is the same, without delay difference entering the first delay-dividing block 3 and the second delay-dividing block 4, respectively.
A second Gain adjustment DTCOff _ Gain _ out for the quantization error eqSet to a fixed value of 1, the delay gain of the second delay-and-divide block 3 is calibrated so that the total delay time from the multi-modulus divided clock ck _ mmd to the formation of the rising edge pair is the same in the case where the entry of the multi-modulus divided clock ck _ mmd into the first delay-and-divide block 3 is delayed by one cycle of the input clock compared to the entry into the second delay-and-divide block 4.
To facilitate understanding of the generation process of the Gain adjustment amount in the present embodiment, the following description will be made regarding the relationship between the phase difference of the output clocks of the first digital-to-time converter 31 and the second digital-to-time converter 41 and the first Gain adjustment amount dtcof _ Gain _ out and the second Gain adjustment amount DTCm _ Gain _ out. Fig. 5 is a timing diagram of the time-division multiplexing phase detection. In fig. 5, the clock signals are generated by the multi-modulus divider 2 with an integer division factor N =4 and the first post-divider 32 and the second post-divider 42 with a division ratio of a quarter-division. Wherein, the kth rising edge and the falling edge of the output clock ck _ out (i.e. the second divided clock) are synchronized with the 4k and 4k +2 rising edges of cko _ DTCm, respectively. Then, the 4k +1 th and 4k +3 th rising edges of cko _ DTCm do not affect every rising or falling edge of the output clock ck _ out, wherever located. Therefore, the present embodiment performs time-sharing adjustment of the first Gain adjustment amount dtcof _ Gain _ out of the first digital time converter 31 (dtcof) and the second Gain adjustment amount DTCm _ Gain _ out of the second digital time converter 41 (DTCm) at the 4k +1 or 4k +3 th rising edge of the cko _ DTCm to achieve calibration of the delay gains of dtcof and DTCm.
Gain calibration for DTCoff: when the Gain control word (DTCm _ code) of the second digital-to-time converter 41 (DTCm) is 0, that is, DTCm has only a fixed delay time, the multi-mode frequency-divided clock ck _ mmd is directly switched in to the input terminals of the first digital-to-time converter 31 and the second digital-to-time converter 41, and at the 4k +1 or 4k +3 rising edge of cko _ DTCm, the first Gain adjustment amount dtcofoff _ Gain _ out of dtcof is adjusted, and then the Gain of DTCoff is adjusted until the delay times from the same multi-mode frequency-divided clock ck _ mmd to the generation of the two frequency-divided clocks output by the first post-divider 32 and the second post-divider 42, respectively, are the same, that is, the detuning and the mismatch between the two frequency-divided clock signals are eliminated.
Gain calibration of DTCm: when the Gain control word (DTCm _ code) of the second digital-to-time converter 41 (DTCm) is an actual Gain value (Gain), i.e., the quantization error DTCm _ in =1, the multi-modulus division clock ck _ mmd is directly coupled to the input of the second digital-to-time converter 41, and the multi-modulus division clock ck _ mmd delayed by one cycle of the input clock ck _ in is coupled to the input of the first digital-to-time converter 31. Thus, theoretically, only one cycle of the input clock ck _ in will be different between the delay times experienced from the same multi-modulus divided clock ck _ mmd to the generation of the two divided clocks output by the first post-divider 32 and the second post-divider 42, respectively, after the gain calibration for dtcofoff is completed. At this time, at the 4k +1 th or 4k +3 th rising edge of cko _ DTCm, the second Gain adjustment amount DTCm _ Gain _ out of DTCm is adjusted, and thus the Gain of DTCm is adjusted until the delay times from the same multi-modulus divided clock ck _ mmd to the generation of the two divided clocks output by the first post-divider 32 and the second post-divider 42, respectively, are the same, i.e., the Gain of DTCm is made equal to the period Tin of the input clock ck _ in.
In actual operation, the gain calibration of DTCoff and the gain calibration of DTCm can be performed alternately without affecting the phase of the output clock ck _ out, which can resist DTCm from temperature drift, voltage drift, misalignment, mismatch, and other factors.
The gain calibration process described above is equally applicable to other division ratios for first post-divider 32 and second post-divider 42, as long as a calibratable rising edge is selected in principle. For the case of divide-by-two, the rising edge of cko _ DTCm that produces the falling edge of the output clock can also be selected for gain adjustment if there is no special requirement for the falling edge of the output clock.
In addition, in some other application scenarios, the dividing ratio P1 of the first frequency divider back 32 and the dividing ratio P2 of the second frequency divider back 42 may also be different, as long as it is ensured that P1 and P2 are in even-numbered multiple relation, for example, P1 may be even-numbered multiple of P2, or P2 is even-numbered multiple of P1.
For example, P2=8, P1=4, then the rising and falling edges of ck _ out correspond to the uncorrectable rising edges of 8k and 8k +4, respectively, of cko _ DTCm; through phase selection, a 4k +1 position can be selected as a calibratable rising edge; the rising and falling edges of ck _ dummy correspond to the rising edges of 4k and 4k +2 of cko _ DTCOff, respectively; through phase selection, the 4k +1 position can be selected as a calibratable rising edge.
Based on this, the Gain calibration module 5 of this embodiment extracts a calibratable rising edge pair corresponding to the rising edge of the same multi-modulus frequency-division clock ck _ mmd from the first delay clock cko _ dtcof and the second delay clock cko _ DTCm under different specified states, generates a first Gain adjustment amount DTCoff _ Gain _ out or a second Gain adjustment amount DTCm _ Gain _ out according to the phase difference between two rising edges in the multiple sets of rising edge pairs, and alternately adjusts the delay gains in the corresponding first delay frequency-division module 3 and the corresponding second delay frequency-division module 4, so that the final delay Gain of the second delay frequency-division module 4 approaches the period Tin of the input clock ck _ in, thereby making the output clock ck _ out (i.e., the second frequency-division clock) meet the requirement.
Specifically, as shown in fig. 2, the gain calibration module 5 may include: a first phase selection block 51, a second phase selection block 52, a phase detector 53 and a digital calibration block 54.
The first phase selection module 51 is coupled to the output of the first digital-to-time converter 31 and the output of the first post divider 32 for extracting a calibratable first rising edge ck _ ref from the first delayed clock.
A second phase selection block 52 connected to the output of the second digital-to-time converter 41 and the output of the second post-divider 42 for extracting a calibratable second rising edge ck _ fb from the second delayed clock; a pair of rising edges is formed corresponding to a calibratable first rising edge and a calibratable second rising edge of a same multi-modulus clock rising edge.
Specifically, as shown in fig. 6, the first phase selection module 51 and the second phase selection module 52 are both D flip-flops.
The D flip-flop DFF3 of the first phase selection module 51 has a clock terminal CLK connected to the output terminal of the first digital-to-time converter 31 (switch in cko _ dtcof), a D terminal connected to the output terminal of the first post divider 32 (switch in ck _ dummy), and a Q terminal for generating the first rising edge ck _ ref.
As the D flip-flop DFF4 of the second phase selection module 52, the clock terminal CLK is connected to the output terminal (switched in cko _ DTCm) of the second digital-to-time converter 41, the D terminal is connected to the output terminal (switched in ck _ out) of the second post divider 42, and the Q terminal is used for generating the second rising edge ck _ fb. A first calibratable rising edge and a second calibratable rising edge corresponding to the same rising edge of the multi-divided clock form a rising edge pair, namely, a pair ck _ ref and a pair ck _ fb.
Since the above DFFs 3 and 4 are clocked by cko _ dtcof and cko _ DTCm, respectively, the selected first and second calibratable rising edges are the next rising edge of the rising edge in cko _ DTCm corresponding to the kth and falling edges of the output clock (i.e., the second divided clock) ck _ out. For example, in FIG. 5, the selected calibratable first rising edge and the calibratable second rising edge are both 4k +1 and 4k +3 rising edges in cko _ DTCM.
In practical operation, when the division ratio of the first post-divider 32 and the second post-divider 42 is 4, then:
half of the rising edges in cko _ DTCm are "calibratable rising edges," such as the 2 nd, 4 th, 6 th, 8 th, … th rising edges shown in the waveform diagram in fig. 5; 1, 5, 9, …, etc. "uncorrectable rising edge" is used to generate the rising edge of ck _ out; the 3 rd, 7 th, 11 th, … th, etc. "uncorrectable rising edge" is used to generate the falling edge of ck _ out.
When the division ratio of the first post-divider 32 and the second post-divider 42 is 8, then:
referring now to FIG. 5 for comparison, most rising edges in cko _ DTCM are "calibratable rising edges", e.g., rising edges 2, 3, 4, 6, 7, 8, 10, 11, 12, 14, 15, 16, 18, …, etc.; 1, 9, 17, …, etc. "uncorrectable rising edge" is used to generate the rising edge of ck _ out; the "uncorrectable rising edge" of 5 th, 13 th, 21 th, … th, etc. is used to generate the falling edge of ck _ out.
When the division ratio of the first post-divider 32 and the second post-divider 42 is 2, then:
the comparison reference cko _ DTCm in fig. 5 does not have a "calibratable rising edge". 1, 3, 5, …, etc. "uncorrectable rising edge" is used to generate the rising edge of ck _ out; 2, 4, 6, …, etc. "uncorrectable rising edge" is used to generate the falling edge of ck _ out; however, in some application scenarios, if the falling edge of ck _ out is not required, the 2 nd, 4 th, 6 th, … th of cko _ DTCM can be treated as a "calibratable rising edge".
The phase detector 53 is connected to the output end of the first phase selection module 51 and the output end of the second phase selection module 52, and is configured to compare the phases of the first rising edge ck _ ref and the second rising edge ck _ fb in the pair of rising edges (ck _ ref and ck _ fb) to generate a comparison value COMP.
Specifically, the phase detector 53 is a bang-bang phase detector (BBPD).
This example lists the structure of a conventional BBPD constructed based on D flip-flops (fig. 7 a), and the structure of a BBPD with digital-to-time converter (fig. 7 b).
The digital calibration block 54 is connected to the output of the phase detector 53 for quantifying the error eqSet to a fixed value of 0, the multi-modulus divider clock generates a first Gain adjustment amount dtcof _ Gain _ out according to the comparison value COMP when no delay difference enters the first delay divider module 3 and the second delay divider module 4, respectively, and calibrates the delay Gain of the first digital-to-time converter 31 according to the first Gain adjustment amount so that the average value of the comparison values repeats; alternatively, when the quantization error is set to a fixed value of 1, the multi-modulus division clock entersWhen the first delay/divide module 3 delays the input of the second delay/divide module 4 by one cycle of the input clock, the second Gain adjustment amount DTCm _ Gain _ out is generated according to the comparison value COMP, and the delay Gain of the second digital-to-time converter 41 is calibrated according to the second Gain adjustment amount so that the average value of the comparison value is repeated.
Specifically, the first digital-to-time converter 31: (DTCm) The linear model of delay time of (1) is:
t dtcm = t dtcm,0+dtcm_in·△ dtcm ………………………（1）
wherein, the first and the second end of the pipe are connected with each other, t dtcm,0is composed ofDTCmA fixed delay time of dtcm _ in.Δ dtcm Is composed ofDTCmIs determined by the quantization error dtcm _ in andDTCminner unit delay time Δ of dtcm And (6) determining.
Second digital-to-time converter 41: (DTCoff) The linear model of delay time of (1) is:
t dtcoff = t dtcoff,0+dtcoff_in·△ dtcoff ………………………（2）
wherein the content of the first and second substances, t dtcoff,0is composed ofDTCoffA fixed delay time of dtcoff _ in.delta dtcoff Is composed ofDTCoffBy the quantization error dtcoff _ in andDTCoffinner unit delay time Δ of dtcoff And (6) determining.
At quantization error eqThat is, DTCm _ in is set to a fixed value of 0, and the rising edge positions of the two input clocks of the edge drop phase detector 53 (BBPD) at the correctable rising edge of cko _ DTCm, that is, the position corresponding to ck _ ref in the rising edge pair, are the positions of the rising edges of the two input clocks of the edge drop phase detector 53 (BBPD) in the case where the multi-modulus division clock enters the first digital-to-time converter 31 of the first delay division block 3 and the second digital-to-time converter 41 of the second delay division block 4, respectively, without delay differencet rise.DTCoff Position corresponding to ck _ fbt rise.DTCm Comprises the following steps:
t rise.DTCoff =t rise.mmd +t dtcoff + t off，bbpd ………………………（3）
t rise.DTCm =t rise.mmd + t dtcm,0………………………（4）
wherein, the first and the second end of the pipe are connected with each other,t rise.mmd for the rising edge time of the multi-modulus divided signal ck mmd output by the multi-modulus divider 2,t dtcoff as the delay time of the first digital-to-time converter 31 (refer to equation (2)),t off，bbpd is the self-detuning time of the phase detector 53 (BBPD). According to the output result COMP of the phase detector 53 (BBPD), the first Gain adjustment quantity DTCOff _ Gain _ out is adjusted, and the delay Gain of the first digital-to-time converter 31 is calibrated according to the first Gain adjustment quantity, so that the delay Gain is adjustedt rise.DTCoff Is equal tot rise.DTCm Namely:t dtcoff + t off，bbpd = t dtcm,0。
thus, the handle can be realizedt dtcm,0Copied as the total delay time of the first digital-to-time converter 31 and the phase detector 53 (BBPD). The criterion for checking whether the adjustment is completed is to repeat the average value of the comparison values generated by calibrating the delay gain of the first digital-to-time converter 31. For example, when the average value of the comparison results COMP of the phase detector 53 (BBPD) every 100 times is rounded to 1, the first Gain adjustment amount dtcof _ Gain _ out increases by unit 1 (or decreases by unit 1, and increases or decreases by a specific definition of the sign of each parameter); when its average value is rounded to 0, the first Gain adjustment dtcof _ Gain _ out is then self-decreasing by unit 1 (or by unit 1, either self-increasing or self-decreasing depending on the specific definition of the sign of the respective parameter). The average of the comparison values obtained in the previous 100 times was rounded to 1 and the average of the comparison values obtained in the next 100 times wasValues are rounded to 0; or the average of the comparison values obtained in the previous 100 times is rounded to 0, and the average of the comparison values obtained in the next 100 times is rounded to 1, which indicates that the calibration of the delay gain of the first digital-to-time converter 31 is completed.
At quantization error eqThat is, dtcm _ in is set to a fixed value of 1, and the entry of the multi-modulus divided clock into the first delay-and-divide block 3 is delayed by one cycle of the input clock compared with the entry into the second delay-and-divide block 4T in In the case of (2), the rising edge positions of the two input clocks of edge drop phase detector 53 (BBPD), i.e., the position corresponding to ck _ ref in the rising edge pair, are at the correctable rising edge of cko _ DTCMt rise.DTCoff Position corresponding to ck _ fbt rise.DTCm Comprises the following steps:
t rise.DTCoff =t rise.mmd +t dtcoff + t off，bbpd +T in ………………………（5）
t rise.DTCm =t rise.mmd + t dtcm,0+DTCm_Gain_out·△ dtcm ………………………（6）
wherein the content of the first and second substances,t rise.mmd for the rising edge time of the multi-modulus divided signal ck mmd output by the multi-modulus divider 2,t dtcoff as the delay time of the first digital-to-time converter 31,t dtcm,0DTCM _ Gain _ out is a second Gain adjustment DTCM _ Gain _ out, Delta, which is a fixed delay time of the second digital-to-time converter 41 dtcm Is the internal unit delay time of the second digital-to-time converter 41. According to the output result COMP of the phase detector 53 (BBPD), the second Gain adjustment amount DTCm _ Gain _ out is adjusted, and the delay Gain of the second digital-to-time converter 41 is calibrated according to the second Gain adjustment amount, so thatt rise.DTCoff Is equal tot rise.DTCm Namely: DTCm _ Gain _ out =T in /△ dtcm 。
Thus, after the calibration of the delay gain of the first digital-to-time converter 31 is completed, the adjustment of the delay gain of the second digital-to-time converter 41 to the target value, i.e., the period T of the input clock ck _ in, can be further realizedin. The criterion for checking whether the adjustment is completed is to repeat the average value of the comparison values generated by calibrating the delay gain of the second digital-to-time converter 41. For example, when the average value of the comparison results COMP of the phase detector 53 (BBPD) every 100 times is rounded to 1, the second Gain adjustment amount DTCm _ Gain _ out increases by unit 1 (or decreases by unit 1, and increases or decreases by a specific definition of the sign of each parameter); when its average value is rounded to 0, the first Gain adjustment DTCm _ Gain _ out is self-decreasing by unit 1 (or by unit 1, self-increasing or self-decreasing depending on the specific definition of the sign of the respective parameter). The average of the comparison values obtained in the previous 100 times was rounded to 1, and the average of the comparison values obtained in the next 100 times was rounded to 0; or the average value of the comparison values obtained in the previous 100 times is rounded to 0, and the average value of the comparison values obtained in the next 100 times is rounded to 1, which indicates that the calibration of the delay gain of the second digital-to-time converter 41 is completed.
After the calibration of the delay gain of the first digital-to-time converter 31 and the calibration of the delay gain of the second digital-to-time converter 41 are completed, a complete gain calibration process is completed. Of course, in actual practice, the complete gain calibration process may be repeated periodically and repeatedly. Therefore, the gain calibration result can be corrected in real time along with the drift of the temperature or the voltage along with the time so as to ensure the accuracy of the integral delay gain of the system.
A digital calibration block 54, further configured to generate a logic split control word from the second delay clock (cko _ DTCm).
Specifically, in order to ensure the correct processing state of each clock signal during the complete gain calibration process, the present embodiment adds a logic separation control word for controlling the state of the relevant clock signal during the complete gain calibration process to the digital calibration module 54. For example, the logic separation control word may include a logic separation control word for controlling a quantization error, and a logic separation control word for controlling a delay difference of the multi-modulus divider clock into the first delay-divider block 3 and the second delay-divider block 4.
On this basis, the gain calibration module 5 further includes: a first logical separation module 55.
As shown in fig. 2, the first logic separation module 55 is connected to a branch of the multi-modulus divided clock ck _ mmd flowing to the first digital-to-time converter 31, and is connected to an output terminal of the digital calibration module 54, for directly inputting the multi-modulus divided clock to the first digital-to-time converter 31 according to a logic separation control word; alternatively, the multi-modulus division clock is delayed by one cycle of the input clock according to the logic separation control word and input to the first digital-to-time converter 31.
Specifically, the logic separation control word may include a logic separation control word Cal _ Gain that calibrates the Gain, the Cal _ Gain having a value of [0,1 ]. When the Cal _ Gain value is 0, the first logic separation module 55 may be controlled to directly input the multi-modulus frequency division clock to the first digital-to-time converter 31; when the value of Cal _ Gain is 1, the first logic separation module 55 may be controlled to delay the divided clock with one cycle of the input clock and input the divided clock to the first digital-to-time converter 31.
As shown in fig. 2, the first logic separation module 55 includes: a D flip-flop (DFF 0) and a two-way select module (mux 0).
The clock end clk of the D flip-flop is connected to the input clock ck _ in, the D end is connected to the multi-modulus frequency division clock ck _ mmd, and the Q end is connected to one channel input end of the two-channel selection module mux0 (the value of Cal _ Gain corresponding to the channel input end is 1); the other path input end of the path selection module mux0 is connected to a multi-modulus frequency division clock (the value of Cal _ Gain corresponding to the path input end is 0).
Thus, the digital calibration module 54 can control the delay difference of the multi-modulus frequency division clock entering the first delay frequency division module 3 and the second delay frequency division module 4 by controlling the value of the Cal _ Gain.
On this basis, the gain calibration module 5 further includes: a second logical separation module 56.
As shown in FIG. 2, a second logic separation block 56 is connected to the quantization error eqFlows to a branch of the second digital-to-time converter 41 and is connected to the output of the digital calibration block 54 for quantizing the error e according to a logically separate control wordqSet to a fixed value of 0; or, quantizing the error eqSet to a fixed value of 1; alternatively, the quantization error is not changed.
In particular, the logically separate control word may include a logically separate control word Cal _ en that enables calibration gain, the Cal _ en taking on a value of [0,1 ]. When Cal _ en takes a value of 0, the second logic separation module 56 can be controlled to input the quantization error (original quantization error) that is not processed additionally into the second digital-to-time converter 41. When the value of Cal _ en is 1, the second logic separation module 56 may be controlled to set the quantization error to a fixed value and then input the fixed value to the second digital-to-time converter 41; when the value of Cal _ Gain is 0, the second logic separation module 56 may be controlled to set the quantization error to a fixed value of 0, and when the value of Cal _ Gain is 1, the second logic separation module 56 may be controlled to set the quantization error to a fixed value of 1.
Thus, the digital calibration module 54 can control the value of the quantization error by controlling the values of Cal _ Gain and Cal _ en.
Specifically, as shown in fig. 8, the second logic separation module 56 may include: two-way select modules mux1, mux2, and a PUL _ Logic Logic circuit constructed from Logic gates and2_0, and2_1 ("AND") and inv ("NOT"). When Cal _ PUL =0, mux2 goes 0 channel, and when Cal _ PUL =1, mux2 goes 1 channel; cal _ Gain =0, mux0 goes 0 channel, Cal _ Gain =1, mux1 goes 1 channel.
As shown in fig. 9, the work flow of the digital calibration module 54 is shown. Assuming that the current state is a Gain adjustment stage (dtcof calibration stage) for dtcofoff, then when Cal _ en =1 and Cal _ Gain =0, skipping to judge whether the average value of COMP counted this time is repeated (AVR { COMP } Toggle) compared with the average value of COMP counted last time; if yes, continuing to jump to judge whether the average value of the COMP counted at this time is larger than 0 after being rounded (whether AVR { COMP } > 0 is judged); if so, the first Gain adjustment amount is increased automatically based on the original first Gain adjustment amount to generate a new first Gain adjustment amount (DTCOff _ Gain _ out + +), and if not, the first Gain adjustment amount is decreased automatically based on the original first Gain adjustment amount to generate a new first Gain adjustment amount (DTCOff _ Gain _ out-).
After jumping to judge whether the average value of the COMP counted at this time is repeated (AVR { COMP } Toggle) or not compared with the average value of the COMP counted at the last time; if the judgment result is negative, jumping to a Gain adjustment stage (DTCM correction stage) aiming at the DTCM, and then when Cal _ en =1 and Cal _ Gain =1, jumping to judge whether the average value of COMP counted this time is repeated (AVR { COMP } Toggle) compared with the average value of COMP counted last time; if yes, continuing to jump to judge whether the average value of the COMP counted at this time is larger than 0 after rounding (whether AVR { COMP } > 0 is judged); if so, the first Gain adjustment amount is automatically increased on the basis of the original second Gain adjustment amount to generate a new second Gain adjustment amount (DTCM _ Gain _ out + +), and if not, the second Gain adjustment amount is automatically decreased on the basis of the original second Gain adjustment amount to generate a new second Gain adjustment amount (DTCM _ Gain _ out-).
In a gain adjustment stage (DTCM compensation stage) aiming at DTCM, after the jump judges whether the average value of COMP counted this time is repeated (AVR { COMP } Toggle) compared with the average value of COMP counted last time, if the judgment result is negative, the jump is carried out to a gain adjustment stage (DTCOff compensation stage) aiming at DTCOff.
After generating the second Gain adjustment amount (DTCm _ Gain _ out) based on the above-described workflow, Gain calibration of the DTCm Gain at the present time according to the second Gain adjustment amount can be achieved in two ways.
The first method is as follows:
as shown in fig. 10, the gain calibration module 5 further includes: a digital-to-analog converter 57 and a linear regulated power supply 58.
The input end of the digital-to-analog converter 57 is connected to the output end of the digital calibration module 54, and is configured to perform digital-to-analog conversion on the digital signal of the second gain adjustment amount to generate an analog voltage signal;
an input terminal of the linear regulated power supply 58 is connected to an output terminal of the digital-to-analog converter 57, and is configured to generate an output voltage signal with the analog voltage signal as a reference voltage signal, and to use the output voltage signal as a power supply voltage of the second digital-to-time converter.
Specifically, the second Gain adjustment DTCm _ Gain _ out output by the digital calibration module 54 is a digital signal, and the digital signal needs to be converted into an analog signal by the digital-to-analog converter 57, and the analog signal is used as the input reference voltage of the linear regulated power supply 58, so the analog signal is also called an analog voltage signal (Vref).
An input terminal of the linear regulated power supply 58 is connected to an output terminal of the digital-to-analog converter 57, and is configured to generate an output voltage signal Vdd _ DTCm by using the analog voltage signal as a reference voltage signal, and supply the output voltage signal Vdd _ DTCm as a power supply voltage of the second digital-to-time converter 41.
Specifically, since the input and the output of the linear regulated power supply are in a linear relationship, and the supply voltage and the gain of the digital-to-time converter are also in a linear relationship, the adjustment of the delay gain of the second digital-to-time converter 41 can be realized by using the linear regulated power supply to obtain the delay gain at the next time, so that the second digital-to-time converter 41 is controlled based on the quantization error and the delay gain at the next time.
The second method comprises the following steps:
as shown in fig. 11, the gain calibration module 5 further includes: a multiplier 59.
In particular, the multiplier 59 is connected to the quantization error eqFlows to the branch of the second digital-to-time converter 41 and the first input of the multiplier 59 is connected to the quantization error eqThe second input end is connected to the second gain adjustment amount, and the output end is connected to the second digital-to-time converter 41, so that the product of the second gain adjustment amount and the delay gain of the second digital-to-time converter 41 at the current time is used as the delay gain of the second digital-to-time converter 41 at the next time.
Specifically, the second Gain adjustment amount DTCm _ Gain _ out output by the digital calibration module 54 may be directly multiplied by the delay Gain of the second digital-to-time converter 41 at the present time by the multiplier 59, and the resultant product is used as the delay Gain of the next time, so that the second digital-to-time converter 41 is controlled based on the quantization error and the delay Gain of the next time.
Compared with the related art, the embodiment of the invention generates the output bit and the quantization error according to the decimal frequency division coefficient through the modulation module, and generates the frequency division control signal by adding the output bit and the integer frequency division coefficient; the multi-mode frequency divider switches between N/N +1 frequency division ratios according to the frequency division control signal and divides the frequency of the input clock to output a multi-mode frequency division clock; the first delay frequency division module delays the multi-mode frequency division clock to generate a first delay clock, and divides the frequency of the first delay clock to generate a first frequency division clock; the second delay frequency division module delays the multi-mode frequency division clock according to the quantization error to generate a second delay clock, and divides the frequency of the second delay clock to generate a second frequency division clock; the gain calibration module extracts a calibratable rising edge pair corresponding to the rising edge of the same multi-modulus frequency division clock from the first delay clock and the second delay clock, and generates a first gain adjustment amount or a second gain adjustment amount according to the phase difference of two rising edges in the rising edge pair; wherein the first gain adjustment amount is used for calibrating the delay gain of the first delay division module under the condition that the quantization error is set to be a fixed value 0 and the multi-mode frequency division clock respectively enters the first delay division module and the second delay division module without delay difference, so that the total delay time from the multi-mode frequency division clock to the formation of the rising edge pair is the same; and a second gain adjustment amount for calibrating the delay gain of the second delay-and-divide block so that the total delay time from the multi-modulus divider clock to the rising edge pair is the same, in a case where the quantization error is set to a fixed value of 1 and the entry of the multi-modulus divider clock into the first delay-and-divide block is delayed by one period of the input clock compared to the entry into the second delay-and-divide block. According to the scheme, a first gain adjustment quantity or a second gain adjustment quantity generated by the phase difference of two rising edges in a calibratable rising edge pair extracted from a first delay clock and a second delay clock is used, the first gain adjustment quantity is used for calibrating the delay gain of a first delay frequency division module to enable the delay gain to be equivalent to the difference of fixed delay time between the first delay frequency division module and the second delay frequency division module, then, a period delay of an input clock is added to a delay path of the first delay frequency division module, and the delay gain of the second delay frequency division module is calibrated by adjusting the second gain adjustment quantity to enable the delay gain to approach the period of the input clock, namely the target gain. The gain of the DTC does not need to be changed according to the change of the PVT, so that the design difficulty of the open-loop fractional frequency divider is greatly reduced.
Another embodiment of the present invention relates to a clock system, including: the open-loop fractional divider based on time division multiplexing gain calibration in the above-described embodiment.
Specifically, the clock system may be a clock system built in any device such as a terminal, a server, or the like.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.

Claims (14)

1. An open-loop fractional divider based on time division multiplexed gain calibration, comprising: the device comprises a modulation module, a multi-mode frequency divider, a first delay frequency dividing module, a second delay frequency dividing module and a gain calibration module;
the modulation module is used for generating an output bit and a quantization error according to the decimal frequency division coefficient and generating a frequency division control signal by adding the output bit and the integer frequency division coefficient;
the multi-mode frequency divider is connected with the output end of the modulation module and used for switching between N/N +1 frequency division ratios according to the frequency division control signal and dividing an input clock to output a multi-mode frequency division clock;
the first delay frequency division module is connected with the output end of the multi-mode frequency divider and used for delaying the multi-mode frequency division clock to generate a first delay clock and dividing the frequency of the first delay clock to generate a first frequency division clock;
the second delay frequency division module is connected with the output end of the modulation module and the output end of the multi-mode frequency divider, and is used for delaying the multi-mode frequency division clock according to the quantization error to generate a second delay clock and dividing the second delay clock to generate a second frequency division clock;
the gain calibration module is connected with the output end of the first delay frequency division module and the output end of the second delay frequency division module, and is used for extracting a calibratable rising edge pair corresponding to the rising edge of the same multi-mode frequency division clock from the first delay clock and the second delay clock, and generating a first gain adjustment amount or a second gain adjustment amount according to the phase difference of two rising edges in the rising edge pair;
the first gain adjustment amount is used for calibrating the delay gain of the first delay division module under the condition that the quantization error is set to be a fixed value 0 and the multi-modulus frequency division clock respectively enters the first delay division module and the second delay division module without delay difference so as to lead the total delay time from the multi-modulus frequency division clock to the formation of the rising edge pair to be the same;
the second gain adjustment amount is used for calibrating the delay gain of the second delay-and-divide module so that the total delay time from the multi-modulus frequency-division clock to the formation of the rising edge pair is the same when the quantization error is set to be a fixed value of 1 and the entry of the multi-modulus frequency-division clock into the first delay-and-divide module is delayed by one period of the input clock compared with the entry of the multi-modulus frequency-division clock into the second delay-and-divide module;
and N is the integer frequency division coefficient and is a positive integer greater than or equal to 1.
2. The open-loop fractional divider based on time division multiplexed gain calibration of claim 1, wherein the modulation module comprises: a delta-sigma modulator and a first adder;
the input end of the delta-sigma modulator is connected with the fractional frequency division coefficient, the first output end generates the output bit, and the second output end generates the quantization error;
the first input end of the first adder is connected to the integer frequency division coefficient, the second input end of the first adder is connected to the first output end of the delta-sigma modulator, and the output end of the first adder generates the frequency division control signal.
3. The time division multiplexed gain calibration based open loop fractional divider of claim 2, wherein the Δ Σ modulator is a first order Δ Σ modulator.
4. The open-loop fractional divider based on time division multiplexing gain calibration of claim 1, wherein the first delay-divide module comprises: a first digital-to-time converter and a first post-divider;
the first digital-to-time converter is connected with the output end of the multi-modulus frequency divider and used for delaying the multi-modulus frequency division clock to generate a first delayed clock;
the first post-divider is connected to the output end of the first digital-to-time converter, and is configured to divide the frequency of the first delayed clock to generate the first divided clock.
5. The time-division-multiplexed-gain-calibration-based open-loop fractional divider of claim 4, wherein the second delayed-divide module comprises: a second digital-to-time converter and a second post-divider;
the second digital time converter is connected with the output end of the modulation module and the output end of the multi-mode frequency divider and used for delaying the multi-mode frequency division clock according to the quantization error to generate a second delay clock;
the second post-divider is connected to the output end of the second digital-to-time converter, and is configured to divide the frequency of the second delayed clock to generate the second divided clock.
6. The time division multiplexed gain calibration based open loop fractional divider of claim 5, wherein the gain calibration module comprises: the device comprises a first phase selection module, a second phase selection module, a phase discriminator and a digital calibration module;
the first phase selection module is connected with the output end of the first digital-to-time converter and the output end of the first frequency post-divider and used for extracting a calibratable first rising edge from the first delay clock;
the second phase selection module is connected with the output end of the second digital time converter and the output end of the second frequency divider and used for extracting a second adjustable rising edge from the second delay clock; forming a pair of said correctable first rising edges and said calibratable second rising edges corresponding to a same rising edge of said multi-divided clock;
the phase discriminator is connected with the output end of the first phase selection module and the output end of the second phase selection module, and is used for comparing the phases of the first rising edge and the second rising edge in the rising edge pair to generate a comparison value;
the digital calibration module is connected with the output end of the phase discriminator and is used for generating the first gain adjustment quantity according to the comparison value under the condition that the quantization error is set to be a fixed value 0 and the multi-mode frequency division clock respectively enters the first delay frequency division module and the second delay frequency division module without delay difference, and calibrating the delay gain of the first digital time converter according to the first gain adjustment quantity so as to enable the average value of the comparison value to repeat; or, when the quantization error is set to a fixed value of 1, and the multi-modulus frequency division clock enters the first delay frequency division module with a delay of one input clock period compared with the second delay frequency division module, generating the second gain adjustment amount according to the comparison value, and calibrating the delay gain of the second digital-to-time converter according to the second gain adjustment amount, so as to repeat the average value of the comparison value;
the digital calibration module is further configured to generate a logic separation control word according to the second delay clock.
7. The time-division-multiplexed-gain-calibration-based open-loop fractional divider of claim 6, wherein the first phase selection module and the second phase selection module are both D flip-flops:
the D flip-flop as the first phase selection module has a clock terminal connected to the output terminal of the first digital-to-time converter, a D terminal connected to the output terminal of the first frequency divider, and a Q terminal for generating the first rising edge;
and the D trigger as the second phase selection module has a clock end connected with the output end of the second digital-to-time converter, a D end connected with the output end of the second post frequency divider, and a Q end for generating the second rising edge.
8. The open-loop fractional divider based on time division multiplexed gain calibration of claim 7, wherein the phase detector is a bang-bang phase detector.
9. The time division multiplexed gain calibration based open loop fractional divider of claim 6, wherein the gain calibration module further comprises: a first logical separation module;
the first logic separation module is connected to a branch of the multi-modulus frequency division clock flowing to the first digital-to-time converter, is connected with the output end of the digital calibration module, and is used for directly inputting the multi-modulus frequency division clock to the first digital-to-time converter according to the logic separation control word; or delaying the multi-modulus frequency division clock by one period of the input clock according to the logic separation control word and inputting the multi-modulus frequency division clock to the first digital-to-time converter.
10. The open-loop fractional divider based on time division multiplexed gain calibration of claim 9, wherein the first logic splitting module comprises: a D trigger and a two-way selection module;
the clock end of the D flip-flop is connected with the input clock, the D end is connected with the multi-modulus frequency division clock, and the Q end is connected with one channel input end of the two-channel selection module; and the other path input end of the path selection module is connected with the multi-modulus frequency division clock.
11. The time division multiplexed gain calibration based open loop fractional divider of claim 6, wherein the gain calibration module further comprises: a second logical separation module;
the second logic separation module is connected to a branch of the quantization error flow to the second digital-to-time converter, is connected to an output end of the digital calibration module, and is configured to set the quantization error to a fixed value of 0 according to the logic separation control word; or, setting the quantization error to a fixed value of 1; alternatively, the quantization error is not changed.
12. The open-loop fractional divider based on time-division multiplexing gain calibration of any one of claims 6 to 11, wherein the gain calibration module further comprises: a digital-to-analog converter and a linear regulated power supply;
the input end of the digital-to-analog converter is connected with the output end of the digital calibration module and is used for performing digital-to-analog conversion on the digital signal of the second gain adjustment quantity to generate an analog voltage signal;
the input end of the linear voltage-stabilized source is connected with the output end of the digital-to-analog converter and used for generating an output voltage signal by taking the analog voltage signal as a reference voltage signal and taking the output voltage signal as the power voltage of the second digital time converter.
13. The time division multiplexed gain calibration based open loop fractional divider as claimed in any of claims 6 to 11, wherein the gain calibration module further comprises: a multiplier;
the multiplier is connected to a branch of the quantization error flow to the second digital-to-time converter, a first input end of the multiplier is connected to the quantization error, a second input end of the multiplier is connected to the second gain adjustment quantity, and an output end of the multiplier is connected to the second digital-to-time converter, so that the product of the second gain adjustment quantity and the delay gain of the second digital-to-time converter at the current moment is used as the delay gain of the second digital-to-time converter at the next moment.
14. A clock system, the clock system comprising: the open-loop fractional divider based on time division multiplexed gain calibration of any of claims 1-13.
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