CN112003620B - Pipeline successive approximation type ADC (analog to digital converter) bit weight background calibration system and method - Google Patents
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Abstract
The invention discloses a pipeline successive approximation type ADC (analog to digital converter) position weight background calibration system, which comprises a first-stage SAR ADC circuit and a second-stage SAR ADC circuit; the first-stage SAR ADC circuit comprises an auxiliary DAC, a main DAC, a comparator, an SAR logic module, a pseudo-random signal generator and a decision logic module; the output end of the auxiliary DAC is connected with the input end of the comparator, and input signals are quantized to obtain a digital output code D of the first-stage SAROUT1(ii) a The SAR logic module performs one additional comparison on the residual information of the auxiliary DAC to obtain D0(ii) a Decision logic module will DOUT1And D0Compiled output DPNA full range pseudo-random signal (PN) injection window is generated by the master DAC as an input to the master DAC. The invention can realize the PN signal injection in the full range, thereby improving the algorithm convergence speed and ensuring that the output signal of the amplifier does not exceed the quantization range of the SAR ADC in the next stage.
Description
Technical Field
The invention relates to the technical field of pipeline successive approximation type analog-to-digital converters, in particular to a pipeline successive approximation type ADC bit right background calibration system and method.
Background
The pipeline-SAR ADC is a composite ADC structure that combines the advantages of both Pipelined and successive approximation ADCs. The signals are quantized in two stages by connecting two SAR ADCs with smaller quantization bits together in a pipeline method. The high-speed high-precision SAR analog-to-digital converter has the advantages of low SAR power consumption and simple structure, and also has the high-speed high-precision characteristic of a pipeline ADC.
A pipeline-SAR ADC background calibration method based on pseudo-random noise signal injection is a practical calibration method which is started in recent years. The method usually generates a PN injection window by detecting the state of a comparator in a subthreshold region, detects and estimates the mismatch and the interstage gain error of a capacitor array by injecting a PN signal into an input signal in the window, and then calibrates the capacitor mismatch and the interstage gain error in a digital domain or an analog domain. By utilizing the sub-threshold effect, the size of a window for outputting a PN signal can be effectively positioned, but the window obtained by sub-threshold detection is small and unstable in range, the convergence speed of the algorithm is low, and the precision is limited when the circuit is calibrated; the direct injection of the PN signal into the capacitor results in the amplifier output exceeding the quantization range of the next stage. The problem that the generation of an input window and the guarantee that the rest amount of voltage after the injection of a PN signal cannot exceed the maximum quantization range of the second-stage SAR ADC after being amplified by an amplifier still needs to be solved urgently in the field.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a system and a method for calibrating the bit weight background of an analog-to-digital converter (ADC) in a pipeline successive approximation mode, which can realize the PN signal injection in a full range, thereby improving the algorithm convergence speed and ensuring that the output signal of an amplifier does not exceed the quantization range of the SAR ADC in the next stage.
In order to achieve the purpose, the invention adopts the following technical scheme:
a pipeline successive approximation type ADC (analog to digital converter) position weight background calibration system comprises a first-stage SAR ADC circuit and a second-stage SAR ADC circuit, wherein the output end of the first-stage SAR ADC circuit is connected with the input end of the second-stage SAR ADC circuit through an interstage amplifier;
the first-stage SAR ADC circuit comprises an auxiliary DAC, a main DAC, a comparator, an SAR logic module, a pseudo-random signal generator and a decision logic module;
the output end of the auxiliary DAC is connected with the input end of the comparator to quantize the input signal, wherein the capacitor array of the auxiliary DAC samples the upper electrode plate, the comparator directly compares the input signal for the first time, the comparison result is processed by the SAR logic module and then used for controlling the switching of the auxiliary DAC array, successive approximation operation is carried out until the first-stage quantization is completed, and the digital output code D of the first-stage SAR is obtainedOUT1(ii) a Meanwhile, the SAR logic module performs one-time additional comparison on the residual information of the auxiliary DAC to obtain D0；
One input end of the decision logic module and the SAR logic moduleIs connected to the pseudo-random signal generator, and has an output connected to the input of the main DACOUT1And D0Compiled output DPNGenerating a full range PN signal injection window by the main DAC as an input to the main DAC, wherein D is used0The signal further subdivides the injection window into 4 regions;
the output end of the main DAC is connected with the input end of the second-stage SAR ADC circuit through the interstage amplifier, and the output result of the main DAC is amplified by the interstage amplifier and then serves as the input signal of the second-stage SAR ADC circuit.
In order to optimize the technical scheme, the specific measures adopted further comprise:
furthermore, the calibration system further comprises a digital domain calculation and calibration error circuit, wherein the digital domain calculation and calibration error circuit comprises three input ends which are respectively connected with the output end of the pseudo-random signal generator, the output end of the second-stage SAR ADC circuit and the output end of the decision logic module and used for calibrating the ADC system error.
Further, the input signal and the reference voltage are simultaneously used as the input of the main DAC.
Further characterized in that an additional capacitor C is inserted in the main DACdAnd the circuit is used for reversing the reference voltage of the shifting capacitor according to the polarity of the PN signal input and integrally descending or ascending a transfer curve close to the maximum margin voltage range after the PN signal is injected.
Based on the calibration system, the invention also provides a pipeline successive approximation type ADC bit right background calibration method, which comprises the following steps:
s1, defining any group of input signals and reference voltage, and performing successive approximation conversion by the first-stage SAR circuit, wherein the input signals are quantized by the cooperation of the auxiliary DAC and the comparator, and the output digital code of the first-stage SAR circuit is D after the quantization is finishedOUT1Then, making an additional comparison on the residual information of the auxiliary DAC to obtain D0；
S2, mixing DOUT1And D0As input to the decision logic block, DOUT1D is obtained by quantizing the auxiliary DAC and the comparator once more for the result after the conversion of the first-stage SAR ADC circuit is finished0The signal further subdivides the injection window into 4 regions; d is converted into D by adopting a decision logic moduleOUT1And D0Compiled output DPNGenerating a final residual signal by the main DAC as an input to the main DAC;
and S3, amplifying the output result of the main DAC by the interstage amplifier to be used as the input signal of the second-stage SAR ADC circuit.
Further, in step S3, D obtained by quantizing the auxiliary DAC once more0The signal further subdivides the input window into 4 regions, meaning:
in each full-range PN signal injection window, the PN signal controls the judgment logic module to output two random conditions, and the full-range PN signal injection window is divided into four areas.
Further, the calibration method further comprises:
inserting an additional capacitance C in the main DACdAn additional capacitance CdShifting the reference voltage of the capacitor in a reverse direction according to the polarity input by the PN signal, and integrally descending or ascending a transfer curve close to the maximum margin voltage range after the PN signal is injected;
calculating to obtain an additional capacitor C according to a preset redundancy rangedThe output of the interstage amplifier is controlled within the allowable range of the next stage SAR ADC signal.
Further, the calibration method further comprises:
combining PN signal generated by pseudo-random signal generator and D generated by second-stage SAR ADC circuitOUT2D of signal and decision logic module outputPNThe signal is corrected by adopting a digital domain calculation and correction error circuit to obtain a final output result DOUT。
The invention has the beneficial effects that:
(1) the use of the master DAC may limit the thermal noise of the sampling process and may produce a stable full range input window.
(2) Because the auxiliary DAC and the comparator are combined to complete the quantization work of the first-stage SAR ADC, the quantization speed of the first-stage SAR ADC is high, and the delay time added by inserting decision logic and extra comparison can be offset. Because the capacitance value of the auxiliary DAC used for quantization is small, the caused extra hardware overhead and the influence of the extra hardware overhead on the input buffer are small, the improvement of the ADC speed can be omitted compared with the structure, and the performance of the whole system is effectively improved.
(3) Inserting extra C in the main DACdThe capacitor can make corresponding reference voltage switching when the PN signal is injected, and even if non-ideal factors such as noise exist, the residual voltage of the first-stage SAR ADC can be ensured not to exceed the quantization range of the second-stage SAR ADC after the PN signal is injected and amplified by the amplifier.
Drawings
FIG. 1 is a schematic structural diagram of a pipeline successive approximation type ADC bit right background calibration system according to the present invention.
Fig. 2 is a diagram of the input signal transfer curve for an additional comparison of the residual information of the auxiliary DAC to further divide the input window into A, B, C, D four regions.
FIG. 3 is a schematic diagram of a stable full-range PN injection window generated by injecting PN and correspondingly toggling a small capacitor Cd.
Fig. 4 is a schematic diagram of a variation curve of the magnitude of the margin voltage by applying the method of the present invention.
Fig. 5 is a diagram showing simulation results of the ADC before calibration.
Fig. 6 is a diagram showing simulation results of the ADC after calibration.
Detailed Description
The present invention will now be described in further detail with reference to the accompanying drawings.
It should be noted that the terms "upper", "lower", "left", "right", "front", "back", etc. used in the present invention are for clarity of description only, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not limited by the technical contents of the essential changes.
With reference to fig. 1, the present invention provides a pipeline successive approximation type ADC bit weight background calibration system, which includes a first stage SAR ADC circuit and a second stage SAR ADC circuit, wherein an output terminal of the first stage SAR ADC circuit is connected to an input terminal of the second stage SAR ADC circuit through an interstage amplifier.
The first-stage SAR ADC circuit comprises an auxiliary DAC, a main DAC, a comparator, an SAR logic module, a pseudo-random signal generator and a decision logic module.
The output end of the auxiliary DAC is connected with the input end of the comparator to quantize the input signal, wherein the capacitor array of the auxiliary DAC samples the upper electrode plate, the comparator directly compares the input signal for the first time, the comparison result is processed by the SAR logic module and then used for controlling the switching of the auxiliary DAC array, successive approximation operation is carried out until the first-stage quantization is completed, and the digital output code D of the first-stage SAR is obtainedOUT1(ii) a Meanwhile, the SAR logic module performs one-time additional comparison on the residual information of the auxiliary DAC to obtain D0。
One input end of the decision logic module is connected with the output end of the SAR logic module, the other input end of the decision logic module is connected with the pseudo-random signal generator, the output end of the decision logic module is connected with the input end of the main DAC, and D is obtainedOUT1And D0Compiled output DPNGenerating a full range PN signal injection window by the main DAC as an input to the main DAC, wherein D is used0The signal further subdivides the input window into 4 regions. The full range PN injection window here means that PN injection can be performed to calibrate over the range of the input signal.
The output end of the main DAC is connected with the input end of the second-stage SAR ADC circuit through the interstage amplifier, and the output result of the main DAC is amplified by the interstage amplifier and then serves as the input signal of the second-stage SAR ADC circuit.
The invention adopts the auxiliary DAC and the main DAC to combine to carry out the quantization work of the first-stage SAR ADC, the auxiliary DAC is utilized to quickly complete the quantization, and the main DAC generates a stable full-range PN injection window. The invention is further described with reference to the following figures and examples.
FIG. 1 is a full range of the present embodiment based on stabilizationAnd the first-stage SAR ADC circuit adopts a structure of combining an auxiliary DAC and a main DAC. The auxiliary DAC is fast in establishment speed in the quantization process due to small capacitance, so that the quantization of the first-stage SAR can be completed faster to obtain DOUT1And performing one additional comparison on the margin after the conversion of the auxiliary DAC is finished to obtain D0. As shown in FIG. 2, D0The window is further divided into A, B, C, D four regions, and the PN signals generated by the pseudo-random signal generator are injected into A, B, C, D four regions, respectively. The input of the signals to the main DAC is realized through a decision logic module, and finally, the main DAC generates a final full-range PN injection window and connects the margin of the first-stage SAR ADC to the input end of the interstage amplifier to provide the conversion of the next stage.
The respective injection of PN signals in the A, B, C, D regions results in a transfer curve range covering the maximum margin voltage range, and in order to tolerate the influence of noise and other non-ideal factors, the ADC still needs to have a certain redundancy range. Inserting an additional capacitor C in the main DACdToggling C according to the polarity direction of PN signal during PN injectiondThe reference voltage of (1). Poke CdThe whole transfer curve in the window can be raised or lowered, and C is reasonably selecteddCan be controlled to be 75% of the range of the next stage ADC quantization signal, as shown in fig. 3. It should be understood that CdIs related to the redundancy range, and can dynamically adjust C according to actual requirementsdBut the working principle is the same.
The invention also provides a calibration method of the pipeline successive approximation type analog-to-digital converter bit weight background calibration circuit based on the stable full-range window, in the method, the pipeline successive approximation type analog-to-digital converter bit weight background calibration circuit based on the stable full-range window can realize PN signal injection of the full-range window, and the steps of generating the stable full-range injection pseudo-random signal window are as follows:
(1) defining any group of input signals and reference voltage, and performing successive approximation conversion by a first-stage SAR ADC circuit in which an auxiliary DAC is used for comparing the input signals with the reference voltageThe comparator is matched for quantization, and after the quantization is finished, the output digital code of the first stage is obtained and is DOUT1Then, making an additional comparison on the residual information of the auxiliary DAC to obtain D0。
(2) Will DOUT1And D0As input to decision logic, DOUT1D is obtained by quantizing the auxiliary DAC for one more time for the residual voltage after the conversion of the first-stage SAR ADC circuit is finished0The signal further subdivides the injection window into A, B, C, D4 regions.
(3) In each window, the PN signal controls the logic circuit to enable the output of the logic circuit to be in two random conditions, the window is divided into four areas, a stable full-range window can be realized, the output of the main DAC does not exceed the quantization range of the next-stage sub ADC after being amplified by the amplifier, but in order to tolerate the influence of other non-ideal factors such as noise, the ADC still needs to have a certain redundancy range, and the overflow of signals is avoided.
(4) An additional capacitor C is added in the main DACd，CdCan stir the reference voltage of the electric capacity according to the polarity reversal of PN signal input, will be close to the whole decline or the rise of transfer curve of the maximum margin voltage scope after injecting the PN signal, simultaneously, the transfer curve of originally keeping away from the maximum margin voltage scope also can be because of stirring CdThe overall change occurs; by reasonably selecting CdThe output of the amplifier can be controlled to be 75% of the signal range of the next-stage ADC, so that a 25% redundant range is obtained to tolerate the influence of noise and other non-ideal factors, and the output signal of the amplifier is ensured not to exceed the quantization range of the next-stage ADC.
Because the capacitance value of the auxiliary DAC used for quantization is small, the caused extra hardware overhead and the influence of the extra hardware overhead on the input buffer are small, and the improvement of the ADC speed can not be calculated compared with the structure. In addition, the input signal and the reference voltage are simultaneously connected with the main DAC, so that the thermal noise in the sampling process can be limited, and further noise influence can not be received. The structure that the auxiliary DAC and the main DAC work in a combined mode greatly accelerates the speed of the method for calibrating the Pipelined-SAR ADC through injecting PN signals through small hardware overhead and power consumption, and an input window generated by the main DAC has the advantages of being full-range and stable. Fig. 4 is a variation curve of the magnitude of the margin voltage by applying the method of the present invention.
On the premise of no or little loss of conversion speed of the original ADC, accuracy and hardware overhead are the main criteria for checking the performance of the calibration circuit, and the improvement of the effective number or the Spurious Free Dynamic Range (SFDR) after calibration is usually used as the basis for judgment. In order to verify the performance of the invention, simulation tests are carried out on platforms such as Cadence and Matlab on the stable full-range window-based pipeline successive approximation type analog-to-digital converter bit weight background calibration circuit. As shown in fig. 5 and 6, after calibration, the effective number is increased by 0.24b, the signal-to-noise-and-distortion ratio is increased by 1.5dB, the spurious-free dynamic range is increased by 12.2dBc, and the dynamic performance of the circuit is significantly improved.
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and embellishments within the scope of the invention may be made by those skilled in the art without departing from the principle of the invention.
Claims (7)
1. A pipeline successive approximation type ADC (analog to digital converter) bit weight background calibration system is characterized by comprising a first-stage SAR ADC circuit and a second-stage SAR ADC circuit, wherein the output end of the first-stage SAR ADC circuit is connected with the input end of the second-stage SAR ADC circuit through an interstage amplifier;
the first-stage SAR ADC circuit comprises an auxiliary DAC, a main DAC, a comparator, an SAR logic module, a pseudo-random signal generator and a decision logic module;
the output end of the auxiliary DAC is connected with the input end of the comparator to quantize the input signal, wherein the capacitor array of the auxiliary DAC samples the upper plate, the comparator directly compares the input signal for the first time, the comparison result is processed by the SAR logic module and then used for controlling the switching of the auxiliary DAC array, and successive approximation operation is carried out until the first-stage quantization is completedTo obtain the digital output code D of the first-stage SAROUT1(ii) a Meanwhile, the SAR logic module performs one-time additional comparison on the residual information of the auxiliary DAC to obtain D0；
One input end of the decision logic module is connected with the output end of the SAR logic module, the other input end of the decision logic module is connected with the pseudo-random signal generator, the output end of the decision logic module is connected with the input end of the main DAC, and D is obtainedOUT1And D0Compiled output DPNGenerating a full range PN signal injection window by the main DAC as an input to the main DAC, wherein D is used0The signal further subdivides the full range PN signal injection window into 4 regions;
the output end of the main DAC is connected with the input end of the second-stage SAR ADC circuit through an interstage amplifier, and the output result of the main DAC is amplified by the interstage amplifier and then is used as an input signal of the second-stage SAR ADC circuit;
an additional capacitor C is inserted into the main DACdAnd the circuit is used for reversing the reference voltage of the shifting capacitor according to the polarity of the PN signal input and integrally descending or ascending the transmission curve after the PN signal is injected.
2. The pipelined successive approximation type ADC bit weight background calibration system of claim 1, further comprising a digital domain calculation and calibration error circuit comprising three input terminals respectively connected to an output terminal of the pseudo-random signal generator, an output terminal of the second stage SAR ADC circuit and an output terminal of the decision logic module for calibrating ADC system errors.
3. The pipelined successive approximation ADC bit-weight background calibration system of claim 1, in which the input signal and a reference voltage are simultaneously inputs to a main DAC.
4. A pipeline successive approximation ADC bit right background calibration method based on the calibration system of claim 1, wherein the calibration method comprises the following steps:
s1, defining any group of input signals and reference voltage, and performing successive approximation conversion by the first-stage SAR circuit, wherein the input signals are quantized by the cooperation of the auxiliary DAC and the comparator, and the output digital code of the first-stage SAR circuit is D after the quantization is finishedOUT1Then, making an additional comparison on the residual information of the auxiliary DAC to obtain D0；
S2, mixing DOUT1And D0As input to the decision logic block, DOUT1D is obtained by quantizing the auxiliary DAC and the comparator once more for the result after the conversion of the first-stage SAR ADC circuit is finished0Signal, further subdividing the injection window into 4 regions; d is converted into D by adopting a decision logic moduleOUT1And D0Compiled output DPNGenerating a first-stage residual signal by the main DAC as an input of the main DAC;
and S3, amplifying the output result of the main DAC by the interstage amplifier to be used as the input signal of the second-stage SAR ADC circuit.
5. The pipelined successive approximation ADC bit weight background calibration method of claim 4, wherein in step S2, the D obtained by quantizing the auxiliary DAC once more0The signal further subdivides the input window into 4 regions, meaning:
in each full-range PN signal injection window, the PN signal controls the judgment logic module to output two random conditions, and the full-range PN signal injection window is divided into four areas.
6. The pipelined successive approximation ADC bit weight background calibration method of claim 4, further comprising:
inserting an additional capacitance C in the main DACdAn additional capacitance CdShifting the reference voltage of the capacitor in a reverse direction according to the polarity input by the PN signal, and lowering or raising the whole transfer curve after the PN signal is injected;
calculating to obtain an additional capacitor C according to a preset redundancy rangedTo control the output of the interstage amplifier to be the next stage SAR ADC signalWithin the allowable range.
7. The pipelined successive approximation ADC bit weight background calibration method of claim 4, further comprising:
combining PN signal generated by pseudo-random signal generator and D generated by second-stage SAR ADC circuitOUT2D of signal and decision logic module outputPNThe signal is calibrated for system error by adopting a digital domain calculation and calibration error module to obtain a final output result DOUT。
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| CN112600559B (en) * | 2020-12-02 | 2024-03-19 | 深圳市国微电子有限公司 | Pipelined analog-to-digital converter and transceiver chip |
| CN113098511B (en) * | 2021-03-01 | 2023-03-21 | 深圳市纽瑞芯科技有限公司 | Front-end self-calibration method of pipeline successive approximation type analog-to-digital converter |
| CN113437972B (en) * | 2021-06-11 | 2023-03-24 | 上海联影微电子科技有限公司 | Capacitance calibration method and electronic device |
| CN113839674B (en) * | 2021-09-24 | 2024-04-02 | 澳门大学 | Analog-to-digital conversion circuit |
| CN114070314B (en) * | 2022-01-18 | 2022-05-03 | 南京航空航天大学 | Method and system for calibrating interstage gain error of pipeline successive approximation ADC (analog-to-digital converter) |
| CN115589228B (en) * | 2022-11-24 | 2023-03-28 | 奉加微电子（昆山）有限公司 | Method and system for calibrating Pipeline-SAR ADC nonlinear error |
| CN116208154B (en) * | 2023-05-06 | 2023-07-07 | 南京航空航天大学 | Bit weight detection and calibration method for pipeline successive approximation type ADC |
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