CN102751990A - Pipelined analog-to-digital converter capable of improving dynamic performance - Google Patents
Pipelined analog-to-digital converter capable of improving dynamic performance Download PDFInfo
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- CN102751990A CN102751990A CN2012102023598A CN201210202359A CN102751990A CN 102751990 A CN102751990 A CN 102751990A CN 2012102023598 A CN2012102023598 A CN 2012102023598A CN 201210202359 A CN201210202359 A CN 201210202359A CN 102751990 A CN102751990 A CN 102751990A
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Abstract
The invention discloses a pipelined analog-to-digital converter capable of improving dynamic performance. The pipelined analog-to-digital converter comprises a pipelined analog-to-digital converter (ADC) grade circuit module which comprises a sampling retaining circuit, a sub- analog-to-digital converter, a sub-digital-to-analog converter, a subtracter, an allowance amplifier, a barrel-shaped shifter, a decoder and a pseudo random number generator. The pseudo random number generator is used for generating pseudo random numbers, the decoder is used for decoding the input binary-format pseudo random numbers into corresponding signals, and the barrel-shaped shifter is used for performing random shifting on control signals of the sub-grade digital-to-analog converter according to the pseudo random numbers. Based on the fact that the control signal sequence of the sub-digital-to-analog converter is controlled by the pseudo random numbers, capacitor mismatch errors which are relatively fixed originally are randomized, and the dynamic performance of the pipelined analog-to-digital converter is improved. According to the pipelined analog-to-digital converter, the circuit is simple in structure, influences on normal work of the pipelined analog-to-digital converter are small, and the dynamic performance is obviously improved.
Description
Technical field
The present invention relates to a kind of analog to digital converter and a kind of capacitor averaging thereof technology, be specifically related to a kind of pipelined analog-digital converter that improves dynamic property.
Background technology
Pipelined analog-digital converter (pipelined analog-to-digital converter is hereinafter to be referred as pipeline system ADC) is a kind of a kind of critical elements that often is used in video image system, digital user loop, Ethernet transceiver or the wireless telecommunication system.The analog-to-digital conversion of pipeline system (A/D conversion; Hereinafter to be referred as the A/D conversion) can on power, speed, integrated circuit chip area, obtain good balance point, so can be used for realizing that sampling frequency is among the high-precision adc computing of MHz grade.
Fig. 1 is a conventional flow line type ADC structured flowchart; Analog signal is through after the sampling hold circuit 100; Quantizing through some grades of circuit modules 200 and back level analog to digital conversion circuit module 300; At last with the quantized values that obtain at different levels through time-delay and dislocation summation module 400 according to the addition that misplaces of time delays and weight, export final digital signal.
Fig. 2 is the single-ended structure block diagram of single-level circuit module among the conventional flow line type ADC; It is by two non-overlapping clock controls; In phase place 1,210 pairs of input signals of sampling hold circuit are sampled, and 220 pairs of input signals of submodule number conversion module slightly quantize to obtain quantized value D; In phase place 2; Subnumber weighted-voltage D/A converter 230 converts above-mentioned thick quantized value D to the corresponding simulating signal; This analog signal gets in subtracter 240 to subtract each other with input signal and obtains quantizing surplus then, and this surplus is finally exported to the next stage circuit module through the amplification of amplifier 250.Each grade circuit module is like this streamline work all; Sampling; The thick quantification, surplus is amplified, and outputs to the next stage circuit module; The output of afterbody circuit module is delivered in the back level analog-to-digital conversion module in 300, simultaneously the quantized value D of the thick quantized value D of each grade circuit module and back level analog-to-digital conversion module
bAlso to export to time-delay and dislocation summation module 400.
Fig. 3 is a kind of circuit common of realizing above-mentioned Fig. 2 function, realizes sampled input signal, the function that thick quantification and surplus are amplified.The work under two phase clock control of this circuit, in phase place 1, all switch S
1Conducting, all switch S
2Close, input signal is sampled at C
1-C
16On these 16 electric capacity, 221 pairs of input signals of comparator array quantize simultaneously, and 14 comparators are arranged in the comparator array 221, therefore export 14 bit digital thermometer code D
b, this thermometer code D
bBecome binary code D output after the coding through encoder 222; In phase place 2, all switch S
1Close all switch S
2Conducting, 14 capacitor array are respectively according to comparator battle array output D
tEverybody the decision be to link-V
RefStill+V
Ref, two remaining electric capacity connect the fixed common mode level, and capacitor C
17Be connected to the output of amplifier as feedback capacity.Through after two phase places, this circuit has just been realized the function of level circuit module 200 like this.
Suppose C
1-C
16These 16 electric capacity mate fully, i.e. C
1=C
2=... C
16=C, C
17Be twice cell capacitance, i.e. C
17=2C, switch are desirable, and operational amplifier 251 is desirable (infinitely-great open-loop gains with zero input imbalance), and so according to law of conservation of charge, can obtain output voltage is V
o=8V
i-DV
Ref,, wherein D is-7 to+7, and V
RefRealize V through differential signal
Ref=V
Reft-V
Refb, desirable surplus transmission curve is as indicated with a dotted line in Fig. 4.D
bBe this level output signal V
oThe quantized result that all grades circuit module 200 after the process and back level analog-to-digital conversion module 300 obtain; Obtain the complete transmission curve of grade circuit module 200 behind this result and the thick quantized value D weighting summation at the corresponding levels; Suppose that each grade circuit module 200 and back level analog-to-digital conversion module 300 all are desirable, so this complete transmission curve (D+D
b) should be the fixing straight line of a slope, shown in Fig. 5 dotted line.
But in actual conditions, have mismatch between each cell capacitance, this non-ideal factor can cause the deterioration of transmission curve, and shown in the solid line among Fig. 4 and Fig. 5, this situation will make the performance of analog-to-digital convertor variation.
Summary of the invention
The object of the present invention is to provide a kind of pipelined analog-digital converter that improves dynamic property; Through the order of using pseudo random number to come capacitor array in the STOCHASTIC CONTROL subseries weighted-voltage D/A converter; The error randomization that capacitance mismatch is caused, thus influence reduced to the ADC dynamic property.
The technical scheme that the present invention adopts is: a kind of pipelined analog-digital converter that improves dynamic property; Comprise pipeline system ADC level circuit module, this pipeline system ADC level circuit module comprises sampling hold circuit, sub-adc converter, subnumber weighted-voltage D/A converter, subtracter, surplus amplifier, barrel shifter, decoder and pseudorandom number generator;
Said pseudorandom number generator is used for producing pseudo random number;
Said decoder is used for the binary format pseudo random number of input is translated into corresponding signal;
Said barrel shifter is used for the wheel that the control signal of subseries weighted-voltage D/A converter is carried out at random according to pseudo random number is changeed.
Workflow is following: input signal gets into sampling hold circuit and submodule number conversion module simultaneously; Submodule number conversion module is carried out the quantification of certain precision to input signal; The binary code that quantizes is directly exported; And thereby the thermometer code that quantizes to obtain is controlled its output voltage through barrel shifter displacement back entering subnumber mould modular converter, and the output of sampling hold circuit and subnumber mould modular converter is through exporting to next stage after subtracter and the surplus amplifier.Wherein barrel shifter is controlled by pseudo random number the displacement figure place of thermometer code, and just the figure place of displacement is at random each time, and pseudo random number is produced by pseudorandom number generator and decoder.
Beneficial effect: analog circuit of the present invention is simple; Only many pseudorandom number generator, decoder and barrel shifters on traditional structure; And the work influence to traditional structure is less; Just increased the time-delay of a barrel shifter, this technology can obviously improve the ADC linearity, improves its dynamic property.
Description of drawings
Fig. 1: traditional pipeline ADC structured flowchart;
Fig. 2: traditional pipeline ADC middle rank circuit module structured flowchart;
Fig. 3: traditional pipeline ADC middle rank circuit module circuit diagram;
Fig. 4: traditional pipeline ADC middle rank circuit module surplus transmission curve;
Fig. 5: traditional pipeline ADC middle rank circuit module complete transmission curve;
Fig. 6: pipeline ADC middle rank circuit module structured flowchart of the present invention;
Fig. 7: pipeline ADC middle rank circuit module circuit diagram of the present invention;
Fig. 8: capacitor averaging technology sketch map in the pipeline ADC of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described further:
As shown in Figure 6; Pipeline ADC level circuit module 200 of the present invention has increased barrel shifter 260, decoder 270 and pseudorandom number generator 280 on the basis of original sampling hold circuit 210, sub-adc converter 220, subnumber weighted-voltage D/A converter 230, subtracter 240 and surplus amplifier 250.This structure is worked under the control of two mutually non-overlapping clocks, in phase place 1, and 210 pairs of inputs of sampling hold circuit analog signal V
iSample, 220 pairs of inputs of sub-adc converter analog signal quantizes, and obtains binary system output D and corresponding thermometer code output D respectively
t, pseudorandom number generator 280 produces pseudo random number PN, and pseudo random number PN obtains R after translating through decoder 270, the thermometer code output D of sub-adc converter 220
tThrough becoming D behind the barrel shifter 260 displacement R positions
Tr, get into subnumber weighted-voltage D/A converter 230; In phase place 2, subnumber weighted-voltage D/A converter 230 is according to the output D of barrel shifter 260
TrThe output aanalogvoltage, subtracter 240 will be imported analog signal V then
iDeduct the surplus that this aanalogvoltage is slightly quantized, surplus amplifier 250 amplifies this surplus certain multiple and is output as V
o
As shown in Figure 7, be the difference channel sketch map of realizing 3.5 level circuit modules, by comparator array 221, encoder 222, barrel shifter 260, pseudorandom number generator 270, decoder 280, two groups of C
1~ C
17Electric capacity, amplifier 551 and switch S
1With S
2Form.
Comparator array 221 is made up of 14 comparators, and the turnover level of 14 comparators is respectively-13/16V
Ref,-11/16V
Ref13/16V
RefAnalog signal gets into comparator array 221, and each comparator in the comparator array will draw comparative result according to the size of this signal, if input signal is greater than comparator turnover level then export 1; Otherwise export 0, so comparator array 221 is with direct output temperature sign indicating number D
t, this thermometer code D
tTranslate into binary code D through encoder 222 and export to time-delay and dislocation summation module 400.
Same, this circuit also is operated under the two mutually non-overlapping clocks, in phase place 1, and all switch S
1Conducting, all switch S
2Turn-off, the input analog signal is sampled 16 capacitor C
1~ C
16On, to import analog signal simultaneously and get into comparator array 221, the comparative result of each comparator obtains thick quantized value D at the corresponding levels through encoder 222, also obtains thermometer code D simultaneously
t, pseudorandom number generator 280 produces pseudo random number PN, and pseudo random number PN obtains R after translating through decoder 270, the thermometer code output D of sub-adc converter 220
tThrough becoming D behind the barrel shifter 260 displacement R positions
TrIn phase place 2, all switch S
1Turn-off all switch S
2Conducting, capacitor C
17Lower shoe is linked the output of amplifier 251 as feedback capacity, capacitor C
1~ C
14Lower shoe according to D
TrBe connected respectively on the reference level, work as D
TrThe i position be 1, i.e. D
Tri=1 o'clock, the cell capacitance C of P end
iBe connected to high reference level V
ReftBe taken in D
TrThe i position be 0, i.e. D
Tri=0 o'clock, the cell capacitance C of P end
iBe connected to high reference level V
RefbOn, N end unit electric capacity is opposite with P end annexation, and two remaining electric capacity meet fixed common mode level, C like this
1~ C
16, C
17Formed a degenerative closed-loop path with amplifier 251, surplus has been amplified corresponding multiple output.
Suppose C
1~ C
16These 16 electric capacity mate fully, i.e. C
1=C
2=... C
16=C, C
17Be twice cell capacitance, i.e. C
17=2C, switch are desirable, and operational amplifier 251 is desirable (infinitely-great open-loop gains with zero input imbalance), and so according to law of conservation of charge, can obtain output voltage is V
o=8V
iDV
Ref,, wherein D is-7 to+7, and V
RefRealize V through differential signal
Ref=V
Reft-V
Refb, desirable surplus transmission curve is as indicated with a dotted line in Fig. 4.D
bBe this level output signal V
oThe quantized result that all grades circuit module 200 after the process and back level analog-to-digital conversion module 300 obtain; Obtain the complete transmission curve of grade circuit module 200 behind this result and the thick quantized value D weighting summation at the corresponding levels; Suppose that each grade circuit module 200 and back level analog-to-digital conversion module 300 all are desirable, so this complete transmission curve (D+D
b) should be the fixing straight line of a slope, shown in Fig. 5 dotted line.
Before using the capacitor averaging technology, consider the mismatch of C1～C14 capacitor array, the input-output function of level circuit module 200 can depart from V
o=8V
i-DV
Ref, capacitance mismatch will cause actual transmission curve error to occur, shown in the solid line among Fig. 4, and the transmission curve (D+D of whole ADC
b) shown in the solid line among Fig. 5, at the threshold level place of each comparator trip point appears, and no longer continuous, these fixing errors will cause the degradation of ADC.
After using the capacitor averaging technology, the thermometer code of sub-adc converter 220 output D
tThrough becoming D behind the barrel shifter 260 displacement R positions
Tr, concrete displacement mode is as shown in Figure 8.Wherein R is a random number, can translate by pseudorandom number generator 270 generations and through decoder 280 to obtain.Suppose the thermometer code output D of sub-adc converter 220
tPreceding n position be 1, promptly 1 ~ n position is 1, all the other positions are 0, are that (1+R) ~ (n+R) position is 1 through becoming behind the barrel shifter 260 displacement R positions, all the other positions are 0, are the situation of R=4 and n=5 among Fig. 8.
C
1~ C
14The connection status of cell capacitance array is by D
TrConfirm, work as D
TrThe i position be 1, i.e. D
Tri=1 o'clock, the cell capacitance C of P end
iBe connected to high reference level V
ReftBe taken in D
TrThe i position be 0, i.e. D
Tri=0 o'clock, the cell capacitance C of P end
iBe connected to high reference level V
RefbOn, N end unit electric capacity connection status is opposite with the P end.If the situation among Fig. 7, P holds C
5~ C
9Be connected to V
Reft, C
1~ C
4And C
10~ C
14Be connected to V
Refb, N end electric capacity connection status is opposite with the P end.So originally, the fixed error that causes of capacitance mismatch is at thermometer code D
tWheel changes D into
TrThe back by randomization, thereby the equivalence lifting the dynamic property of ADC.
Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention, can also make some improvement and retouching, these improvement and retouching also should be regarded as protection scope of the present invention.The all available prior art of each part not clear and definite in the present embodiment realizes.
Claims (1)
1. pipelined analog-digital converter that can improve dynamic property; Comprise pipeline system ADC level circuit module; This pipeline system ADC level circuit module comprises sampling hold circuit, sub-adc converter, subnumber weighted-voltage D/A converter, subtracter, surplus amplifier, it is characterized in that: also include barrel shifter, decoder and pseudorandom number generator;
Said pseudorandom number generator is used for producing pseudo random number;
Said decoder is used for the binary format pseudo random number of input is translated into corresponding signal;
Said barrel shifter is used for the wheel that the control signal of subseries weighted-voltage D/A converter is carried out at random according to pseudo random number is changeed.
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Cited By (12)
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| CN104639167A (en) * | 2015-02-04 | 2015-05-20 | 东南大学 | Comparator applied to low-power-consumption Pipeline ADCs (analog-to-digital converter) |
| CN105635606A (en) * | 2014-11-26 | 2016-06-01 | 全视科技有限公司 | Method and system for implementing correlated multi-sampling with improved analog-to-digital converter linearity |
| CN106130552A (en) * | 2016-06-16 | 2016-11-16 | 武汉芯泰科技有限公司 | A kind of pipelined analog-digital converter |
| CN106209099A (en) * | 2016-06-28 | 2016-12-07 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
| CN106571821A (en) * | 2015-10-13 | 2017-04-19 | 上海贝岭股份有限公司 | Assembly line ADC forestage calibrating method |
| CN106788437A (en) * | 2015-11-20 | 2017-05-31 | 上海贝岭股份有限公司 | The method of the sampling rate of flow-line modulus converter and raising analog-digital converter |
| CN107346973A (en) * | 2017-07-07 | 2017-11-14 | 中国电子科技集团公司第二十四研究所 | A kind of production line analog-digital converter based on DAC and Sub ADC sampling network time-sharing multiplexs |
| WO2017214955A1 (en) * | 2016-06-14 | 2017-12-21 | 中国电子科技集团公司第二十四研究所 | Error compensation correction device for use in pipeline analog to digital converter |
| CN110690902A (en) * | 2019-09-25 | 2020-01-14 | 电子科技大学 | Random truncation-based time-interleaved ADC mismatch optimization method |
| WO2020238227A1 (en) * | 2019-05-29 | 2020-12-03 | 中国电子科技集团公司第二十四研究所 | Multi-bit resolution sub-pipeline structure for measuring jump magnitude of transmission curve |
| CN112511169A (en) * | 2020-12-16 | 2021-03-16 | 东南大学 | Production line ADC dynamic compensation system and method based on Sigma-Delta modulator |
| CN112913144A (en) * | 2021-01-12 | 2021-06-04 | 尼奥耐克索斯有限私人贸易公司 | Analog-to-digital converter for differential output voltage and analog-to-digital conversion method |
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| CN105635606A (en) * | 2014-11-26 | 2016-06-01 | 全视科技有限公司 | Method and system for implementing correlated multi-sampling with improved analog-to-digital converter linearity |
| CN105635606B (en) * | 2014-11-26 | 2019-01-01 | 豪威科技股份有限公司 | Implement the correlation for the having improvement analog-digital converter linear method and system sampled more |
| CN104639167B (en) * | 2015-02-04 | 2018-01-16 | 东南大学 | A kind of comparator applied to low-power consumption Pipeline ADC |
| CN104639167A (en) * | 2015-02-04 | 2015-05-20 | 东南大学 | Comparator applied to low-power-consumption Pipeline ADCs (analog-to-digital converter) |
| CN106571821A (en) * | 2015-10-13 | 2017-04-19 | 上海贝岭股份有限公司 | Assembly line ADC forestage calibrating method |
| CN106571821B (en) * | 2015-10-13 | 2020-10-09 | 上海贝岭股份有限公司 | Foreground calibration method of pipeline ADC (analog to digital converter) |
| CN106788437B (en) * | 2015-11-20 | 2024-02-27 | 上海贝岭股份有限公司 | Pipelined analog-to-digital converter and method for increasing sampling rate of analog-to-digital converter |
| CN106788437A (en) * | 2015-11-20 | 2017-05-31 | 上海贝岭股份有限公司 | The method of the sampling rate of flow-line modulus converter and raising analog-digital converter |
| US10735014B2 (en) | 2016-06-14 | 2020-08-04 | China Electronic Technology Corporation, 24Th Research Institute | Error compensation correction device for pipeline analog-to-digital converter |
| WO2017214955A1 (en) * | 2016-06-14 | 2017-12-21 | 中国电子科技集团公司第二十四研究所 | Error compensation correction device for use in pipeline analog to digital converter |
| CN106130552A (en) * | 2016-06-16 | 2016-11-16 | 武汉芯泰科技有限公司 | A kind of pipelined analog-digital converter |
| CN106130552B (en) * | 2016-06-16 | 2023-06-23 | 武汉芯泰科技有限公司 | Pipelined analog-to-digital converter |
| CN106209099B (en) * | 2016-06-28 | 2019-06-04 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
| CN106209099A (en) * | 2016-06-28 | 2016-12-07 | 中国电子科技集团公司第二十四研究所 | Production line analog-digital converter dynamic compensating device based on true random number sequence |
| CN107346973A (en) * | 2017-07-07 | 2017-11-14 | 中国电子科技集团公司第二十四研究所 | A kind of production line analog-digital converter based on DAC and Sub ADC sampling network time-sharing multiplexs |
| WO2020238227A1 (en) * | 2019-05-29 | 2020-12-03 | 中国电子科技集团公司第二十四研究所 | Multi-bit resolution sub-pipeline structure for measuring jump magnitude of transmission curve |
| US11716091B2 (en) | 2019-05-29 | 2023-08-01 | No. 24 Research Institute of China Electronics Technology Group Corporation | Multi-bit resolution sub-pipeline structure for measuring jump magnitude of transmission curve |
| CN110690902A (en) * | 2019-09-25 | 2020-01-14 | 电子科技大学 | Random truncation-based time-interleaved ADC mismatch optimization method |
| CN110690902B (en) * | 2019-09-25 | 2022-05-17 | 电子科技大学 | Random truncation-based time-interleaved ADC mismatch optimization method |
| CN112511169A (en) * | 2020-12-16 | 2021-03-16 | 东南大学 | Production line ADC dynamic compensation system and method based on Sigma-Delta modulator |
| CN112511169B (en) * | 2020-12-16 | 2023-08-29 | 东南大学 | Pipelined ADC dynamic compensation system and method based on Sigma-Delta modulator |
| CN112913144A (en) * | 2021-01-12 | 2021-06-04 | 尼奥耐克索斯有限私人贸易公司 | Analog-to-digital converter for differential output voltage and analog-to-digital conversion method |
| CN112913144B (en) * | 2021-01-12 | 2023-12-29 | 北京苹芯科技有限公司 | Analog-to-digital converter for differential output voltage and analog-to-digital conversion method |
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Application publication date: 20121024 |