CN106571821A - Assembly line ADC forestage calibrating method - Google Patents
Assembly line ADC forestage calibrating method Download PDFInfo
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- CN106571821A CN106571821A CN201510657955.9A CN201510657955A CN106571821A CN 106571821 A CN106571821 A CN 106571821A CN 201510657955 A CN201510657955 A CN 201510657955A CN 106571821 A CN106571821 A CN 106571821A
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Abstract
The invention provides an assembly line ADC forestage calibrating method comprising the following steps: S10, detecting size relations between each sampling capacitor Cs i from a first assembly level sampling capacitor sequence Cs 1, Cs 2, Cs 3...Cs N-1, and Cs N, wherein i= 1,2, ...N; S20, ranking each sampling capacitor Cs, i from small to big, thus obtaining a ranked sampling capacitor index sequence j1, j2, j3, j4...jN, wherein jk refers to the index i of the ranked sampling capacitor Cs i, k=1,2, ...N; S30, re-ranking the sampling capacitor sequence according to the index sequence so as to obtain the new sampling capacitor sequence C 's j1, C 's jN, C 's j2, C 's jN-1, C 's j3, C 's jN-2,... C 's jM. The method can improve SFDR without sacrificing SNR and the input signal amplitude.
Description
Technical field
The present invention relates to a kind of foreground calibration methods of pipeline ADC.
Background technology
High-speed high-precision flow line ADC is the important component part of Analogous Integrated Electronic Circuits.Due to system
The reason for making technique, the sampling capacitance in ADC are constantly present unmatched problem, sampling capacitance
Mismatch the linearity of ADC can be caused to be deteriorated, SFDR is shown as on frequency spectrum
(SFDR, Spurious Free Dynamic range) is deteriorated.
The calibration algorithm for improving SFDR has dynamic capacity matching technique (DEM, dynamic
Element matching) technology, shake injection (dither injection) technology.Although they
Have an effect for preferably improving SFDR, but DEM technologies can cause signal to noise ratio (SNR,
Signal noise ratio) be deteriorated, that is to say, that DEM technologies be to sacrifice SNR as cost,
To improve SFDR.Dither injection needs to inject a stochastic signal so that input signal
Amplitude is limited, and sacrifices the amplitude range of input signal.
Need one kind under conditions of SNR and input signal amplitude is not sacrificed, improve SFDR's
Method.
The content of the invention
The present invention provides a kind of foreground calibration methods of pipeline ADC, for calibration due to son
The SFDR that the electric capacity of DAC is mismatched and caused is poor.
The foreground calibration methods of the pipeline ADC of the present invention, comprise the steps：S10. examine
Survey the sampling capacitance sequence C of the first pipelining-stageS, 1, CS, 2, CS, 3..., CS, N-1, CS, NIn each sampling electricity
Hold CS, iBetween magnitude relationship, wherein i=1,2 ..., N；S20. to each sampling capacitance CS, iPress
According to order sequence from small to large, with the index sequence of the sampling capacitance after being sorted
J1, j2, j3, j4 ..., jN, wherein jk represent the sampling capacitance C after sequenceS, iIndex i,
K=1,2 ..., N；S30. the sampling capacitance sequence is arranged again according to the index sequence
Sequence, with the sampling capacitance sequence after being calibrated
C′S, j1, C 'S, jN, C 'S, j2, C 'S, jN-1, C 'S, j3, C 'S, jN-2..., C 'S, jM, wherein when N is even number
M=N/2+1, the M=(N+1)/2 when N is odd number.
Further, step S10 includes：S11. disconnect the sub- ADC of first pipelining-stage
And the connection between sub- DAC, the input of the sub- DAC is connected to the one-hot encoding of N-bit
Enumerator；S12. the input of first pipelining-stage is set to into fixed voltage V1；S13. it is described
One-hot encoding enumerator increases to nth state from the 1st state and is input into N to the sub- DAC successively
The one-hot encoding H of individual N specific heatsi, record N number of digital signal Do of the pipeline ADC outputi,
Each digital signal DoiWith each sampling capacitance CS, iCorrespond, wherein i=1,2 ..., N；
S14. with each digital signal DoiBetween magnitude relationship as each sampling capacitance CS, iIt
Between magnitude relationship.
The foreground calibration methods of the pipeline ADC of the present invention, can calibrate due to sub- ADC's
Electric capacity mismatches the poor problems of caused SFDR, can not sacrifice SNR and input letter
SFDR is improved in the case of number amplitude.
Description of the drawings
Electrical block diagrams of the Fig. 1 for pipeline ADC；
Fig. 2 is the electrical block diagram of an example of the first pipelining-stage in Fig. 1；
Fig. 3 is the electrical block diagram of dashed box part A in Fig. 2；
Fig. 4 is the electrical block diagram of dashed box part B in Fig. 3；
Fig. 5 is the flow chart of the foreground calibration methods of the pipeline ADC of the present invention；
The electrical block diagram arrived used in the step of Fig. 6 is Fig. 5 S10.
Specific embodiment
With reference to the accompanying drawings and detailed description to the present invention pipeline ADC Foreground calibration
Method is described in further detail, but not as a limitation of the invention.
The calibrating principle of the foreground calibration methods of the pipeline ADC of the present invention is entered referring initially to accompanying drawing
Row explanation.
As shown in figure 1, for the electrical block diagram of pipeline ADC.The pipeline ADC
Input signal be analogue signal Vin(nTs), output signal is digital signal Do [n], wherein TsFor
The inverse of ADC sample frequencys, n represent that n-th is sampled.The surplus of the first pipelining-stage is output as
RA(nTs), RA (nTs) digital code after late-class circuit quantifies is Rn [n], the first pipelining-stage
Sub- ADC be output as VADC1[n]。
Can be seen that by the circuit structure in Fig. 1：Do [n]=VADC1[n]+Rn[n]。
If ignoring the quantization error of sub- ADC, there are Rn [n]=RA (nTs), so as to entirely flow
The digital signal of the output of waterline ADC is represented by：
Do [n]=Vin(nTs)=VADC1[n]+Rn[n]=VADC1[n]+RA(nTs)。
Therefore, if by input signal V of pipeline ADCin(nTs) fixed value is set to, then
VADC1[n] is also fixed value, then output signal Do [n] of pipeline ADC and the first pipelining-stage
Output signal RA (nTs) is directly proportional, i.e. Do [n] ∝ RA (nTs).
In Fig. 1 an example of the first pipelining-stage circuit structure as shown in Fig. 2 the example with
First pipelining-stage illustrates the structure of the first pipelining-stage as a example by exporting 4 bits.First pipelining-stage
Input signal Vin(nTs) digital code D is exported Jing after sub- ADC quantifies[16：1], in the digital code
The value of each Di is 1 or 0.Digital code D[16：1]It is input to encoder, warp knit code
After export VADC1[n].In this example, digital code D[16：1]For the thermometer-code of 16 bits, Jing
Excess temperature meter code turns the encoder of binary code, the V of outputADC1[4：1] be 4 bits binary system
Code.
The part of dashed box A in Fig. 2 is as shown in figure 3, wherein Cs<16:1>For sampling capacitance battle array
Row, the sampling capacitance array are as shown in Figure 4.Cs, i represent ith sample electric capacity, wherein i=1～16,
The Ks of series connection with it connection, i represent the switch of control ith sample capacitive path.Cf is feedback
Electric capacity, Vref is reference voltage, and Vcm is common-mode voltage, Vin(nTs) it is the signal that comes in and goes out.
The output signal that the first pipelining-stage be can be seen that by the circuit structure of Fig. 2 and Fig. 3 can
It is expressed as：
Formula 1
Assume sampling capacitance average beI.e.：
Then the value of each sampling capacitance is represented by：
Wherein, ΔiRepresent ith sample electric capacity CS, iWith averageDeviation.
Then formula 1 can be deformed into：
Formula 2
When input signal Vin(nTs) when being set to fixed value, due to ideally sampling capacitance array
Cs<16:1>It is also fixed value with feedback capacity Cf, the value of Di is also fixed value i.e. 1 or 0,
Therefore, the deviation delta of output signal RA (nTs) of the first pipelining-stage and sampling capacitanceiIt is directly proportional, i.e.,
RA(nTs)∝-Δi。
And the output signal of output signal Do [n] and the first pipelining-stage due to pipeline ADC
RA (nTs) is directly proportional, then can obtain the deviation delta of Do [n] and sampling capacitanceiIt is directly proportional, i.e.,
Do[n]∝-Δi。
Therefore, it can using the principle, when input signal Vin(nTs) for fixed value when, by inspection
The size of output signal Do [n] is surveyed, the size of the deviation of sampling capacitance is judged.So as to pass through weight
The new path to sampling capacitance carries out gating sequence, reaches the purpose for calibrating the pipeline ADC.
With reference to Fig. 5, it is the foreground calibration methods of the pipeline ADC of the present invention, including：
Step S10：Detect the sampling capacitance sequence of the first pipelining-stage
CS, 1, CS, 2, CS, 3..., CS, N-1, CS, NIn each sampling capacitance CS, iBetween magnitude relationship, wherein
I=1,2 ..., N.
Step S20：Each sampling capacitance is sorted according to order from small to large, after being sorted
Sampling capacitance index sequence j1, j2, j3, j4 ..., jN, wherein jk represent sequence after sampling electricity
Hold CS, iIndex i, k=1,2 ..., N.
Step S30：Sampling capacitance sequence is resequenced according to index sequence, to obtain school
Sampling capacitance sequence C ' after standardS, j1, C 'S, jN, C 'S, j2, C 'S, jN-1, C 'S, j3, C 'S, jN-2..., C 'S, jM, wherein when
M=N/2+1 when N is even number, the M=(N+1)/2 when N is odd number.
Analyzed by principles above, output signal Do of pipeline ADCiWith each sampling electricity
The deviation delta of appearanceiIt is directly proportional, therefore, detect each sampling capacitance CS, iBetween magnitude relationship just can be with
By output signal Do for detecting pipeline ADCiBetween magnitude relationship realizing.Specifically,
Step S10 can include：
Step S11：As shown in fig. 6, disconnect the first pipelining-stage sub- ADC and sub- DAC it
Between connection, the input of sub- DAC is connected to into the one-hot encoding enumerator of N-bit.
Step S12：The input of the first pipelining-stage is set to into fixed voltage V1。
Step S13：One-hot encoding enumerator increases to nth state successively to sub- DAC from the 1st state
It is input into the one-hot encoding H of N number of N specific heatsi, record N number of digital signal Do of pipeline ADC outputi,
Each digital signal DoiWith each sampling capacitance C in sampling capacitance sequenceS, iCorrespond and its size
Relationship consistency, wherein i=1,2 ..., N.
Step S14：With each digital signal DoiBetween magnitude relationship as each sampling capacitance CS, iIt
Between magnitude relationship.
Before the pipeline ADC of the present invention is specifically described below according to a specific embodiment
Platform calibration steps.
In this embodiment, in N=16, i.e. sampling capacitance sequence, the number of sampling capacitance is 16
Individual, the bit number of one-hot encoding is 16.
Step S10
As shown in fig. 6, the connection between the sub- ADC and sub- DAC of the first pipelining-stage of disconnection,
The input of sub- DAC is connected to into the one-hot encoding enumerator of 16 bits.By the first pipelining-stage
Input is set to fixed voltage V1(preferably fixed voltage V1Satisfaction -15/16Vref<V1<
- 13/16Vref, wherein Vref are reference voltages), 16 bit one-hot encoding enumerators are according to from the 1st
State increases to the order of nth state, is sequentially output the one-hot encoding H of 16 bitsi, i.e., according to
0x0001、0x0002、0x0004、0x0008、0x0010、……、0x1000、0x2000、
The order of 0x4000,0x8000, is input into 1 one-hot encoding H to sub- DAC every timei, while successively
Record the digital signal Do of each pipeline ADC outputi, i=1,2 ..., 16 totally 16 times.
N-th is input into one-hot encoding HnWhen, the sampling capacitance of gating is CS, n, the digital signal of output
It is Don, therefore, 16 digital signal Doi(Do1, Do2, Do3..., Do15, Do16) with adopt
Each sampling capacitance C in sample electric capacity sequenceS, i(CS, 1, CS, 2, CS, 3..., CS, 15, CS, 16) it is one a pair
Answer.
According to formula 2, when the one-hot encoding of the 1st output of one-hot encoding enumerator is 0x0001,
The residual signal of the output of the first pipelining-stage the 1st time is：
In the same manner, it is when the one-hot encoding of the 2nd output of one-hot encoding enumerator is 0x0002, first-class
The residual signal of the output of water level the 2nd time is：
By that analogy, when the one-hot encoding of the 16th output of one-hot encoding enumerator is 0x8000,
The residual signal of the output of the first pipelining-stage the 16th time is：
It is various as can be seen that the residual signal RA of the first pipelining-stage output by more thaniWith sampling capacitance
Deviation deltaiIt is directly proportional.Again due to the residual signal RA of the first pipelining-stage outputiWith pipeline ADC
The digital signal Do of outputiIt is directly proportional (in the case where the quantization error of ADC is ignored), therefore,
Digital signal DoiWith with its corresponding sampling capacitance CS, iBetween be also directly proportional, i.e. digital signal Doi
Between magnitude relationship with its one-to-one sampling capacitance CS, iBetween magnitude relationship be consistent
's.
Therefore, it can with each digital signal DoiBetween magnitude relationship replace each sampling capacitance CS, iIt
Between magnitude relationship, to each sampling capacitance CS, iIt is ranked up.
Step S20
To 16 sampling capacitance CS, iAccording to order sequence from small to large, the i.e. one-hot encoding to being input into
The digital signal Do of 16 pipeline ADC outputs from 0x0001 to 0x8000i
(Do1, Do2, Do3..., Do15, Do16), it is ranked up according to order from small to large, obtains
Digital signal sequences Do after sequencejk(Doj1, Doj2, Doj3..., Doj15, Doj16), so as to
Sampling capacitance C to after sequenceS, iIndex sequence J (j1, j2, j3, j4 ..., j16).Wherein jk tables
Show the sampling capacitance C after sequenceS, iIndex i, k=1,2 ..., 16.
Illustrated with an example.For example, by 16 DoiBy the number after arranging from small to large
Word signal sequence DojkIt is [Do1 Do5 Do2 Do16 Do12 Do3 Do7 Do6 Do4 Do9
Do8 Do11 Do13 Do14 Do15 Do10], that is, the sampling capacitance C after sortingS, iIndex sequence
J is [1 52 16 12 376498 11 13 14 15 10].
Step S30
According to index sequence J to sampling capacitance sequence CS, iResequenced, after being calibrated
Sampling capacitance sequence C 'S, m(C′S, j1, C 'S, j16, C 'S, j2, C 'S, j15, C 'S, j3, C 'S, j14..., C 'S, j9), wherein
M=j1, j16, j2, j15, j3 ..., j9.
According to index sequence J obtained after sequence, switch arrays as shown in Figure 4 are controlled,
So that the order of each sampling capacitance gating meets the sampling capacitance sequence C ' after calibrationS, mEven if,
Sampling capacitance after must calibrating meets following relation：
C′S, 1=CS, j1, C 'S, 2=CS, j16, C 'S, 3=CS, j2, C 'S, 4=CS, j15,
C′S, 5=CS, j3, C 'S, 6=CS, j14, C 'S, 7=CS, j4, C 'S, 8=CS, j13,
C′S, 9=CS, j5, C 'S, 10=CS, j12, C 'S, 11=CS, j6, C 'S, 12=CS, j11,
C′S, 13=CS, j7C′S, 14=CS, j10, C 'S, 15=CS, j8, C 'S, 16=CS, j9。
According to examples detailed above, after being calibrated after sampling capacitance sequence is resequenced
Electric capacity sequence C 'S, m：
C′S, 1=C1, C 'S, 2=C10, C 'S, 3=C5, C 'S, 4=C15,
C′S, 5=C2, C 'S, 6=C14, C 'S, 7=C16, C 'S, 8=C13,
C′S, 9=C12, C 'S, 10=C11, C 'S, 11=C3, C 'S, 12=C8,
C′S, 13=C7, C 'S, 14=C9, C 'S, 15=C6, C 'S, 16=C4。
I.e. in the work process of pipeline ADC, controlling switch array so that sampling capacitance
Gating sequence meets co-relation, so as to complete the calibration process of pipeline ADC.
The foreground calibration methods of the pipeline ADC of the present invention, Jing matlab simulating, verifyings have can
Row, and SFDR can be improved into 6～10dB under conditions of SNR is not reduced.
Above specific embodiment is only the illustrative embodiments of the present invention, it is impossible to for limiting
The present invention, protection scope of the present invention are defined by the claims.Those skilled in the art can be with
In the essence and protection domain of the present invention, various modifications or equivalent are made to the present invention,
These modifications or equivalent also should be regarded as being within the scope of the present invention.
Claims (3)
1. a kind of foreground calibration methods of pipeline ADC, it is characterised in that including following step
Suddenly：
S10. detect the sampling capacitance sequence C of the first pipelining-stageS, 1, CS, 2, CS, 3..., CS, N-1, CS, N
In each sampling capacitance CS, iBetween magnitude relationship, wherein i=1,2 ..., N；
S20. to each sampling capacitance CS, iAccording to order sequence from small to large, to be sorted
Index sequence j1 of sampling capacitance afterwards, wherein j2, j3, j4 ..., jN, jk represent the sampling after sequence
Electric capacity CS, iIndex i, k=1,2 ..., N；
S30. the sampling capacitance sequence is resequenced according to the index sequence, with
Sampling capacitance sequence C ' to after calibrationS, j1, C 'S, jN, C 'S, j2, C 'S, jN-1, C 'S, j3, C 'S, jN-2..., C 'S, jM, its
In when N be even number when M=N/2+1, when N be odd number when M=(N+1)/2.
2. foreground calibration methods of pipeline ADC according to claim 1, its feature
It is that step S10 includes：
S11. the connection between the sub- ADC and sub- DAC of first pipelining-stage is disconnected, it is described
The input of sub- DAC is connected to the one-hot encoding enumerator of N-bit；
S12. the input of first pipelining-stage is set to into fixed voltage V1；
S13. the one-hot encoding enumerator increases to nth state successively to the son from the 1st state
DAC is input into the one-hot encoding H of N number of N specific heatsi, record the N number of of the pipeline ADC output
Digital signal Doi, each digital signal DoiWith each sampling capacitance CS, iCorrespond, its
Middle i=1,2 ..., N；
S14. with each digital signal DoiBetween magnitude relationship as each sampling capacitance
CS, iBetween magnitude relationship.
3. foreground calibration methods of pipeline ADC according to claim 2, its feature
It is, the fixed voltage V1Meet -15/16Vref ＜ V1＜ -13/16Vref, wherein Vref are institute
State the reference voltage of the first pipelining-stage.
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