CN106899300B

CN106899300B - Redundancy cyclic averaging method for successive approximation analog-to-digital converter

Info

Publication number: CN106899300B
Application number: CN201710080955.6A
Authority: CN
Inventors: 樊华; 李大刚; 胡达千; 岑远军; 苏华英
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2017-02-15
Filing date: 2017-02-15
Publication date: 2020-05-12
Anticipated expiration: 2037-02-15
Also published as: CN106899300A

Abstract

The invention discloses a method for improving the redundancy cyclic average of an SFDR (resistive-capacitive successive approximation analog-to-digital converter), relates to the fields of microelectronics and solid electronics, and particularly relates to a method for setting a capacitor in the SFDR in the field. The capacitor mismatch correction technology is firstly considered to be easy to realize on chip, a correction scheme based on an LMS algorithm is high in precision and good in correction effect, but the complexity of the algorithm is increased even is not converged if initial values are selected improperly, and the correction scheme is not easy to realize on chip.

Description

Redundancy cyclic averaging method for successive approximation analog-to-digital converter

Technical Field

The invention relates to the field of microelectronics and solid electronics, in particular to a capacitor setting method in a resistance-capacitance type successive approximation analog-digital converter in the field.

Background

An ADC is a "bridge" of analog systems and Digital Signal Processing (DSP). ADCs are generally classified into a full parallel analog-to-digital converter (Flash ADC), a Pipeline analog-to-digital converter (Pipeline ADC), an oversampling analog-to-digital converter (Σ Δ ADC), and a successive approximation analog-to-digital converter (SAR ADC). Comparing several types of pipelines, oversampling, Flash, etcADC and SAR ADC have the advantages of simple structure, small area, easy on-chip integration and the like. However, due to the limitation of the current process conditions, the capacitor can only meet the matching precision of 10 bits, and high precision is not easy to realize, so that the correction technology is essential in high-precision ADC design to overcome the process defects. How to realize an efficient capacitance mismatch correction technology on a chip is a difficult problem which must be faced in the design of an ultra-high precision ADC. The capacitance mismatch correction technique generally adopts the following three design schemes: scheme 1 is an auxiliary DAC foreground correction method, including documents A.T.Nguyen, J.xu and Z.Yang, and' A14-bit 0.17mm²SAR ADC in 0.13 μm CMOSfor high precision neutral recording, in Proc. of IEEE CICC, pp.1-4,2015. the method adopts DAC foreground correction technology to correct capacitor mismatch error, and the performance after correction is obviously improved, but the correction DAC not only has large power consumption and area, but also needs to interrupt the normal work of the analog-to-digital converter. Nevertheless, DAC-based correction schemes are currently the most mature, stable, successful, and easy to implement on-chip. Scheme 2 is a slow and accurate auxiliary ADC calibration method, including documents s.chen, r.brodersen, "A6-bit 600-MS/s 5.3-mwasychronous ADC in 0.13 μm CMOS," IEEE Journal of Solid-State Circuits,2006,41(12): 2669-2680. the slow and accurate auxiliary ADC calibration method uses a slow and accurate auxiliary ADC to convert the input voltage together with the main ADC, the output of the auxiliary ADC is used as a reference for the main ADC output, and the "minimum mean square error" algorithm adjusts the parameter to be calibrated of the main ADC according to the output value of the auxiliary ADC, so that the difference between the two ADC outputs becomes smaller and smaller, and finally converges. The auxiliary ADC correction technology has high precision and is easy to integrate on a chip, but because the correction method needs to design another more precise auxiliary ADC besides the main ADC, the complexity of design is increased, and the power consumption and the area of a chip are also increased. Scheme 3 is a method for correcting inserted pseudo-random (PN) sequences, which is disclosed in Y.Zhou, B.Xu, Y.Chiu, "A12 Bit 160MS/s Two-Step SAR ADC With Background Bit-Weight Calibration Using a Time-domain simulation Detector," IEEE Journal of Solid-State Circuits,2015,50(4): 920-931. the method is implemented by pseudo-random sequences and input signalsThe pseudo-random sequence is transmitted in the analog-to-digital converter, information such as capacitance error is carried on the amplitude of the pseudo-random sequence, digital output of the analog-to-digital converter is processed in a digital domain, circuit error information carried on the pseudo-random sequence is extracted by an error estimation module, the digital output is corrected by an error correction module according to the estimated value of the circuit error, and finally the inserted pseudo-random sequence is eliminated in the digital output to obtain correct digital output. Although the correction algorithm for inserting a pseudo-random (PN) sequence has high accuracy, it is not easy to converge and to implement on-chip.

The successive approximation analog-to-digital converter has various types, and under a specific process, it is one of the key technologies of the SAR ADC design to select a proper circuit structure and the size of the passive element to meet the matching requirement. According to the quantization method, the SAR ADC is mainly classified into a charge redistribution type and a hybrid resistance capacitance type. For the charge redistribution type, the number of internal capacitors is exponentially increased along with the increase of digits, and the area is large, so that a high-precision successive approximation analog-to-digital converter usually adopts a mixed resistance-capacitor structure, in the mixed resistance-capacitor structure, two elements of a resistor and a capacitor are adopted, and a high-order DAC and a low-order DAC are respectively formed by a binary capacitor array and a resistor string, so that the total capacitance value is smaller than that of the binary capacitor structure with the same precision, the area of the capacitor array is effectively reduced, the area is reduced, and the speed is increased. The hybrid resistance-capacitance type has the advantages of no floating node, good linearity and capability of improving the static characteristic of the analog-digital converter, so that the hybrid resistance-capacitance structure is commonly used in a high-precision successive approximation analog-digital converter with more than 14 bits. Taking a 14-bit mixed-rc successive approximation analog-to-digital converter as an example, as shown in fig. 1, the 14-bit mixed-rc successive approximation analog-to-digital converter is composed of a high-6-bit capacitor DAC and a low-8-bit capacitor DAC, and the high-6-bit capacitor DAC contains 64 unit capacitors in total.

Disclosure of Invention

The capacitor mismatch correction technology is firstly considered to be easy to realize on chip, a correction scheme based on an LMS algorithm is high in precision and good in calibration effect, but the complexity of the algorithm is increased even is not converged if initial values are selected improperly, and the correction scheme is not easy to realize on chip.

The technical scheme of the invention is a redundancy cyclic averaging method for improving the SFDR of a resistive-capacitive successive approximation analog-to-digital converter, which comprises the following steps:

step 1: respectively arranging 80 unit capacitors at a positive capacitor array and a negative capacitor array of the hybrid resistance-capacitance type successive approximation analog-to-digital converter, dividing the unit capacitors opposite to the positive capacitor array and the negative capacitor array into a group, wherein the unit capacitors are 80 groups of unit capacitors, sequentially numbering from left to right is C1, C2 and C3 … C80, dividing the front 32 groups of unit capacitors C1-C32 into 32C capacitor groups, dividing C33-C48 into 16C capacitor groups, dividing C49-C64 into redundant 16C capacitor groups, dividing C65-C72 into 8C capacitor groups, dividing C73-C76 into 4C capacitor groups, dividing C77-C78 into 2C capacitor groups, and respectively setting the last two capacitor groups as 1C capacitor groups;

step 2: performing successive approximation analog-to-digital converter bit cycle on the ith input voltage according to a binary search algorithm to obtain a conversion result, and determining the cyclic displacement of the second sampling according to the input result;

and step 3: circularly displacing 80 groups of unit capacitors according to the circularly displaced amount obtained in the step 2, and re-determining the unit capacitors in the 32C, 16C, redundant 16C, 8C, 4C, 2C, 1C and 1C capacitor groups;

and 4, step 4: under the method of dividing the capacitor bank in the step 3, carrying out bit circulation on the ith input voltage by using a traditional successive approximation analog-to-digital converter according to a binary search algorithm to obtain a conversion result;

and 5: averaging the conversion results of the step 2 and the step 4, wherein the average value is the conversion result of the ith input voltage.

The invention provides a redundancy cyclic averaging technology capable of improving the linearity of a successive approximation analog-to-digital converter, which is characterized in that: the capacitor mismatch error can be dynamically offset by only splitting the capacitor into unit capacitors, increasing redundant bits and adopting dynamic circulation and averaging techniques without introducing a minimum mean square error algorithm. The capacitance redundancy cyclic averaging method provided by the invention can avoid the continuous accumulation of capacitance mismatch errors, so that compared with the traditional correction method which relies on a correction algorithm to improve the linearity, the capacitance redundancy cyclic averaging method has the effects of simpler structure, smaller occupied chip area and easier realization on a chip.

Drawings

Fig. 1 shows a conventional 14-bit rc-type successive approximation adc.

Fig. 2 is a 14-bit rc-type successive approximation adc according to the present invention.

FIG. 3 is a schematic diagram of the capacitive redundancy and cyclic averaging method of the present invention for a positive capacitor array.

Fig. 4 is a comparison of simulation results of a conventional 14-bit rc successive approximation adc and a 14-bit rc successive approximation adc according to the present invention without stray dynamic range SFDR monte carlo.

Detailed Description

The invention provides a capacitance redundancy cyclic averaging method capable of improving linearity of a resistance-capacitance type successive approximation analog-to-digital converter. The following description will be made by taking a 14-bit rc type successive approximation analog-to-digital converter as an example. Fig. 2 shows a system structure of a 14-bit rc-type successive approximation analog-to-digital converter according to the present invention, which is composed of a high-6-bit capacitor DAC, a low-8-bit capacitor DAC, and a comparator, and is different from the conventional one in that the conventional high-6-bit capacitor DAC includes 64 unit capacitors, whereas in the 14-bit rc-type successive approximation analog-to-digital converter according to the present invention, the high-6-bit capacitor DAC includes 80 unit capacitors.

Fig. 3 shows a capacitance redundancy and cyclic averaging method according to the present invention. Based on the conventional binary capacitor array shown in fig. 3(a), a redundant capacitor 16C (fig. 3(b)) is inserted, and the binary capacitor array is divided into unit capacitor arrays, which are numbered C1 and C2 … C80 sequentially from left to right, i.e. 32C is composed of the first 32 unit capacitors C1-C32, 16C is composed of C33-C48, redundant capacitor 16C is composed of C49-C64, and by analogy, the input voltage is sampled and then converted, assuming that the ith input voltage vin (i) (i) ═ 0.0391, 32C, 8C and C are connected to VREFP according to the result of the bit cycle of the conventional successive approximation analog-to-digital converter, and the remaining capacitors are connected to VREFN, i.e. 41 unit capacitors in total are connected to VREFP, the capacitor cycle shift amount is 41, and then the ith input voltage is still converted, but the capacitor array is cyclically shifted, i.e. 32C is composed of C42-C73, 16C is composed of the last 7 capacitors C74-C80 and the first 9 capacitors C1-C9, the redundancy 16C is composed of C10-C25, and so on, the reordered capacitors are bit-cycled according to the binary search algorithm of the conventional successive approximation analog-to-digital converter, assuming that after the conversion is completed, 41 unit capacitors are connected to VREFP, the shift amount is still 41, i.e. at the next conversion, 32C is composed of C3-C34, 16C is composed of C35-C50, and so on, the digital codes converted twice are averaged to obtain the digital code corresponding to vin (i) finally, the next conversion is performed after the conversion of the ith input voltage vin (i), assuming that the next input voltage vin (j) is 0.0031, according to the result of the bit-cycling of the conventional successive approximation analog-to-digital converter, 32C, 8C are connected to vrp, and the remaining capacitors are connected to vrn, i.e. 40 unit capacitors are connected to VREFP, the cyclic displacement of the capacitor is 40, that is, at the next transition, 32C is composed of C43-C74, 16C is composed of the last 6 capacitors C75-C80 and the first 10 capacitors C1-C10, and so on.

The invention is characterized in that the redundancy dynamic circulation is carried out after the binary capacitor array is only split into the unit capacitors in the analog domain, which is very beneficial to the circuit realization. Compared with other capacitance error calibration methods, the method has the advantages of simple calibration circuit, no influence on the working speed of the circuit, insensitivity to working environment change and the like.

For the conventional 14-bit RC type and the present inventionMatlab simulation is carried out by the successive approximation analog-to-digital converter, the SFDR simulation result without stray dynamic range is shown in figure 4, the value of the unit capacitor is 100f, and the mismatch error of the unit capacitor

0.001 and 0.002, respectively, and the number of monte carlo simulations was 500.

Table 1 summarizes the performance comparison of the SFDR monte carlo simulation of the conventional rc successive approximation adc and the rc successive approximation adc proposed by the present invention. Table 1 shows that: compared with the traditional resistance-capacitance type successive approximation analog-to-digital converter, the unit capacitance mismatch error is reduced

When the capacitance is 0.001, the average value of the SFDR is improved by 21.7dB, and when the unit capacitance mismatch error is reduced

At 0.002, the present invention improves the average SFDR by 22.2 dB.

The invention provides a new capacitance redundancy cycle averaging technology for the traditional resistance-capacitance type successive approximation analog-to-digital converter, can realize the optimization of linearity only by splitting a capacitor into unit capacitors and performing redundancy cycle, has simple control logic and low hardware cost, and has the characteristics of simple calibration circuit, no influence on analog-to-digital conversion speed, insensitivity to working environment change and the like compared with the traditional method for improving the linearity by adopting a noise shaping technology or a correction algorithm.

Table 1: SFDR simulation comparison of traditional 14-bit SAR ADC and 14-bit SAR ADC provided by the invention

Claims

1. A method for improving the redundancy cyclic average of the SFDR of a resistive-capacitive successive approximation analog-to-digital converter comprises the following steps:

and 5: averaging the conversion results of the step 2 and the step 4, wherein the obtained average value is the conversion result of the ith input voltage.