CN106209106B - A kind of position round-robin method improving hybrid resistor capacitor type analog-to-digital converter dynamic property - Google Patents
A kind of position round-robin method improving hybrid resistor capacitor type analog-to-digital converter dynamic property Download PDFInfo
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- CN106209106B CN106209106B CN201610591962.8A CN201610591962A CN106209106B CN 106209106 B CN106209106 B CN 106209106B CN 201610591962 A CN201610591962 A CN 201610591962A CN 106209106 B CN106209106 B CN 106209106B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/40—Analogue value compared with reference values sequentially only, e.g. successive approximation type recirculation type
Abstract
A kind of position round-robin method for improving hybrid resistor capacitor type analog-to-digital converter dynamic property of the disclosure of the invention, the technical field of application is the high-precision adc in Microelectronics and Solid State Electronics field.Position round-robin method proposed by the present invention is suitable for the gradually-appoximant analog-digital converter of any structure, its core concept is to split highest order (MSB) capacitor and time high-order (MSB-1) capacitor, capacitor array is divided into four groups, each position circulation all changes capacitor order, achievees the effect that capacitance error consecutive mean.It is characterized in that: it does not need to introduce any correcting algorithm, does not need to introduce correction DAC, do not sacrifice analog-digital converter sample rate, and do not interrupt analog-digital converter normal work.Position round-robin method proposed by the present invention can carry out consecutive mean to capacitance error, therefore, compared with tradition relies on the bearing calibration of correction DAC and correcting algorithm to improve the linearity, has the effect of that structure is simpler, chip occupying area is smaller, is easier to realize on piece.
Description
Technical field
It is direct applied the present invention relates to a kind of novel gradually-appoximant analog-digital converter (SAR ADC) position round-robin method
Technical field is the high-precision adc in Microelectronics and Solid State Electronics field.
Background technique
The analog signal of real world is converted into digital signal by analog-digital converter, is a filtering, sampling is kept and volume
The process of code, analog-digital converter have been widely used in various systems on chip, and different application systems is to analog-digital converter
The requirement of energy is different, and the performance of analog-digital converter all has significant effect the stability, reliability and persistence of system.
The performance indicator of analog-digital converter is usually illustrated in terms of static parameter and dynamic parameter two, static parameter
Main includes imbalance (Offset), mistake code (Missing Code), monotonicity (Monotonicity), gain error (Gain
Error), differential nonlinearity (DNL:Differential Nonlinearity) and integral nonlinearity (INL:Integral
Nonlinearity) etc., dynamic parameter includes signal-to-noise ratio (SNR:Signal-to-Noise Ratio), signal noise distortion ratio
(SNDR:Signal-to-Noise-and-Distortion Ratio), total harmonic distortion (THD:Total Harmonic
Distortion), spurious-free dynamic range (SFDR:Spurious-Free Dynamic Range) and effective accuracy
(ENOB:Effective Number of Bits) etc..The dynamic property and input frequency, input signal width of analog-digital converter
Degree, capacitor matching and sampling rate are related.
There are many different types for gradually-appoximant analog-digital converter, and different structures need to be selected according to system requirements.By
The secondary analog-digital converter that approaches is broadly divided into capacitive binary capacitor type, three level binaries, sectional capacitance type and hybrid resistor
Capacitive four kinds.The specific capacitance number of N traditional binary capacitor arrays and three level binary capacitor arrays is with precision N
It is in exponential increase, cause binary capacitor array occupied area larger, limits the conversion speed and precision of capacitor array, and divide
The capacitor array of section capacitive structure reduces capacitor array area by way of being inserted into coupled capacitor and improves conversion speed
The advantages of degree, sectional capacitance type structure is that capacitor is small, area is small, low in energy consumption, but fractional-type coupled capacitor introduces floating section
Point and increase the complexity of layout design, it is not easy to realize high-precision, in mixing resistance capacitance structure, using resistance and
Two kinds of elements of capacitor, high-order DAC and low level DAC are made of binary capacitor array and resistance string respectively, therefore, total capacitance value ratio
The binary capacitor structure of equal accuracy and three level binary capacitance structures are all small, effectively reduce the face of capacitor array
Product, area become smaller, and speed becomes faster.The capacitive advantage of hybrid resistor and traditional binary is capacitive and three level binary capacitors
Type is the same, that is, does not have floating node, and the linearity is good, can improve the static characteristic of analog-digital converter, therefore, hybrid resistor capacitive junctions
Structure is usually used in high-precision gradually-appoximant analog-digital converter.
The matching of capacitor is to determine the key factor of gradually-appoximant analog-digital converter dynamic property, especially in high-precision
In, the matching problem of gradually-appoximant analog-digital converter capacitor is challenging always problem, this is because by current
Process conditions limitation, capacitor can only meet 10 matching precisions, it is not easy to realize high-precision, therefore high-precision Approach by inchmeal mould
Number converter depends on two methods of foreground analog correction and backstage figure adjustment, document [Z.Wang, R.Lin,
E.Gordon,H.Lakdawala,L.Carley,J.Jensen,“An in-situ temperature-sensing
interface based on a SAR ADC in 45nm LP digital CMOS for the frequency-
temperature compensation of crystal oscillators”,IEEE ISSCC Dig.Tech.Papers,
Pp.316-317, Feb 2010.] method that uses foreground analog correction, one powers on and first calculates each capacitance error, by each electricity
Hold error and be stored in register, later when gradually-appoximant analog-digital converter works normally, using correction DAC to capacitance error
It is offset, achievees the purpose that correction.The shortcomings that foreground analog correction, is to need to introduce additional correction DAC, and needs
Interrupt the normal work of analog-digital converter.Backstage figure adjustment generallys use " least mean-square error " (LMS:Least Mean
Square) algorithm carries out mismatch repair to capacitor, and based on the correcting scheme of LMS algorithm given error modeling condition
Under, precision is high and calibration effect is good, if but initial value choose improper, will lead to algorithm complexity increase, even result in algorithm not
The problems such as convergence, is not easy on piece realization.
Summary of the invention
Curve guide impeller one kind does not need to introduce correction DAC the present invention in view of the deficiencies of the prior art, does not sacrifice modulus
Converter sampling rate does not interrupt analog-digital converter normal work, and structure is simpler, chip occupying area is smaller, is easier in piece
The position round-robin method that can be improved gradually-appoximant analog-digital converter dynamic property of upper realization.Position round-robin method proposed by the present invention
Suitable for the gradually-appoximant analog-digital converter of any structure, core concept is to split highest order (MSB) capacitor and a time high position
(MSB-1) capacitor array is divided into four groups by capacitor, and each position circulation all changes capacitor order, reaches flat to capacitance error dynamic
Equal effect.12 hybrid resistor capacitor gradually-appoximant analog-digital converters to position round-robin method proposed by the present invention based on Fig. 1
It is illustrated, as shown in Figure 1,12 hybrid resistor capacitor gradually-appoximant analog-digital converters are by high 5 capacitor DAC and low 7 electricity
DAC, comparator and digital control circuit composition are hindered, compares sectional capacitance type structure, hybrid resistor capacitive structure is not due to having
Floating node, so the linearity is more preferable than segmentation capacitive structure.
The technical scheme is that a kind of position circulation side for improving hybrid resistor capacitor type analog-to-digital converter dynamic property
Method, this method comprises:
Step 1: the capacitive gradually-appoximant analog-digital converter of hybrid resistor includes: high-order capacitor DAC and low level resistance
All specific capacitances in high-order capacitor DAC are equally divided into 4 groups by DAC；When converting for the first time, first and second group of capacitor is as most
A high position, third group capacitor is as a time high position, and to position circulation is carried out after first input voltage vin (1) sampling, generation corresponds to
The output codons of first input voltage vin (1)；
Step 2: second when converting, third and fourth group of capacitor is used as highest order, and first group of capacitor is as a time high position, to the
Position circulation is carried out after two input voltage vin (2) samplings, generates the output code for corresponding to second input voltage vin (2)
Word；
Step 3: when third time is converted, first, fourth group of capacitor is used as highest order, and second group of capacitor is as a time high position, to the
Position circulation is carried out after three input voltage vin (3) samplings, generates the output code for corresponding to third input voltage vin (3)
Word；
Step 4: when the 4th conversion, second and third group of capacitor is as highest order, and the 4th group of capacitor is as time high-order, to the
Position circulation is carried out after four input voltage vin (4) samplings, generates the output code for corresponding to the 4th input voltage vin (4)
Word；
Step 5: when the 5th conversion, third and fourth group of capacitor is as highest order, and first group of capacitor is as time high-order, to the
Position circulation is carried out after five input voltage vin (5) samplings, generates the output code for corresponding to the 5th input voltage vin (5)
Word；
Step 6: when the 6th conversion, first and second group of capacitor is as highest order, and third group capacitor is as time high-order, to the
Position circulation is carried out after six input voltage vin (6) samplings, generates the output code for corresponding to the 6th input voltage vin (6)
Word；
Step 7: when the 7th conversion, second and third group of capacitor is as highest order, and the 4th group of capacitor is as time high-order, to the
Position circulation is carried out after seven input voltage vin (7) samplings, generates the output code for corresponding to the 7th input voltage vin (7)
Word；
Step 8: when the 8th conversion, first, fourth group of capacitor is as highest order, and second group of capacitor is as time high-order, to the
Position circulation is carried out after eight input voltage vin (8) samplings, generates the output code for corresponding to the 8th input voltage vin (8)
Word；
During ADC subsequent output codons, the mode of the 9th conversion is identical as first time, the mode of the tenth conversion
It is identical as second, it circuits sequentially.
The present invention proposes that a kind of position round-robin method that can improve gradually-appoximant analog-digital converter dynamic property, feature exist
In: it does not need to introduce any correcting algorithm, does not need to introduce correction DAC, do not sacrifice analog-digital converter sample rate, and do not interrupt
Analog-digital converter works normally.Position round-robin method proposed by the present invention can carry out consecutive mean to capacitance error, therefore, with biography
The bearing calibration that system dependence correction DAC improves the linearity with correcting algorithm is compared, the simpler, chip occupying area with structure
Effect that is smaller, more easily being realized on piece.
Detailed description of the invention
Fig. 1 is traditional 12 capacitive gradually-appoximant analog-digital converters of hybrid resistor.
Fig. 2 is the position round-robin method proposed by the present invention for gradually-appoximant analog-digital converter capacitor array.
Fig. 3 is the capacitive gradually-appoximant analog-digital converter SFDR Monte Carlo simulation of 12 hybrid resistors proposed by the present invention
As a result.
Fig. 4 is the capacitive gradually-appoximant analog-digital converter SFDR Monte Carlo simulation result of traditional 12 hybrid resistors.
Specific embodiment
The present invention proposes a kind of position round-robin method that can improve gradually-appoximant analog-digital converter dynamic property, as shown in Fig. 2,
(MSB) capacitor of highest order in Fig. 1 16C is split into 4C, 2C, C, C, 4C, 2C, C, C, a secondary high position (MSB-1) capacitor 8C is split into
The total capacitance 32C of 5 capacitor DAC high in Fig. 1 points are four groups by 4C, 2C, C, C, this four groups of capacitors are in Fig. 2 with different
Color indicates that first group of capacitor C13~C16 indicates that second group of capacitor C9~C12 is indicated with purple with black, third group capacitor
C5~C8 indicates that the 4th group of capacitor C1~C4 is indicated with blue with red, and every group includes 8 specific capacitances, i.e. 4C, 2C, C,
C, each position circulation use different capacitor combinations, realize the consecutive mean of capacitance error, improve dynamic property to reach
Purpose.
It converts for the first time: to progress position circulation after first input voltage vin (1) sampling, highest order (MSB) capacitor
16C is collectively constituted by first and second group of capacitor (C9~C16), and a secondary high position (MSB-1) capacitor 8C is by third group capacitor (C5~C8) group
At C2~C4 generates the output codons Dout (1) for corresponding to first input voltage vin (1) as low three capacitors；
Second of conversion: to progress position circulation after second input voltage vin (2) sampling, highest order (MSB) capacitor
16C is collectively constituted by third and fourth group of capacitor (C1~C8), and a secondary high position (MSB-1) capacitor 8C is by first group of capacitor (C13~C16)
Composition, C10~C12 generate the output codons Dout (2) for corresponding to second input voltage vin (2) as low three capacitors；
Third time is converted: to progress position circulation after third input voltage vin (3) sampling, highest order (MSB) capacitor
16C is collectively constituted by first, fourth group of capacitor (C1~C4, C13~C16), and a secondary high position (MSB-1) capacitor 8C is by third group capacitor
(C9~C12) composition, C6~C8 generate the output codons for corresponding to third input voltage vin (3) as low three capacitors
Dout(3)；
4th conversion: to progress position circulation after the 4th input voltage vin (4) sampling, highest order (MSB) capacitor
16C is collectively constituted by second and third group of capacitor (C5~C12), and a secondary high position (MSB-1) capacitor 8C is by the 4th group of capacitor (C1~C4) group
At C14~C16 generates the output codons Dout (4) for corresponding to the 4th input voltage vin (4) as low three capacitors；
5th conversion: to progress position circulation after the 5th input voltage vin (5) sampling, highest order (MSB) capacitor
16C is collectively constituted by third and fourth group of capacitor (C1~C8), and a secondary high position (MSB-1) capacitor 8C is by first group of capacitor (C13~C16)
Composition, C10~C12 generate the output codons Dout (5) for corresponding to the 5th input voltage vin (5) as low three capacitors；
6th conversion: to progress position circulation after the 6th input voltage vin (6) sampling, highest order (MSB) capacitor
16C is collectively constituted by first and second group of capacitor (C9~C16), and a secondary high position (MSB-1) capacitor 8C is by third group capacitor (C5~C8) group
At C2~C4 generates the output codons Dout (6) for corresponding to the 6th input voltage vin (6) as low three capacitors；
7th conversion: to progress position circulation after the 7th input voltage vin (7) sampling, highest order (MSB) capacitor
16C is collectively constituted by second and third group of capacitor (C5~C12), and a secondary high position (MSB-1) capacitor 8C is by the 4th group of capacitor (C1~C4) group
At C14~C16 generates the output codons Dout (7) for corresponding to the 7th input voltage vin (7) as low three capacitors；
8th conversion: to progress position circulation after the 8th input voltage vin (8) sampling, highest order (MSB) capacitor
16C is collectively constituted by first, fourth group of capacitor (C1~C4, C13~C16), and a secondary high position (MSB-1) capacitor 8C is by third group capacitor
(C9~C12) composition, C6~C8 generate the output codons for corresponding to the 8th input voltage vin (8) as low three capacitors
Dout(8)；
In ADC subsequent bit cyclic process, the 9th time conversion mode it is identical with first time, the tenth time convert mode and
Second identical, circuits sequentially.
Why the present invention can be improved dynamic property, and be based primarily upon following central idea: conventional successive is approached modulus and turned
The position circulation pattern that parallel operation generallys use are as follows: the capacitor that a certain fixation is always used to the judgement of a certain fixed bit, i.e., converted
Cheng Zhong, all circulations all use same charge redistribution scheme, cause the error introduced by capacitance mismatch always in same code
Word is constantly cumulative, and in order to avoid the error introduced by capacitance mismatch is always constantly cumulative in same code word, the present invention proposes a kind of new
The simple capacitor grouping circulation pattern easily realized of type, does not need to introduce additional DAC and corrects, and does not need any figure adjustment yet
Algorithm, it is only necessary to which the position of each position varying cyclically capacitor sequence can avoid the error of capacitance mismatch introducing always in same code
Word is constantly cumulative, to achieve the purpose that promote dynamic property.
12 resistance-capacitance types gradually-appoximant analog-digital converter SFDR simulation result proposed by the present invention is as shown in figure 3, list
Position capacitor value is 10 μ f, specific capacitance mismatch errorIt is 0.003, Monte Carlo simulation number is 200 times, and traditional
12 resistance-capacitance type gradually-appoximant analog-digital converter SFDR simulation results are as shown in Figure 4.
Table 1 summarizes 12 resistance-capacitance type gradually-appoximant analog-digital converters of tradition and 12 resistance electricity proposed by the present invention
The performance comparison of the SFDR emulation of appearance type gradually-appoximant analog-digital converter.Table 1 shows: comparing the capacitive Approach by inchmeal of traditional resistor
SFDR minimum value is improved 10.7dB by analog-digital converter, the present invention, and SFDR average value improves 8.5dB.
The present invention approaches analog-digital converter for conventional successive and proposes a kind of new position circulating technology, it is only necessary to by highest
Two capacitors are split, and all use different capacitor combinations in each position circulation, so that it may which the optimization for realizing dynamic property is compared
Conventionally employed correction DAC technique or correcting algorithm are come the method for improving dynamic property, and control logic of the present invention is simple, and hardware is opened
It sells small, power consumption and chip area can be saved.
Table 1: the SFDR of tradition 12 SAR ADC and 12 SAR ADC proposed by the present invention is compared
Claims (1)
1. a kind of position round-robin method for improving hybrid resistor capacitor type analog-to-digital converter dynamic property, this method comprises:
Step 1: the hybrid resistor capacitor type analog-to-digital converter includes: high-order capacitor DAC and low level resistance DAC, by high-order electricity
Hold all specific capacitances in DAC and be equally divided into 4 groups, group technology is that MSB capacitor in high-order capacitor DAC is split as and is removed
MSB-1 capacitor is split as except MSB capacitor by identical two group pattern of bit capacitor array except MSB capacitor and MSB-1 capacitor
Array identical with the bit capacitor array except MSB-1 capacitor is one group, and remaining bit capacitor array is one group；For the first time
When conversion, first and second group of capacitor adopts first input voltage vin (1) as a time high position as highest order, third group capacitor
Position circulation is carried out after sample, generates the output codons for corresponding to first input voltage vin (1)；
Step 2: when second of conversion, third and fourth group of capacitor is as highest order, and first group of capacitor is as a time high position, to second
Position circulation is carried out after input voltage vin (2) sampling, generates the output codons for corresponding to second input voltage vin (2)；
Step 3: when third time is converted, first, fourth group of capacitor is as highest order, and second group of capacitor is as a time high position, to third
Position circulation is carried out after input voltage vin (3) sampling, generates the output codons for corresponding to third input voltage vin (3)；
Step 4: when the 4th conversion, second and third group of capacitor is as highest order, and the 4th group of capacitor is as a time high position, to the 4th
Position circulation is carried out after input voltage vin (4) sampling, generates the output codons for corresponding to the 4th input voltage vin (4)；
Step 5: when the 5th conversion, third and fourth group of capacitor is as highest order, and first group of capacitor is as a time high position, to the 5th
Position circulation is carried out after input voltage vin (5) sampling, generates the output codons for corresponding to the 5th input voltage vin (5)；
Step 6: when the 6th conversion, first and second group of capacitor is as highest order, and third group capacitor is as a time high position, to the 6th
Position circulation is carried out after input voltage vin (6) sampling, generates the output codons for corresponding to the 6th input voltage vin (6)；
Step 7: when the 7th conversion, second and third group of capacitor is as highest order, and the 4th group of capacitor is as a time high position, to the 7th
Position circulation is carried out after input voltage vin (7) sampling, generates the output codons for corresponding to the 7th input voltage vin (7)；
Step 8: when the 8th conversion, first, fourth group of capacitor is as highest order, and second group of capacitor is as a time high position, to the 8th
Position circulation is carried out after input voltage vin (8) sampling, generates the output codons for corresponding to the 8th input voltage vin (8)；
During ADC subsequent output codons, the mode of the 9th conversion is identical with first time, the tenth mode converted and the
Secondary phase is same, circuits sequentially.
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| US9654131B1 (en) * | 2016-02-26 | 2017-05-16 | Texas Instruments Deutschland Gmbh | Capacitor order determination in an analog-to-digital converter |
| CN106877869B (en) * | 2017-02-10 | 2020-01-14 | 电子科技大学 | Capacitor sorting method capable of improving linearity of resistance-capacitance type successive approximation analog-to-digital converter |
| CN106899300B (en) * | 2017-02-15 | 2020-05-12 | 电子科技大学 | Redundancy cyclic averaging method for successive approximation analog-to-digital converter |
| CN107863966B (en) * | 2017-10-31 | 2021-02-05 | 电子科技大学 | Successive approximation analog-digital converter capacitance optimization method for intelligent sensor |
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| US7233276B1 (en) * | 2005-11-29 | 2007-06-19 | Himax Technologies, Inc. | Pipelined analog to digital converter with capacitor mismatch compensation |
| CN103873058A (en) * | 2012-12-17 | 2014-06-18 | 达斯特网络公司 | Anti-aliasing sampling circuits and analog-to-digital converters |
| CN105322966A (en) * | 2015-11-12 | 2016-02-10 | 电子科技大学 | Capacitor switching and averaging method for improving linearity of successive approximation analog-digital converter |
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| US7233276B1 (en) * | 2005-11-29 | 2007-06-19 | Himax Technologies, Inc. | Pipelined analog to digital converter with capacitor mismatch compensation |
| CN103873058A (en) * | 2012-12-17 | 2014-06-18 | 达斯特网络公司 | Anti-aliasing sampling circuits and analog-to-digital converters |
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