CN113839674B - Analog-to-digital conversion circuit - Google Patents
Analog-to-digital conversion circuit Download PDFInfo
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- CN113839674B CN113839674B CN202111120927.5A CN202111120927A CN113839674B CN 113839674 B CN113839674 B CN 113839674B CN 202111120927 A CN202111120927 A CN 202111120927A CN 113839674 B CN113839674 B CN 113839674B
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- 238000006243 chemical reaction Methods 0.000 title claims abstract description 198
- 239000000872 buffer Substances 0.000 claims abstract description 56
- 238000005070 sampling Methods 0.000 claims description 17
- 239000003990 capacitor Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 description 22
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- 238000012545 processing Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1009—Calibration
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
Abstract
The application provides an analog-to-digital conversion circuit, and relates to the technical field of analog-to-digital conversion. The analog-to-digital conversion circuit includes: a main channel, an auxiliary channel and a calibration module; wherein, the main channel includes: a main input buffer and a main analog-to-digital conversion unit, the auxiliary channel including; an auxiliary input buffer and an auxiliary analog-to-digital conversion unit; the input ends of the main input buffer and the auxiliary input buffer are used for receiving input analog signals; the output end of the main input buffer is connected with the main analog-digital conversion unit, and the output end of the auxiliary input buffer is connected with the auxiliary analog-digital conversion unit; the output ends of the main analog-digital conversion unit and the auxiliary analog-digital conversion unit are both connected with the input end of the calibration module, so that the calibration module carries out nonlinear calibration on the main digital signal output by the main analog-digital conversion unit by adopting the auxiliary digital signal obtained by the auxiliary analog-digital conversion unit, and then outputs a linear digital signal through the first output end of the calibration module. According to the embodiment of the application, the circuit structure of analog-to-digital conversion is effectively simplified, and nonlinear calibration of digital signals is realized.
Description
Technical Field
The application relates to the technical field of analog-to-digital conversion, in particular to an analog-to-digital conversion circuit.
Background
Analog-to-Digital conversion is a conversion of an Analog signal into a Digital signal, and an Analog-to-Digital Converter (ADC) for realizing the Analog-to-Digital conversion has been widely used in actual production. In the analog-to-digital conversion process, it is not easy to achieve high linearity, high bandwidth, especially if the power supply margin is limited.
In the prior art, the linearity of the analog-to-digital conversion result is improved, the analog circuit or the digital circuit can be calibrated, and different methods are adopted to solve the dynamic distortion and the static distortion from the front end of the ADC so as to improve the nonlinearity.
The dynamic and static distortion is processed, and high power supply voltage and negative voltage power supply are often needed, and the additional power supplies not only can cause high power consumption, but also can bring more burden to a power management circuit for supplying power to the analog-to-digital conversion circuit.
Disclosure of Invention
The present application aims to provide an analog-to-digital conversion circuit for solving the problems of complex structure or limited calibration bandwidth in the prior art.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, an embodiment of the present application provides an analog-to-digital conversion circuit, including: a main channel, an auxiliary channel and a calibration module; wherein, the main channel includes: a main input buffer and a main analog-to-digital conversion unit, the auxiliary channel including; an auxiliary input buffer and an auxiliary analog-to-digital conversion unit;
the input ends of the main input buffer and the auxiliary input buffer are used for receiving input analog signals; the output end of the main input buffer is connected with the main analog-to-digital conversion unit, and the output end of the auxiliary input buffer is connected with the auxiliary analog-to-digital conversion unit;
the output ends of the main analog-digital conversion unit and the auxiliary analog-digital conversion unit are both connected with the input end of the calibration module, so that the calibration module carries out nonlinear calibration on the main digital signal output by the main analog-digital conversion unit by adopting the auxiliary digital signal obtained by the auxiliary analog-digital conversion unit, and then outputs a linear digital signal through the first output end of the calibration module.
Optionally, the main input buffer and the auxiliary input buffer are input buffers with the same architecture and the same working voltage.
Optionally, the sampling frequency of the auxiliary analog-to-digital conversion unit is less than or equal to the sampling frequency of the main analog-to-digital conversion unit.
Optionally, the main channel further includes: and the input end of the first sample-and-hold circuit is connected with the output end of the main input buffer, and the output end of the first sample-and-hold circuit is connected with the input end of the main analog-to-digital conversion unit.
Optionally, the first sample-and-hold circuit includes: a first change-over switch and a first holding capacitor;
one end of the first change-over switch is an input end of the first sample hold circuit, the other end of the first change-over switch is grounded through the first holding capacitor, and a connection point between the first change-over switch and the first holding capacitor is an output end of the first sample hold circuit.
Optionally, the auxiliary channel further comprises: and the input end of the second sample-hold circuit is connected with the output end of the auxiliary input buffer, and the output end of the second sample-hold circuit is connected with the input end of the auxiliary analog-to-digital conversion unit.
Optionally, the second sample-and-hold circuit includes: a second change-over switch and a second holding capacitance;
one end of the second change-over switch is an input end of the second sample hold circuit, the other end of the second change-over switch is grounded through the second holding capacitor, and a connection point between the second change-over switch and the second holding capacitor is an output end of the second sample hold circuit.
Optionally, the main analog-to-digital conversion unit and the auxiliary analog-to-digital conversion unit are the same type of analog-to-digital conversion unit, or different types of analog-to-digital conversion units.
Optionally, if the main analog-to-digital conversion unit is a pipelined analog-to-digital conversion unit, the auxiliary analog-to-digital conversion unit is a successive approximation analog-to-digital conversion unit, and the main analog-to-digital conversion unit includes an N-stage analog-to-digital converter, N-1 margin amplifiers, and N-1 adjustment control switches; n is an integer greater than or equal to 2;
the residual output end of the former-stage analog-to-digital converter between two adjacent stages of analog-to-digital converters is connected with the input end of a residual amplifier, and the output end of the residual amplifier is connected with the input end of the latter-stage analog-to-digital converter in the two adjacent stages of analog-to-digital converters; the input end of the first-stage analog-to-digital converter is connected with the output end of the main input buffer, and the output end of the last-stage analog-to-digital converter is connected with the input end of the calibration module; each adjusting control switch is connected to a bias circuit of a residual amplifier;
and a second output end of the calibration module is connected with a control end of the adjusting control switch.
Optionally, the successive approximation analog-to-digital converter is an N-segment split analog-to-digital conversion array, and N is the same as the number of stages N of the pipelined analog-to-digital conversion unit in the main channel.
Compared with the prior art, the application has the following beneficial effects:
an embodiment of the present application provides an analog-to-digital conversion circuit, including: a main channel, an auxiliary channel and a calibration module; wherein, the main channel includes: a main input buffer and a main analog-to-digital conversion unit, the auxiliary channel including; an auxiliary input buffer and an auxiliary analog-to-digital conversion unit; and carrying out nonlinear calibration on the main digital signal output by the main channel through the auxiliary digital signal output by the auxiliary channel, and carrying out gain error calibration on the main digital signal output by the main channel by referring to the digital signal output by the auxiliary channel. In the scheme of the application, the nonlinear calibration of the main digital signal can be completed through the calibration module, so that the circuit structure of analog-to-digital conversion is effectively simplified while the normal operation of the digital-to-analog conversion circuit is ensured, and the calibration bandwidth of the nonlinear calibration of the digital signal is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 2 is a schematic structural diagram of an input buffer in an analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 3 is a flowchart of a calibration method executed by a calibration module in an analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 4 is a schematic structural diagram of another analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of another analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application;
fig. 7A and fig. 7B are graphs comparing transmission characteristic curves before and after calibration of digital signals of the analog-to-digital conversion circuit according to the embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, based on the embodiments herein, which would be apparent to one of ordinary skill in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present application, it should be noted that, if the terms "upper," "lower," "inner," "outer," and the like indicate an azimuth or a positional relationship based on that shown in the drawings, or an azimuth or a positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it does not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
It should be noted that the features of the embodiments of the present invention may be combined with each other without conflict.
In order to realize nonlinear calibration of digital signals in the analog-to-digital conversion process, in the scheme of the application, the analog-to-digital conversion circuit is provided, and nonlinear calibration is carried out on the output digital signals passing through the main channel through the output digital signals of the auxiliary channel, so that the efficiency of nonlinear calibration is improved.
The analog-to-digital conversion circuit provided in the embodiment of the present application is explained by a specific example.
Fig. 1 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application. As shown in fig. 1, the analog-to-digital conversion circuit includes a main channel, an auxiliary channel, and a calibration module 103; wherein, the main channel includes: a main input buffer 101 and a main analog-to-digital conversion unit 102, the auxiliary channel including; a secondary input buffer 104 and a secondary analog-to-digital conversion unit 105.
The output end of the main input buffer 101 is connected with the main analog-to-digital conversion unit 102, and the output end of the auxiliary input buffer 104 is connected with the auxiliary analog-to-digital conversion unit 105; the outputs of the main analog-to-digital conversion unit 102 and the auxiliary analog-to-digital conversion unit 105 are both connected to the input of the calibration module 103, while the inputs of the main input buffer 101 and the auxiliary input buffer 104 are both used for receiving the input analog signal, and the first output of the calibration module 103 is used for outputting the linear digital signal.
In a possible example, the sampling frequency of the primary analog-to-digital conversion unit 102 is different from the sampling frequency of the secondary analog-to-digital conversion unit 105. Optionally, the sampling frequency of the auxiliary analog-to-digital conversion unit 105 is smaller than or equal to the sampling frequency of the main analog-to-digital conversion unit 102, meanwhile, the sampling frequency of the auxiliary analog-to-digital conversion unit 105 depends on the overall power consumption and design complexity of the circuit, and if the overall power consumption of the circuit is lower, the sampling frequency of the auxiliary analog-to-digital conversion unit 105 can be reduced, for example, the sampling frequency of the main analog-to-digital conversion unit 102 is 1GS/S, the sampling frequency of the auxiliary analog-to-digital conversion unit 105 is 125MS/S, and the sampling frequency of the auxiliary analog-to-digital conversion unit 105 is smaller while ensuring that analog-to-digital conversion is performed normally, so that the power consumption of an auxiliary channel can be reduced, and further, the power consumption of the whole analog-to-digital conversion circuit can be reduced.
Alternatively, the primary input buffer and the secondary input buffer are input buffers having the same architecture, the same operating voltage and using low voltage power. By way of example, the operating voltages of the primary input buffer 101 and the secondary input buffer 104 may both be set to within 1V to reduce the power of the operating circuit and the complexity of the power supply regulation circuit. Meanwhile, the buffers with the same structure can facilitate the design of the analog-to-digital conversion circuit, and ensure that the input analog signals are still the same analog signals after being output by the main input buffer 101 and the auxiliary input buffer 104.
Optionally, fig. 2 is a schematic structural diagram of an input buffer in an analog-to-digital conversion circuit according to an embodiment of the present application. As shown in fig. 2, the input buffer includes: the first source follower M1 and the second source follower M2, wherein the first source follower M1 is an N-type MOS tube, the second source follower M2 is a P-type MOS tube, the first end of the first source follower M1 is connected with a power supply, the second end of the first source follower M1 is connected with the first end of the second source follower M2 and is connected with the output end of the input buffer, the second end of the second source follower M2 is grounded, and the control end of the first source follower M1 and the control end of the second source follower M2 are connected with the input end of the input buffer.
Optionally, the first source follower M1 and the second source follower M2 in the input buffer are increased in size. By increasing the size of the first source follower M1 and the second source follower M2 in the input buffer, the operating current can be increased, thereby increasing the sampling bandwidth. The large enough sampling bandwidth can greatly weaken dynamic distortion, the residual influence of the dynamic distortion after weakening can be ignored, and the whole analog-to-digital conversion circuit only needs to complete nonlinear calibration of static distortion, so that the nonlinear calibration bandwidth can be improved. And simultaneously, the holding capacitance of the load end can be reduced to further increase the bandwidth.
When an analog signal to be analog-to-digital converted is input, the input current of the input end is increased, so that the sampling broadband margin is increased. The large enough sampling bandwidth margin can greatly weaken dynamic distortion, the residual influence of the dynamic distortion after weakening can be ignored, and the whole analog-to-digital conversion circuit only needs to finish nonlinear correction and calibration of static distortion, so that the calibration efficiency can be improved.
In the whole analog-digital conversion circuit, the input analog signals are respectively subjected to analog-digital conversion processing of a main channel and analog-digital conversion processing of an auxiliary channel to obtain a main digital signal output by the main analog-digital conversion unit 102 and an auxiliary digital signal output by the auxiliary analog-digital conversion unit 105, the main digital signal and the auxiliary digital signal are input to the calibration module 103, the calibration module 103 takes the auxiliary digital signal as a reference digital signal, and nonlinear calibration is performed on the main digital signal based on the reference digital signal, and after the calibration is completed, a linear digital signal is output through a first output end of the calibration module 103, and the calibration process of an analog-digital conversion output result is completed.
The specific process of non-linear calibration of the calibration module is illustrated in the following figures. Fig. 3 is a flowchart of a calibration method executed by a calibration module in an analog-to-digital conversion circuit according to an embodiment of the present application. As shown in fig. 3, the method includes:
s301, receiving a main digital signal output by the main analog-to-digital conversion unit and an auxiliary digital signal output by the auxiliary analog-to-digital conversion unit.
S302, the main digital signal and the auxiliary digital signal are subjected to difference to obtain an output difference value of the main channel and the auxiliary channel.
Converting the main digital signal and the auxiliary digital signal into corresponding decimal values to obtain a main digital signal value and an auxiliary digital signal value, and decimal-dividing the auxiliary digital signalThe value is decimal to the main digital signal to produce a difference, resulting in an output difference. That is to say,wherein->To output the difference +.>For the main digital signal value,/->Is the secondary digital signal value.
S303, calibrating the main digital signal by outputting the difference value.
The main digital signal includes: the plurality of primary digital signal values in turn, the secondary digital signal comprising: a plurality of secondary digital signal values in sequence. And the main digital signal value converted from the same analog signal is differenced with the auxiliary digital signal value, so that a corresponding output difference value is obtained.
Thus, based on the plurality of main digital signal values and the plurality of auxiliary digital signal values, a plurality of output difference values can be obtained, and based on the plurality of main digital signal values and the corresponding output difference values, polynomial fitting is performed to obtain a plurality of expressions of the output difference values and the main digital signal values. The multiple expression may be. Performing coefficient estimation on the multiple expressions by adopting a least average method, and determining each coefficient in the multiple expressions, wherein ∈9>、/>、/>、……、/>Required for the multiple expressionCoefficients are constants, and n is an integer greater than or equal to 2.
After the calibration module obtains multiple expressions of the output difference value and the main digital signal value, substituting the expression into the re-obtained main digital signal to calculate to obtain an output difference value corresponding to the main digital signal, taking the re-calculated output difference value as a nonlinear error of the main digital signal, carrying out nonlinear calibration on the main digital signal by adopting the calculated nonlinear error, and carrying out calibration in sequence to finally finish the calibration of the analog-to-digital conversion process to obtain the linearization digital signal.
After the calibration method for carrying out nonlinear calibration on the main digital signal is obtained through fitting, the calibration module only needs to calibrate the converted main digital signal by adopting the calibration method, and excessive complex calibration operation and larger modification on an analog-to-digital conversion circuit are not needed. Meanwhile, only when the auxiliary digital signal is acquired and the output difference value is calculated, the auxiliary channel is adopted for analog-to-digital conversion, after the calibration module calculates the calibration method, only the main digital signal output by the main channel is required to be calibrated, the auxiliary channel is not required to be subjected to analog-to-digital conversion, at the moment, the auxiliary channel can be stopped from being powered, the circuit power consumption is reduced, or the auxiliary channel is maintained to work, so that nonlinear offset caused by the change of the working environment (such as temperature, power supply voltage and the like) is tracked.
In summary, in the calibration method executed by the calibration module in the analog-to-digital conversion circuit provided by the embodiment of the application, in the analog-to-digital conversion process, the auxiliary digital signal obtained by the conversion of the auxiliary channel calibrates the main digital signal obtained by the conversion of the main channel to obtain a nonlinear calibration method, and then the nonlinear calibration method is utilized to perform nonlinear calibration on the main digital signal after the reconverted to obtain the output linearized digital signal. On the premise of not greatly changing the circuit structure, the nonlinear calibration method obtained by calculation is utilized to complete nonlinear calibration on the digital signals after analog-to-digital conversion, so that the nonlinear calibration efficiency of the analog-to-digital conversion is improved, and meanwhile, the power consumption of the analog-to-digital conversion circuit is reduced.
On the basis of the analog-to-digital conversion circuit described in fig. 1, another analog-to-digital conversion circuit is further provided in the embodiment of the present application. Fig. 4 is a schematic structural diagram of another analog-to-digital conversion circuit according to an embodiment of the present application. As shown in fig. 4, the analog-to-digital conversion circuit may further include:
the main channel also comprises: a first sample-and-hold circuit 401; an input end of the first sample-and-hold circuit 401 is connected to an output end of the main input buffer, and an output end of the first sample-and-hold circuit 401 is connected to an input end of the main analog-to-digital conversion unit.
Optionally, the auxiliary channel further includes: and the input end of the second sample-and-hold circuit 402 is connected with the output end of the auxiliary input buffer, and the output end of the second sample-and-hold circuit 402 is connected with the input end of the auxiliary analog-to-digital conversion unit.
Because a certain conversion time is needed when analog signals are subjected to analog-to-digital conversion, the conversion accuracy can be ensured only by keeping the analog signals basically unchanged in the conversion time. Therefore, by adding the sample hold circuit before the main analog-digital conversion unit and the auxiliary analog-digital conversion unit in the analog-digital conversion circuit, analog signals on the main channel and the auxiliary channel can be basically kept unchanged, the conversion precision is ensured, and the calibration accuracy of the subsequent calibration module is further improved.
On the basis of the analog-to-digital conversion circuit described in fig. 4, another analog-to-digital conversion circuit is further provided in the embodiment of the application. Fig. 5 is a schematic structural diagram of another analog-to-digital conversion circuit according to an embodiment of the present application. As shown in fig. 5, the analog-to-digital conversion circuit may further include:
the first sample-and-hold circuit 401 on the main channel includes: a first switching switch 4011 and a first holding capacitance 4012; in the first sample-and-hold circuit 401, one end of the first switch 4011 is an input end of the first sample-and-hold circuit 401, the other end of the first switch 4011 is grounded through the first holding capacitor 4012, and a connection point between the first switch 4011 and the first holding capacitor 4012 is an output end of the first sample-and-hold circuit 401.
The second sample-and-hold circuit 402 on the secondary channel includes: a second changeover switch 4021 and a second holding capacitance 4022; in the second sample-and-hold circuit 402, one end of the second switch 4021 is an input end of the second sample-and-hold circuit 402, the other end of the second switch 4021 is grounded through the second holding capacitor 4022, and a connection point between the second switch 4021 and the second holding capacitor 4022 is an output end of the second sample-and-hold circuit 402.
The main channel and the auxiliary channel are provided with a simplified sample hold circuit which consists of an input end, an output end, a change-over switch, a hold capacitor and the like. On the basis of meeting the basic attribute of the sample hold circuit, the number of used devices is reduced, the circuit structure is further simplified, the complexity of circuit design is reduced, the product cost is further reduced, and meanwhile, the power consumption of the circuit is reduced.
Alternatively, in any of the above embodiments, the main analog-to-digital conversion unit 102 and the auxiliary analog-to-digital conversion unit 105 are the same type of analog-to-digital conversion unit, and the analog-to-digital conversion units are, for example: pipelined analog-to-digital conversion units, successive approximation analog-to-digital conversion units, integral analog-to-digital conversion units, and the like. By using the same type of analog-to-digital conversion unit, the distortion generated in the analog-to-digital conversion process of the main channel and the auxiliary channel is the same, and the nonlinear error of the main digital signal can be calibrated by comparing the output digital signals of the two channels.
In other examples, the primary analog-to-digital conversion unit 102 and the secondary analog-to-digital conversion unit 105 are different types of mode conversion units. Illustratively, the primary analog-to-digital conversion unit 102 is a pipelined analog-to-digital conversion unit, and the secondary analog-to-digital conversion unit 105 is a successive approximation type analog-to-digital conversion unit by which the pipelined analog-to-digital conversion unit is simulated. For example, the successive approximation analog-to-digital converter may be an N-segment split analog-to-digital conversion array, where N is the same as the number of stages N of the pipelined analog-to-digital conversion unit in the main channel, so that the number of bits corresponding to each segment is consistent with the number of bits of the corresponding stage of the pipelined analog-to-digital conversion unit. At this time, the successive approximation type analog-to-digital conversion unit on the auxiliary channel can simulate the pipelined analog-to-digital conversion unit on the main channel, so that the distortion generated in the analog-to-digital conversion process of the main channel and the auxiliary channel is the same, the gain errors of the two channels are generated at the same switching point, and the nonlinear error of the main digital signal is calibrated by comparing the output digital signals of the two channels, and the interstage gain error of the digital signal is calibrated.
On the basis of the analog-to-digital conversion circuit described in any one of fig. 1-2 and fig. 4-5, an embodiment of the present application further provides an analog-to-digital conversion circuit. The main analog-to-digital conversion unit 102 is a pipelined analog-to-digital conversion unit, and the auxiliary analog-to-digital conversion unit 105 is a successive approximation analog-to-digital conversion unit. Fig. 6 is a schematic structural diagram of an analog-to-digital conversion circuit according to an embodiment of the present application. As shown in fig. 6, the analog-to-digital conversion circuit may further include:
the main analog-to-digital conversion unit 102 comprises an N-stage analog-to-digital converter, N-1 allowance amplifiers and N-1 regulation control switches; wherein N is an integer greater than or equal to 2; comprising the following steps: the first stage analog-to-digital converter 1021, the second stage analog-to-digital converters 1024, … …, the first residual amplifier 1023, the second residual amplifiers 1026, … …, the first regulation control switch 1022, and the second regulation control switches 1025, … ….
The residual output end of the former-stage analog-to-digital converter between two adjacent stages of analog-to-digital converters is connected with the input end of a residual amplifier, and the output end of the residual amplifier is connected with the input end of the latter-stage analog-to-digital converter in the two adjacent stages of analog-to-digital converters; the input end of the first-stage analog-to-digital converter is connected with the output end of the main input buffer, and the output end of the last-stage analog-to-digital converter is connected with the input end of the calibration module; each adjusting control switch is connected to a bias circuit of a residual amplifier; the second output end of the calibration module is connected with the control end of the adjusting control switch.
For example, when the main digital signal and the auxiliary digital signal are input to the calibration module 103, the calibration module 103 compares the main digital signal with the auxiliary digital signal, and when the calibration module 103 obtains that the main digital signal has a gain error by comparing the main digital signal with the auxiliary digital signal as a reference, the calibration module 103 sends a calibration gain error command according to the gain error amount, and the calibration gain error command is transmitted to the adjustment control switch through the second output end of the calibration module 103, so that the adjustment control switch can adjust N-1 adjustment control switches according to the calibration gain error command, thereby controlling and adjusting the N-1 margin amplifiers, and realizing the calibration of the gain error. Because the calibration of the gain error is carried out by the calibration module on the main digital signal in real time, the calibration time of the gain error can be greatly reduced, and the calibration efficiency of the gain error is improved.
In summary, in the analog-to-digital conversion circuit provided by the embodiment of the application, the calibration module 103 performs gain error calibration on the main digital signal according to the auxiliary digital signal, and controls the plurality of residual amplifiers by controlling the plurality of adjusting control switches, so as to control the main analog-to-digital conversion unit to calibrate the gain error, thereby realizing the calibration of the gain error in the analog-to-digital conversion process and improving the calibration efficiency of the gain error.
Fig. 7A and 7B are transmission characteristic curves before and after calibration of the digital signal based on the analog-to-digital conversion circuit of any one of fig. 1 to 2 and fig. 4 to 6, fig. 7A is a transmission characteristic curve before calibration, and fig. 7B is a transmission characteristic curve after calibration. And calibrating the digital signal by a calibration module, so that the nonlinear error and the gain error caused by distortion in the analog-to-digital conversion process are calibrated, and the transmission characteristic curve of the finally obtained output difference value is a straight line, so that the output main digital signal is a linear digital signal.
In another aspect of the present application, an electronic device is provided, where the electronic device may include the analog-to-digital conversion circuit of any one of fig. 1-2 and fig. 4-6.
Because the electronic equipment comprises the analog-to-digital conversion circuit, the analog-to-digital conversion circuit has the beneficial effects that the analog-to-digital conversion circuit can bring, and the electronic equipment comprises the analog-to-digital conversion circuit and is not repeated here.
The foregoing is merely a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and variations may be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
The foregoing is merely a specific embodiment of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. An analog-to-digital conversion circuit, comprising: a main channel, an auxiliary channel and a calibration module; wherein, the main channel includes: a main input buffer and a main analog-to-digital conversion unit, the auxiliary channel including; an auxiliary input buffer and an auxiliary analog-to-digital conversion unit;
the input ends of the main input buffer and the auxiliary input buffer are used for receiving input analog signals; the output end of the main input buffer is connected with the main analog-to-digital conversion unit, and the output end of the auxiliary input buffer is connected with the auxiliary analog-to-digital conversion unit;
the output ends of the main analog-to-digital conversion unit and the auxiliary analog-to-digital conversion unit are both connected with the input end of the calibration module, so that the calibration module carries out nonlinear calibration on the main digital signal output by the main analog-to-digital conversion unit by adopting the auxiliary digital signal obtained by the auxiliary analog-to-digital conversion unit, and then outputs a linear digital signal through the first output end of the calibration module;
if the main analog-to-digital conversion unit is a pipelined analog-to-digital conversion unit, the auxiliary analog-to-digital conversion unit is a successive approximation analog-to-digital conversion unit, and the main analog-to-digital conversion unit comprises an N-level analog-to-digital converter, N-1 allowance amplifiers and N-1 adjusting control switches; n is an integer greater than or equal to 2;
the residual output end of the former-stage analog-to-digital converter between two adjacent stages of analog-to-digital converters is connected with the input end of a residual amplifier, and the output end of the residual amplifier is connected with the input end of the latter-stage analog-to-digital converter in the two adjacent stages of analog-to-digital converters; the input end of the first-stage analog-to-digital converter is connected with the output end of the main input buffer, and the output end of the last-stage analog-to-digital converter is connected with the input end of the calibration module; each adjusting control switch is connected to a bias circuit of a residual amplifier;
and a second output end of the calibration module is connected with a control end of the adjusting control switch.
2. The analog-to-digital conversion circuit of claim 1, wherein the primary input buffer and the secondary input buffer are input buffers having the same architecture and the same operating voltage.
3. The analog-to-digital conversion circuit of claim 1, wherein a sampling frequency of the auxiliary analog-to-digital conversion unit is less than or equal to a sampling frequency of the main analog-to-digital conversion unit.
4. The analog-to-digital conversion circuit of claim 1, wherein said main channel further comprises: and the input end of the first sample-and-hold circuit is connected with the output end of the main input buffer, and the output end of the first sample-and-hold circuit is connected with the input end of the main analog-to-digital conversion unit.
5. The analog-to-digital conversion circuit of claim 4, wherein said first sample-and-hold circuit comprises: a first change-over switch and a first holding capacitor;
one end of the first change-over switch is an input end of the first sample hold circuit, the other end of the first change-over switch is grounded through the first holding capacitor, and a connection point between the first change-over switch and the first holding capacitor is an output end of the first sample hold circuit.
6. The analog-to-digital conversion circuit of claim 1, wherein the auxiliary channel further comprises: and the input end of the second sample-hold circuit is connected with the output end of the auxiliary input buffer, and the output end of the second sample-hold circuit is connected with the input end of the auxiliary analog-to-digital conversion unit.
7. The analog-to-digital conversion circuit of claim 6, wherein said second sample-and-hold circuit comprises: a second change-over switch and a second holding capacitance;
one end of the second change-over switch is an input end of the second sample hold circuit, the other end of the second change-over switch is grounded through the second holding capacitor, and a connection point between the second change-over switch and the second holding capacitor is an output end of the second sample hold circuit.
8. The analog-to-digital conversion circuit of claim 1, wherein the primary analog-to-digital conversion unit and the secondary analog-to-digital conversion unit are the same type of analog-to-digital conversion unit or different types of analog-to-digital conversion units.
9. The analog-to-digital conversion circuit of claim 1, wherein said successive approximation analog-to-digital conversion unit is an N-segment split analog-to-digital conversion array, N being the same as the number of stages N of said pipelined analog-to-digital conversion unit in said main channel.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3043478A1 (en) * | 2014-12-17 | 2016-07-13 | Analog Devices, Inc. | Microprocessor-assisted calibration for analog-to-digital converter |
| CN112003620A (en) * | 2020-10-29 | 2020-11-27 | 南京航空航天大学 | Pipeline successive approximation type ADC (analog to digital converter) bit weight background calibration system and method |
| CN113271102A (en) * | 2021-04-30 | 2021-08-17 | 澳门大学 | Pipeline analog-to-digital converter |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4977570B2 (en) * | 2007-10-03 | 2012-07-18 | 株式会社日立製作所 | DIGITAL CALIBRATION TYPE ANALOG / DIGITAL CONVERTER AND RADIO RECEIVING CIRCUIT AND RADIO TRANSMITTING / RECEIVER CIRCUIT USING THE SAME |
| JP5189828B2 (en) * | 2007-11-20 | 2013-04-24 | 株式会社日立製作所 | Analog-digital converter chip and RF-IC chip using the same |
| US11239854B2 (en) * | 2019-10-03 | 2022-02-01 | Texas Instruments Incorporated | Non-linearity correction |
-
2021
- 2021-09-24 CN CN202111120927.5A patent/CN113839674B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3043478A1 (en) * | 2014-12-17 | 2016-07-13 | Analog Devices, Inc. | Microprocessor-assisted calibration for analog-to-digital converter |
| CN112003620A (en) * | 2020-10-29 | 2020-11-27 | 南京航空航天大学 | Pipeline successive approximation type ADC (analog to digital converter) bit weight background calibration system and method |
| CN113271102A (en) * | 2021-04-30 | 2021-08-17 | 澳门大学 | Pipeline analog-to-digital converter |
Non-Patent Citations (2)
| Title |
|---|
| Lavita Mendonca 等.Implementation of SAR ADC for Biomedical Applications—A Review.《Advances in Communication, Signal Processing, VLSI, and Embedded Systems》.2019,1. * |
| 成继勋 等.采用ADuC824的数字调节器.《自动化仪表 》.2003,(第10期),4. * |
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