CN114326900A - High-precision adjustable reference voltage generation circuit - Google Patents
High-precision adjustable reference voltage generation circuit Download PDFInfo
- Publication number
- CN114326900A CN114326900A CN202111634363.7A CN202111634363A CN114326900A CN 114326900 A CN114326900 A CN 114326900A CN 202111634363 A CN202111634363 A CN 202111634363A CN 114326900 A CN114326900 A CN 114326900A
- Authority
- CN
- China
- Prior art keywords
- output
- voltage
- analog converter
- digital
- calibration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003139 buffering effect Effects 0.000 claims abstract description 4
- 230000003068 static effect Effects 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 10
- 239000003990 capacitor Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- UDQDXYKYBHKBTI-IZDIIYJESA-N 2-[4-[4-[bis(2-chloroethyl)amino]phenyl]butanoyloxy]ethyl (2e,4e,6e,8e,10e,12e)-docosa-2,4,6,8,10,12-hexaenoate Chemical compound CCCCCCCCC\C=C\C=C\C=C\C=C\C=C\C=C\C(=O)OCCOC(=O)CCCC1=CC=C(N(CCCl)CCCl)C=C1 UDQDXYKYBHKBTI-IZDIIYJESA-N 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a high-precision adjustable reference voltage generating circuit, and belongs to the field of CMOS analog integrated circuits. The method is used for solving the technical problem that a reference voltage circuit suitable for a high-precision application scene is lacked in the prior art. The high-precision adjustable reference voltage generating circuit comprises: the device comprises a reference circuit module, a main DAC, an output buffer amplifier and a voltage calibration circuit module; the reference circuit module is used for generating and outputting a reference voltage; the main DAC is used for generating voltage values of all proportions based on a reference voltage; the output buffer amplifier is used for amplifying and buffering the voltage value generated by the main DAC for output; the voltage calibration circuit module is used for generating a control signal based on the reference voltage and the output voltage of the output buffer amplifier so as to control and adjust the output voltage of the main DAC and realize the calibration of the output reference voltage. By adopting the scheme of the invention, the generation of high-precision adjustable reference voltage can be realized.
Description
Technical Field
The invention belongs to the field of CMOS analog integrated circuit design, and particularly relates to a high-precision adjustable reference voltage generating circuit.
Background
In the field of CMOS Analog integrated circuits, stable and accurate voltage references are required for reference in many cases, especially in Analog to Digital Converter (ADC) designs, the accuracy of reference voltages of some ADCs can seriously affect the conversion accuracy of the ADC if the accuracy of the reference voltages of the ADCs is not satisfactory, for example, some multi-step ADCs require voltage references with different ratios as conversion references, and once the error between different references exceeds the minimum resolution voltage designed by the ADC, the actual accuracy of the ADC will be significantly reduced.
Fig. 1 shows a conventional adjustable reference voltage circuit, which mainly includes a reference module 11, a Digital-to-Analog Converter (DAC) 12 and an output buffer 13, wherein after passing through an N-bit DAC, a reference signal is controlled to be output as any X2 according to a binary input value of the DACNMultiple reference value, wherein X is in the range of 0-2NAn integer in between. However, considering the integral non-linearity error of the DAC, the gain error of the output buffer, and the input offset voltage of the output buffer, when the required precision N is large, the actual output result deviates significantly from the expected output, even by far exceeding 1LSB minimum voltage, which is not acceptable for the application scenario requiring high precision.
Therefore, how to obtain a reference voltage with higher precision is an urgent problem to be solved.
Disclosure of Invention
Aiming at the defects and improvement requirements of the prior art, the invention provides a high-precision adjustable reference voltage generating circuit, which aims to generate high-precision reference voltage and can meet the application occasions such as ADC (analog to digital converter) and the like requiring the high-precision reference voltage.
In order to achieve the above object, the present invention provides a high-precision adjustable voltage reference circuit, including: the device comprises a reference circuit module, a main digital-to-analog converter, an output buffer amplifier and a voltage calibration circuit module;
the reference circuit module is used for generating and outputting a reference voltage;
the input ends of the main digital-to-analog converter and the voltage calibration circuit module are connected with the reference circuit module and used for acquiring the reference voltage;
the input end of the output buffer amplifier is connected with the output end of the main digital-to-analog converter and is used for amplifying and buffering the output voltage of the main digital-to-analog converter;
the other input end of the voltage calibration circuit module is connected with the output end of the output buffer amplifier and is used for acquiring the output voltage of the output buffer amplifier;
the output end of the voltage calibration circuit module is connected with the other input end of the main digital-to-analog converter; the voltage calibration circuit module generates a first control signal based on the reference voltage and the output voltage of the output buffer amplifier, and outputs the first control signal to the main digital-to-analog converter so as to control the main digital-to-analog converter to adjust the output voltage, thereby realizing calibration of the output reference voltage.
Optionally, the voltage calibration circuit module includes: calibrating the digital-to-analog converter, the comparator and the comparison control logic module;
the input end of the calibration digital-to-analog converter is connected with the reference circuit module and used for acquiring the reference voltage;
the negative input end of the comparator is connected with the output end of the calibration digital-to-analog converter, the positive input end of the comparator is connected with the output end of the output buffer amplifier, and the comparator is used for comparing the output voltage of the calibration digital-to-analog converter with the output voltage of the output buffer amplifier to obtain a comparison result;
the input end of the comparison control logic module is connected with the output end of the comparator, the first output end of the comparison control logic module is connected with the main digital-to-analog converter, and the second output end of the comparison control logic module is connected with the calibration digital-to-analog converter; the comparison control logic module generates a first control signal and a second control signal based on the comparison result, and outputs the first control signal and the second control signal to the main digital-to-analog converter and the calibration digital-to-analog converter through the first output end and the second output end respectively, so as to control and adjust the output voltages of the main digital-to-analog converter and the calibration digital-to-analog converter, so as to realize the calibration of the output reference voltage.
Optionally, the reference circuit module is implemented by using a bandgap reference.
Optionally, the main digital-to-analog converter includes: a resistance digital-to-analog converter and a binary current digital-to-analog converter are connected in series; the main digital-to-analog converter realizes high-order output through a series resistance digital-to-analog converter, and realizes low-order output through a binary current digital-to-analog converter.
Optionally, the output buffer amplifier adopts a folded cascode amplifier structure.
Optionally, the calibration digital-to-analog converter is specifically a capacitance digital-to-analog converter.
Optionally, the comparator is a static pre-amplification comparator with output offset storage.
Generally, by the above technical solution of the present invention, at least the following beneficial effects can be obtained:
(1) according to the invention, the voltage calibration circuit module containing the calibration digital-to-analog converter with higher precision calibrates the main digital-to-analog converter with lower precision, and finally, a high-precision adjustable reference voltage output can be obtained, and compared with the traditional structure, the voltage calibration circuit module can eliminate the mismatch error of the main digital-to-analog converter, the offset voltage of an output buffer and the gain error, so that the error of the output voltage is within 1LSB of the minimum resolution voltage.
(2) The system has calibration capability, has stronger tolerance to gain errors and offset errors, does not require the output buffer amplifier to have extremely high gain and matching performance, and greatly reduces the high requirement on amplifier design.
(3) The calibration is completed only once when the system is powered on, the output reference voltage can be kept after the calibration is completed, and the calibration part does not work any more, so that the generation of large power consumption of the system is effectively avoided.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional reference voltage generating circuit according to the background art of the present invention;
fig. 2 is a schematic structural diagram of a high-precision adjustable voltage reference circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another high-precision adjustable voltage reference circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an amplifier circuit used in the output buffer amplifier of the embodiment of the present invention;
FIG. 5 is a schematic diagram of a comparator used in an embodiment of the present invention;
FIG. 6 is a timing diagram illustrating calibration according to an embodiment of the present invention;
fig. 7 is a simulation waveform diagram of a calibration process according to an embodiment of the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The technical solution of the present invention is described in detail with specific examples below.
Referring to fig. 2, a schematic diagram of a high-precision adjustable voltage reference circuit according to an embodiment of the present invention includes: a reference circuit module 1, a main digital-to-analog converter (i.e. main DAC)2, an output buffer amplifier 3 and a voltage calibration circuit module 4; a reference circuit module 1 for generating and outputting a reference voltage; the input ends of the main DAC 2 and the voltage calibration circuit module 4 are connected with the reference circuit module 1 and used for obtaining the reference voltage; the input end of the output buffer amplifier 3 is connected with the output end of the main DAC 2 and is used for amplifying and buffering the output voltage of the main DAC 2 for output; the other input end of the voltage calibration circuit module 4 is connected with the output end of the output buffer amplifier 3 and is used for acquiring the output voltage of the output buffer amplifier 3; the output end of the voltage calibration circuit module 4 is connected with the other input end of the main DAC 2; the voltage calibration circuit module 4 generates a first control signal based on the reference voltage and the output voltage of the output buffer amplifier 3, and outputs the first control signal to the main DAC 2 to control the main DAC 2 to adjust the output voltage, so as to calibrate the output reference voltage.
In the specific implementation process, referring to fig. 3, the voltage calibration circuit module 4 includes: a calibration digital-to-analog converter (i.e., calibration DAC)41, a comparator 42, and a comparison control logic block 43. With reference to fig. 2 and 3, the input terminal of the calibration DAC 41 is connected to the reference circuit module 1 for obtaining the reference voltage; the negative input end (VIN _2) of the comparator 42 is connected with the output end of the calibration DAC 41, the positive input end (VIP _2) of the comparator 42 is connected with the output end of the output buffer amplifier 3, and the comparator 42 is used for comparing the output voltage of the calibration DAC 41 with the output voltage of the output buffer amplifier 3 to obtain a comparison result; the input end of the comparison control logic module 43 is connected with the output end (COMP) of the comparator 42, the first output end is connected with the main DAC 2, and the second output end is connected with the calibration DAC 41; the comparison control logic module 43 generates a first control signal and a second control signal based on the comparison result, and outputs the first control signal and the second control signal to the main DAC 2 and the calibration DAC 41 through the first output terminal and the second output terminal, respectively, for controlling and adjusting the output voltages of the main DAC 2 and the calibration DAC 41, so as to realize calibration of the output reference voltage.
In a specific implementation process, digital-to-analog conversion of the DAC needs to be implemented based on a reference voltage, and the reference circuit module 1 mainly functions to provide a reference voltage.
The main DAC 2 of the present embodiment is implemented by a series resistor DAC and a binary current DAC, and the high order bits use the series resistor DAC and the low order bits use the binary current DAC. The DAC can control the analog output value of the DAC to be any X/2 through controlling the binary input codeNMultiple reference value, wherein X is in the range of 0-2NThe integer between them, of course, the output result still has some error from the ideal result due to the mismatch of resistance and current.
Referring to fig. 3 and 4, the output buffer amplifier 3 port includes a positive input port (VIP _1) connected to the output port of the main DAC 2, and the output port (VOP) serves as the output of the system (i.e., the output of the high-precision adjustable voltage reference generating circuit according to the embodiment of the present application), and is connected to a positive input port (VIP _2) of the comparator 42. The amplifier used in this embodiment is a folded cascode amplifier. The specific structure of the output buffer amplifier 3 can be selected according to the load and the input/output range, as shown in fig. 4, the structure is realized by 7 PMOS devices M1-M7 and 4 NMOS devices M8-M11, in the structure, the source end of the M1 tube is connected with the power supply, the gate end is connected with the bias voltage Vb1, and the drain end is connected with the source ends of M2 and M3; the M2 gate terminal is connected with the positive input terminal (VIP _1), the source terminal is connected with the M1 drain terminal, and the drain terminal is connected with the M8 source terminal and the M10 drain terminal; the grid end of M3 is connected with the negative input end (VIN _1), the source end is connected with the drain end of M1, and the drain end is connected with the source end of M9 and the drain end of M11; the gate of M4 is connected with the drain of M6 and the drain of M8, the source is connected with the power supply, and the drain is connected with the source of M6; the gate end of M5 is connected with the gate end of M4, the source end is connected with the power supply, and the drain end is connected with the source end of M7; the gate terminal of M6 is connected with bias voltage Vb2 and M7, the source terminal is connected with the drain terminal of M4, and the drain terminal is connected with the drain terminal of M8. The grid end of M7 is connected with the grid end of M6, the source end is connected with the drain end of M5, and the drain end is connected with the drain end of M9 and is used as the output end VOP of the amplifier; the grid end of the M8 is connected with a bias voltage Vb3, the source end of the M8 is connected with the drain end of the M10, and the drain end of the M8 is connected with the drain end of the M6; the grid end of M9 is connected with Vb3, the source end is connected with the drain end of M11, and the drain end is connected with VOP; the grid end of M10 is connected with bias voltage Vb4, the source end is connected with the ground, and the drain end is connected with the source end of M8; m11 has its gate terminal connected to bias voltage Vb4, its source terminal connected to ground, and its drain terminal connected to M9.
The calibration DAC 41 used in this embodiment is a capacitor DAC, and the capacitor usually has a good absolute accuracy, but has the disadvantage of continuous leakage, which cannot be maintained for a long time. Since the calibration DAC 41 only needs to be used during calibration, it is feasible to use the high accuracy of the capacitive DAC for calibration of the low accuracy DAC.
Referring to fig. 3 and 5, in the comparator 42 used in the present embodiment, a positive input terminal (VIP _2) of the comparator 42 is connected to the output terminal (VOP) of the output buffer amplifier 3, a negative input terminal (VIN _2) is connected to the output terminal of the calibration DAC 41, and an output terminal (COMP) is connected to the input terminal of the comparison control logic module 43. This embodiment uses a static pre-amplified comparator with output offset storage. In order to avoid the offset error brought by the offset of the comparator to the comparison, the offset of the comparator is eliminated through an output offset storage method.
Still referring to fig. 5, the comparator 42 used in this embodiment includes three stages of pre-amplifiers (a1, a2, A3) and a latch (421), three pairs of offset storage capacitors (C1, C2, C3) and five pairs of switches (S1 to S5). A first pair of switches S1 has a first terminal coupled to the differential inputs VIP _2 and VIN _2 of the comparator 42 and a second terminal coupled to the differential input of the first stage preamplifier a 1; a first end of the second pair of switches S2 is connected to the common-mode reset voltage VCM, and a second end is connected to the differential input end of the first stage preamplifier A1; a first end of the third pair of switches S3 is connected to the common-mode reset voltage VCM, and a second end is connected to the differential input end of the second stage preamplifier a 2; a first end of the fourth pair of switches S4 is connected to the common-mode reset voltage VCM, and a second end is connected to the differential input end of the third stage preamplifier A3; a first terminal of the fifth pair of switches S5 is connected to the common-mode reset voltage VCM, and a second terminal is connected to the input terminal of the latch 421; the output end of the first-stage preamplifier A1 is connected with the first end of a first pair of capacitors C1; the input end of the second-stage preamplifier A2 is connected with the second end of the first pair of capacitors C1, and the output end of the second-stage preamplifier A2 is connected with the first end of the second pair of capacitors C2; the input end of the third-stage preamplifier A3 is connected with the second end of the second pair of capacitors C2, and the output end of the third-stage preamplifier A3 is connected with the first end of the third pair of capacitors C3; the input terminal of latch 421 is connected to the second terminal of the third pair of capacitors C3, and the output is comparator 42 output COMP.
Still referring to fig. 3, the input of the comparison control logic module 43 is connected to the output of the comparator 42, the first output thereof is connected to the control input of the main DAC 2, and the second output thereof is connected to the input of the calibration DAC 41. The comparison control logic module 43 controls the main DAC 2 and the calibration DAC 41 to obtain the required voltage, and then gradually adjusts the output voltage of the main DAC 2 according to the comparison result of the comparator 42, thereby implementing the calibration of the output reference voltage.
Referring to fig. 6, in order to provide a calibration timing diagram according to an embodiment of the present invention, after a system is initialized, a calibration mode is first entered, first, the main DAC 2 and the calibration DAC 41 are assigned according to a required output voltage, and then, an initial voltage value is obtained after the assignment, the voltage value obtained in the calibration DAC 41 refers to the voltage CDAC in the graph, and the output value of the system refers to VOUT in the graph, DONE indicates whether a calibration process is completed. After the assignment is completed, the comparator 42 starts to compare the magnitude of the two, the value of the CDAC is kept unchanged, the output of the main DAC 2 is continuously changed according to the comparison result, so that the step of VOUT is close to the value of the CDAC, and VOUT does not change any more after the result of the comparator 42 turns over, thereby realizing calibration. At the end of calibration, the flag signal DONE is set high, indicating that calibration is complete, while the main DAC 2 may no longer be changed. The calibration DAC 41 and the comparator 42 can stop working, and power consumption is saved.
Referring to fig. 7, a simulation waveform diagram of a calibration process according to an embodiment of the present invention shows a specific calibration process in the simulation process, where a reference voltage is 1V, a required voltage is 31/32 × 1V — 968.75mV, and a required precision is 12 bits, that is, a precision of voltage is 1/2120.244 mV. The voltage output by the system shown in the figure continuously approaches the output value of the calibration digital-to-analog converter, and after the calibration is completed, the output value VOUT of the system is 968.605mV, the error is 0.145mV, and the output value VOUT is within 1LSB, so that the calibration requirement of 12 bits is met.
In general, the invention calibrates the main digital-to-analog converter with lower precision through the calibration digital-to-analog converter with higher precision, and finally obtains a high-precision adjustable reference voltage output, compared with the traditional structure, the invention can eliminate the mismatch error of the main digital-to-analog converter, the offset voltage of the output buffer and the gain error, and ensure that the error of the output voltage is within 1LSB of the minimum resolution voltage. Meanwhile, the method has stronger tolerance to gain errors and offset errors, does not require the output buffer amplifier to have extremely high gain and matching performance, and greatly reduces the high requirement on amplifier design. And the calibration is completed only once when the system is powered on, the output reference voltage can be kept after the calibration is completed, and the calibration part does not work any more, thereby effectively avoiding the generation of larger power consumption of the system.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (7)
1. A high precision adjustable voltage reference circuit, comprising: the device comprises a reference circuit module, a main digital-to-analog converter, an output buffer amplifier and a voltage calibration circuit module;
the reference circuit module is used for generating and outputting a reference voltage;
the input ends of the main digital-to-analog converter and the voltage calibration circuit module are connected with the reference circuit module and used for acquiring the reference voltage;
the input end of the output buffer amplifier is connected with the output end of the main digital-to-analog converter and is used for amplifying and buffering the output voltage of the main digital-to-analog converter;
the other input end of the voltage calibration circuit module is connected with the output end of the output buffer amplifier and is used for acquiring the output voltage of the output buffer amplifier;
the output end of the voltage calibration circuit module is connected with the other input end of the main digital-to-analog converter; the voltage calibration circuit module generates a first control signal based on the reference voltage and the output voltage of the output buffer amplifier, and outputs the first control signal to the main digital-to-analog converter so as to control the main digital-to-analog converter to adjust the output voltage, thereby realizing calibration of the output reference voltage.
2. The high precision adjustable voltage reference circuit of claim 1, wherein the voltage calibration circuit module comprises: calibrating the digital-to-analog converter, the comparator and the comparison control logic module;
the input end of the calibration digital-to-analog converter is connected with the reference circuit module and used for acquiring the reference voltage;
the negative input end of the comparator is connected with the output end of the calibration digital-to-analog converter, the positive input end of the comparator is connected with the output end of the output buffer amplifier, and the comparator is used for comparing the output voltage of the calibration digital-to-analog converter with the output voltage of the output buffer amplifier to obtain a comparison result;
the input end of the comparison control logic module is connected with the output end of the comparator, the first output end of the comparison control logic module is connected with the main digital-to-analog converter, and the second output end of the comparison control logic module is connected with the calibration digital-to-analog converter; the comparison control logic module generates a first control signal and a second control signal based on the comparison result, and outputs the first control signal and the second control signal to the main digital-to-analog converter and the calibration digital-to-analog converter through the first output end and the second output end respectively, so as to control and adjust the output voltages of the main digital-to-analog converter and the calibration digital-to-analog converter, so as to realize the calibration of the output reference voltage.
3. The high precision adjustable voltage reference circuit according to claim 1, wherein said reference circuit block is implemented using a bandgap reference.
4. The high precision adjustable voltage reference circuit of claim 1, wherein said main digital-to-analog converter comprises: a resistance digital-to-analog converter and a binary current digital-to-analog converter are connected in series; the main digital-to-analog converter realizes high-order output through a series resistance digital-to-analog converter, and realizes low-order output through a binary current digital-to-analog converter.
5. The high precision adjustable voltage reference circuit of claim 1, wherein the output buffer amplifier employs a folded cascode amplifier structure.
6. The high accuracy adjustable voltage reference circuit as claimed in claim 2, wherein said calibration digital to analog converter is embodied as a capacitive digital to analog converter.
7. The high accuracy adjustable voltage reference circuit of claim 2 wherein said comparator is a static pre-amplified comparator with output offset storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111634363.7A CN114326900A (en) | 2021-12-29 | 2021-12-29 | High-precision adjustable reference voltage generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111634363.7A CN114326900A (en) | 2021-12-29 | 2021-12-29 | High-precision adjustable reference voltage generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114326900A true CN114326900A (en) | 2022-04-12 |
Family
ID=81017384
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111634363.7A Pending CN114326900A (en) | 2021-12-29 | 2021-12-29 | High-precision adjustable reference voltage generation circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114326900A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075188A (en) * | 2010-12-31 | 2011-05-25 | 北京时代民芯科技有限公司 | Digital static calibration circuit of digital-to-analog converter (DAC) |
| CN202231703U (en) * | 2011-09-14 | 2012-05-23 | 深圳市亿维自动化技术有限公司 | Self-calibration circuit of digital to analog conversion output voltage |
| CN102811058A (en) * | 2011-05-31 | 2012-12-05 | 联咏科技股份有限公司 | Signal processing system and self-calibrating digital-to-analog converting method thereof |
| CN103178846A (en) * | 2013-03-29 | 2013-06-26 | 华南理工大学 | LMS (Least Mean Squares) algorithm for calibrating ADC (Analog to Digital Converter) |
| CN110958021A (en) * | 2019-12-26 | 2020-04-03 | 北京时代民芯科技有限公司 | High-speed high-precision current rudder digital-to-analog converter self-calibration system and method |
| CN112953535A (en) * | 2019-12-11 | 2021-06-11 | 上海交通大学 | Gain error calibration device and method for analog-digital converter with segmented structure |
-
2021
- 2021-12-29 CN CN202111634363.7A patent/CN114326900A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075188A (en) * | 2010-12-31 | 2011-05-25 | 北京时代民芯科技有限公司 | Digital static calibration circuit of digital-to-analog converter (DAC) |
| CN102811058A (en) * | 2011-05-31 | 2012-12-05 | 联咏科技股份有限公司 | Signal processing system and self-calibrating digital-to-analog converting method thereof |
| CN202231703U (en) * | 2011-09-14 | 2012-05-23 | 深圳市亿维自动化技术有限公司 | Self-calibration circuit of digital to analog conversion output voltage |
| CN103178846A (en) * | 2013-03-29 | 2013-06-26 | 华南理工大学 | LMS (Least Mean Squares) algorithm for calibrating ADC (Analog to Digital Converter) |
| CN112953535A (en) * | 2019-12-11 | 2021-06-11 | 上海交通大学 | Gain error calibration device and method for analog-digital converter with segmented structure |
| CN110958021A (en) * | 2019-12-26 | 2020-04-03 | 北京时代民芯科技有限公司 | High-speed high-precision current rudder digital-to-analog converter self-calibration system and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7405691B2 (en) | Analog-to-digital conversion circuit | |
| US8791845B2 (en) | Circuitry and method for reducing area and power of a pipelince ADC | |
| CN110401447B (en) | MDAC type time domain ADC structure without operational amplifier | |
| US8947287B2 (en) | Pipeline A/D converter and A/D converting method | |
| Murden et al. | 12b 50MSample/s two-stage A/D converter | |
| CN112448721B (en) | Low-power consumption comparator with low delay distortion characteristic of self-bias circuit | |
| CN111355492B (en) | Comparator and analog-digital conversion circuit | |
| CN114326900A (en) | High-precision adjustable reference voltage generation circuit | |
| KR101122734B1 (en) | Multiplying digital-to-analog converter using series capacitors and pipelined analog-to-digital converter including the same | |
| Woo et al. | 1.2 V 10-bit 75 MS/s pipelined ADC with phase-dependent gain-transition CDS | |
| US7928872B2 (en) | Analog-to-digital converter | |
| Yang et al. | A CMOS 12-bit 4 MHz pipelined A/D converter with commutative feedback capacitor | |
| CN102025374A (en) | Automatic calibration circuit for correcting differential nonlinear error of digital-to-analog converter in real time | |
| Ramamurthy et al. | A deterministic digital calibration technique for pipelined ADCs using a non-nested algorithm | |
| Hashemi et al. | A low power 1-V 10-bit 40-MS/s pipeline ADC | |
| Zahrai et al. | A 12b 100ms/s highly power efficient pipelined adc for communication applications | |
| CN112799460B (en) | Comparison circuit with mismatch calibration function | |
| CN217363058U (en) | Analog-digital converter circuit, analog-digital converter, and electronic apparatus | |
| CN113839674B (en) | Analog-to-digital conversion circuit | |
| CN112737584B (en) | On-chip full-integrated capacitance mismatch calibration circuit | |
| JP3851305B2 (en) | Analog-digital conversion circuit | |
| CN219181502U (en) | Pipelined analog-to-digital converter | |
| Hati et al. | A 55-mW 300MS/s 8-bit CMOS parallel pipeline ADC | |
| Yun | 20-stage pipelined ADC with radix-based calibration | |
| Charkhkar et al. | A 1.8 V, 10-bit, 40MS/s MOSFET-only pipeline analog-to-digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220412 |
|
| RJ01 | Rejection of invention patent application after publication |