CN102811058A - Signal processing system and self-calibrating digital-to-analog converting method thereof - Google Patents
Signal processing system and self-calibrating digital-to-analog converting method thereof Download PDFInfo
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Abstract
The invention discloses a signal processing system which comprises a digital-to-analog converter, a comparing unit and a control unit. The digital-to-analog converter receives digital input and generates an output voltage. The comparing unit receives output voltage and compares a first output voltage with a reference voltage so as to generate an output value. The control unit receives an output value and generates a digital input in numerical value mapping mode by using a firmware or software, so as to revise the digital-to-analog converter. Besides, a self-calibrating digital-to-analog converting method is also provided.
Description
Technical field
The invention relates to a kind of signal processing system and digital-to-analogue conversion method thereof, and particularly relevant for a kind of tool self-calibrating machine-processed signal processing system and digital-to-analogue conversion method thereof.
Background technology
(digital-to-analog converter DAC) is widely used in now the digital circuit, such as the digital analog converter that is output in video, TV (video DAC, TVDAC) digital analog converter.Known digital analog converter can have an outer meeting resistance usually, and the purpose of its setting is the reference resistance of reference current when exporting as digital analog converter inside.Yet, the design of an outer meeting resistance is set outside digital analog converter, though can be used for reducing the influence of process variation, this design still has probability to cause the loss of yield because of process variation.
Summary of the invention
The present invention provides a kind of signal processing system, can make its digital analog converter possess self-calibrating mechanism, to avoid the influence of process variation, increases its yield.
The present invention provides a kind of self-calibrating digital-to-analogue conversion method, is used for building in one the digital analog converter of reference resistance, can make this digital analog converter possess self-calibrating mechanism, to avoid the influence of process variation, increases its yield.
The present invention provides a kind of signal processing system, and it comprises a digital analog converter, a comparing unit and a control unit.Digital analog converter receives a numeral input and produces one first output voltage.Comparing unit receives first output voltage and compares first output voltage and one first reference voltage, to produce an output valve.Control unit receives output valve, and utilizes firmware or software to produce the numeral input with the numerical value mapping mode in view of the above, with the correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference resistance.Control unit is selected increase according to output valve or is reduced the resistance of reference resistance, with the correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference current source and a current source array.Control unit select to increase or reduces the mirror ratio of reference current source and current source array according to output valve, with the correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter receives one second reference voltage.Control unit is selected to increase or reduce by second reference voltage according to output valve, with the correcting digital analog converter.
In an embodiment of the present invention, above-mentioned signal processing system also comprises a test compensating unit.The test compensating unit is imported a test signal to digital analog converter, so that digital analog converter produces one second output voltage.The test compensating unit judges whether second output voltage matees with test signal.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a compensating current element, is used to provide an offset current.The test compensating unit selects to increase or reduce the size of offset current according to its judged result.
In an embodiment of the present invention, above-mentioned control unit comprises a look-up table.When producing the numeral input with the numerical value mapping mode, control unit is found out the pairing numeral input of output valve in look-up table, with the correcting digital analog converter.
The present invention provides a kind of self-calibrating digital-to-analogue conversion method, is used for a digital analog converter.Self-calibrating digital-to-analogue conversion method comprises the steps.Receive a numeral input and produce one first output voltage.Receive first output voltage and compare first output voltage and one first reference voltage, to produce an output valve.Receive output valve, and utilize firmware or software to produce the numeral input in view of the above, with the correcting digital analog converter with the numerical value mapping mode.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference resistance.In the step of correcting digital analog converter, according to the resistance of output valve selection increase or minimizing reference resistance, with the correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference current source and a current source array.In the step of correcting digital analog converter, select to increase or reduce the mirror ratio of reference current source and current source array according to output valve, with the correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter receives one second reference voltage.In the step of correcting digital analog converter, select to increase or reduce by second reference voltage according to output valve, with the correcting digital analog converter.
In an embodiment of the present invention, above-mentioned self-calibrating digital-to-analogue conversion method also comprises the steps.Import a test signal to digital analog converter, so that digital analog converter produces one second output voltage.Judge whether second output voltage matees with test signal.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a compensating current element, is suitable for providing an offset current.Self-calibrating digital-to-analogue conversion method also comprises the size of selecting to increase or reduce offset current according to judged result.
In an embodiment of the present invention, above-mentioned utilize firmware or software comprise the steps with the step that the numerical value mapping mode produces this numeral input.In a look-up table, find out the pairing numeral input of output valve, with the correcting digital analog converter.
Based on above-mentioned, in exemplary embodiment of the present invention, to build reference resistance in the digital analog converter, and use above-mentioned digital-to-analogue conversion method, it possesses self-calibrating mechanism, can avoid the influence of process variation, increases its yield.
For letting the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts embodiment, and cooperates appended graphic elaborating as follows.
Description of drawings
Fig. 1 illustrates the functional block diagram of the signal processing system of one embodiment of the invention.
Fig. 2 illustrates the circuit diagram of the digital analog converter of Fig. 1.
Fig. 3 illustrates the method flow diagram of resistance of the adjustment reference resistance of one embodiment of the invention.
Fig. 4 illustrates the adjustment reference current source of one embodiment of the invention and the method flow diagram of the mirror ratio of current source array.
Fig. 5 illustrates the method flow diagram of adjustment second reference voltage of one embodiment of the invention.
Fig. 6 illustrates the method flow diagram of the adjustment offset current of one embodiment of the invention.
Fig. 7 illustrates the look-up table of one embodiment of the invention.
[main element label declaration]
100: signal processing system 110: digital analog converter
112: current source array 120: comparing unit
130: control unit 140: the test compensating unit
I
REF: reference current source I
CPS: compensating current element
R
OUT: output resistance R
ADJ: reference resistance
V
REF1: the first reference voltage V
REF2: second reference voltage
V
OUT1: first output voltage V
OUT2: second output voltage
OP: operational amplifier S
D: output valve, digital signal
S
IN: the defeated S of numeral
TEST: test signal
S300, S302, S304, S306, S308, S310, S312: the method step of the resistance of adjustment reference resistance
S400, S402, S404, S406, S408, S410, S412: the method step of adjustment reference current source and the mirror ratio of current source array
S500, S502, S504, S506, S 508, S510, S512: the method step of adjusting second reference voltage
S600, S602, S604, S606, S608: the method step of adjustment offset current
Embodiment
If with being built in wherein in the known reference resistance that is external in digital analog converter; Will make the reference resistance of building in this receive the influence of processing procedure and cause its resistance different; So that the operating voltage level of digital analog converter output produces drift; Opereating specification changes, and finally makes the yield of chip descend.
In view of this; In exemplary embodiment of the present invention, through self-calibrating digital-to-analogue conversion method, digital analog converter can be made a feedback ratio with the voltage of its output; And the mirror of the resistance through the adjustment reference resistance, adjustment reference current source and current source array is than the size of, adjustment reference voltage or adjustment offset current; With the influence of minimizing processing procedure variation, and then promote the chip yield, reach low cost, dynamical circuit design.
Fig. 1 illustrates the functional block diagram of the signal processing system of one embodiment of the invention.Please refer to Fig. 1, in the present embodiment, signal processing system 100 comprises a digital analog converter 110, a comparing unit 120, a control unit 130 and a test compensating unit 140.Digital analog converter 110 receives a numeral input S
INAnd produce one first output voltage V
OUT1Comparing unit 120 receives first output voltage V
OUT1And comparison first output voltage V
OUT1With one first reference voltage V
REF1, to produce an output valve S
DAnd then control unit 130 receives output valve S
D, and utilize firmware or software to produce numeral input S in view of the above with the numerical value mapping mode
IN, with correcting digital analog converter 110.At this, 100 processors of signal processing system for example are video signals.
In detail, Fig. 2 illustrates the circuit diagram of the digital analog converter of Fig. 1.Please refer to Fig. 2, in the present embodiment, digital analog converter 110 comprises an operational amplifier OP, a current source array 112, a reference resistance R
ADJ, a reference current source I
REF, an output resistance R
OUTAn and compensating current element I
CPS
In the present embodiment, digital analog converter 110 couples comparing unit 120, and exports its first output voltage V
OUT1To comparing unit 120, to utilize comparing unit 120 and the first specific reference voltage V
REF1Compare.For example, comparing unit 120 for example can be an analog-digital converter or a comparator.If comparing unit 120 is to implement with a comparator, then this comparator receives first output voltage V
OUT1With the first reference voltage V
REF1Compare, to obtain first output voltage V
OUT1Level, as shown in Figure 1.If comparing unit 120 is to implement with an analog-digital converter, then this analog-digital converter can be with first output voltage V
OUT1Convert a digital signal into, to represent first output voltage V
OUT1Level.In other words, this moment, comparing unit 120 did not need to receive in addition the first reference voltage V
REF1
Then, signal processing system 100 is adjusted reference resistance R through control unit 130 again
ADJResistance, the adjustment the second reference voltage V
REF2Or adjustment reference current source I
REFCompare to calibrate with the mirror of current source array 112.Perhaps, signal processing system 100 also can be adjusted offset current I through test compensating unit 140
CPSSize, to compensate first output voltage V
OUT1Because of the differential nonlinearity error (Differential non-linearity,
DNL) skew (offset) that caused.
Furthermore, first output voltage V
OUT1After exporting analog-digital converter or comparator to, its comparative result can be sent to control unit 130.Then, control unit 130 can decide how to adjust digital analog converter 110 through firmware (firmware) or software (software) by pre-conditioned.For example, control unit 130 can be selected to adjust reference resistance RADJ, the adjustment second reference voltage V through the loop of voltage transitions current source
REF2Or adjustment reference current source I
REFMirror ratio with current source array 112.Wherein, the loop of this voltage transitions current source for example comprises operational amplifier OP, reference resistance R
ADJAnd reference current source I
REF
In detail, Fig. 3 illustrates the method flow diagram of resistance of the control unit adjustment reference resistance of one embodiment of the invention.Please refer to Fig. 1 to Fig. 3, in the present embodiment, self-calibrating digital-to-analogue conversion method for example is to be suitable for signal processing system 100 and the digital analog converter 110 that Fig. 1 and Fig. 2 illustrate, but the invention is not restricted to this.
At first, in step S300, control unit 130 given numeral input S
INTo digital analog converter 110.Wherein, numeral input S
INIt for example is a video signal.Then, in step S302, digital analog converter 110 is according to numeral input S
INFirst output voltage V that output is corresponding
OUT1To comparing unit 120.Afterwards, in step S304, control unit 130 reads an output valve S of comparing unit 120
D, to judge first output voltage V
OUT1Level whether in a desired extent.In the present embodiment, comparing unit 120 for example is an analog-digital converter, so output valve S
DIt for example is first output voltage V
OUT1A digital signal that gets via the analog digital conversion, it represents first output voltage V
OUT1Level.
Continue it, in step S306, control unit 130 is judged first output voltage V
OUT1Level whether in desired extent.If first output voltage V
OUT1Level in desired extent, expression reference resistance RADJ receives the influence of process variation less, then this moment, control unit 130 was not adjusted reference resistance R
ADJResistance, and finish the operation of self-calibrating.On the contrary, if first output voltage V
OUT1Level not in desired extent, then control unit 130 can adjustment reference resistance R
ADJResistance, to carry out self-calibrating.Be with, if first output voltage V
OUT1Level not in desired extent, self-calibrating digital-to-analogue conversion method can be carried out step S308.
In step S308, control unit 130 is further judged first output voltage V
OUT1Level whether greater than a specific desired value.In step S310, if first output voltage V
OUT1Level greater than this desired value, control unit 130 increases reference resistance R
ADJResistance, to reach the purpose of self-calibrating.On the contrary, in step S312, if the level of first output voltage is less than or equal to this desired value, control unit 130 reduces reference resistance R
ADJResistance, can reach the purpose of self-calibrating equally.Therefore, behind control unit 130 end step S310 or S312, self-calibrating digital-to-analogue conversion method can be got back to step S302 once more, to proceed self-calibrating.In other words, through above-mentioned self-calibrating method, control unit 130 is according to first output voltage V
OUT1Level whether in desired extent, whether decision adjusts reference resistance R
ADJResistance, to adjust first output voltage V
OUT1
What deserves to be mentioned is, in the loop of voltage transitions current source, as reference resistance R
ADJResistance when increasing, reference current source I
REFThe reference electrode that the is provided reduction that fails to be convened for lack of a quorum is so that first output voltage V
OUT1Level can be less than this desired value.On the contrary, as reference resistance R
ADJResistance when reducing, reference current source I
REFThe reference electrode that the is provided increase that fails to be convened for lack of a quorum is so that first output voltage V
OUT1Level can be greater than this desired value.
In other words, in the present embodiment, control unit 130 is reading output valve S
DAfterwards, according to output valve S
DSelect to increase or reduce reference resistance R
ADJResistance, with the correcting digital analog converter.In addition, the self-calibrating digital-to-analogue conversion method of present embodiment is the reference resistance R through adjustment digital analog converter 110
ADJResistance reduce the influence that processing procedure changes.In another embodiment, self-calibrating digital-to-analogue conversion method also can be selected the reference current source I through adjustment digital analog converter 110
REFWith the mirror ratio of current source array 112, the second reference voltage V that is perhaps received through adjustment digital analog converter 110
REF2, reach adjustment first output voltage V
OUT1Purpose, to reduce the influence that processing procedure changes.
Fig. 4 promptly illustrates the control unit adjustment reference current source of one embodiment of the invention and the method flow diagram of the mirror ratio of current source array.Please refer to Fig. 1, Fig. 2 to Fig. 4, in the present embodiment, reference current source I
REFWith current source array 112 for example is to utilize a plurality of current mirrors to implement, and therefore adjustment mirror ratio between the two can change the electric current of current source array 112 outputs, and then reaches adjustment first output voltage V
OUT1Purpose.
In the present embodiment, so-called " mirror ratio " for example is meant at reference current source I
REFWith master and servant (master/slave) the number of transistors purpose ratio that is used for forming current mirror in the current source array 112.Generally speaking, when identical,, can estimate servant's side electric current by the primary side current of current mirror according to master and servant's number of transistors purpose ratio as if the transistorized breadth length ratio (width/length ratio) of implementing current mirror.For example, in the present embodiment, if reference current source I
REFThe reference current that provides is the primary side current of current mirror, and the electric current of current source array 112 outputs is servant's side electric current, and master and servant's number of transistors purpose ratio is 1: 10 o'clock between the two, and the electric current that then can estimate current source array 112 outputs is reference current source I
REF10 times of the reference current that provides.In other words, as reference current source I
REFThe reference current that provides is fixedly the time, and adjustment mirror ratio between the two can change the electric current of current source array 112 outputs.
In the present embodiment, the self-calibrating digital-to-analogue conversion method of adjustment mirror ratio is similar to the self-calibrating digital-to-analogue conversion method of the adjustment reference resistance resistance of Fig. 3, and thought difference between the two for example is step S410 and S412.In step S410, if first output voltage V
OUT1Level greater than this desired value, control unit 130 reduces reference current source I
REFMirror ratio with current source array 112; On the contrary, in step S412, if the level of first output voltage is less than or equal to this desired value, control unit 130 increases both mirror ratios.Therefore, through adjustment mirror ratio, self-calibrating digital-to-analogue conversion method can reach the purpose of self-calibrating equally.
In other words, in the present embodiment, control unit 130 is reading competitive list output valve S
DAfterwards, according to output valve S
DSelect to increase or reduce reference current source I
REFWith the mirror ratio of current source array 112, with correcting digital analog converter 110.In another embodiment, self-calibrating digital-to-analogue conversion method also can be selected through adjusting the second reference voltage V that digital analog converter 110 is received
REF2, reach adjustment first output voltage V
OUT1Purpose, to reduce the influence that processing procedure changes.
The control unit that Fig. 5 promptly illustrates one embodiment of the invention is adjusted the method flow diagram of second reference voltage.Please refer to Fig. 1, Fig. 2 to Fig. 5, in the present embodiment, the non-inverting input of operational amplifier OP is coupled to adjustable second a reference voltage V
REF2, and its reverse input end is coupled to reference current source I
REFWith reference resistance R
ADJBetween node.Therefore, as the second reference voltage V
REF2During change, also can change simultaneously and flow through reference resistance R
ADJElectric current, and then change the electric current of current source array 112 outputs, reach adjustment first output voltage V
OUT1Purpose.
In the present embodiment, the self-calibrating digital-to-analogue conversion method of adjusting second reference voltage is similar to the self-calibrating digital-to-analogue conversion method of the adjustment reference resistance resistance of Fig. 3, and thought difference between the two for example is step S510 and S512.In step S510, if first output voltage V
OUT1Level greater than this desired value, control unit 130 reduces by the second reference voltage V
REF2On the contrary, in step S512, if the level of first output voltage is less than or equal to this desired value, control unit 130 increases by the second reference voltage V
REF2Therefore, through adjusting second reference voltage, self-calibrating digital-to-analogue conversion method can reach the purpose of self-calibrating equally.
In other words, in the present embodiment, control unit 130 is reading competitive list output valve S
DAfterwards, according to output valve S
DSelect to increase or reduce the second reference voltage V
REF2, with correcting digital analog converter 110.
On the other hand, Fig. 6 illustrates the method flow diagram of the test compensating unit adjustment offset current of one embodiment of the invention.Please refer to Fig. 1, Fig. 2 and Fig. 6, in the present embodiment, test compensating unit 140 inputs one test signal S
TESTTo digital analog converter 110, to produce one second output voltage V
OUT2, like step S600.Wherein, test signal S
TESTFor example be a slope (ramp) signal, digital analog converter 110 is carried out linearity test.Then, in step S602, test signal S
TESTJudge second output voltage V of digital analog converter 110
OUT2Whether with test signal S
TESTCoupling.At this, if test signal S
TESTBe the acclivity signal, then second output voltage V
OUT2Variation tendency must be that dull (monotonic) rises, beginning and test signal S
TESTCoupling.Similarly, if test signal S
TESTBe the decline ramp signal, then second output voltage V
OUT2Variation tendency must descend for dullness, the beginning with test signal S
TESTCoupling.And then test compensating unit 140 is according to second output voltage V
OUT2With test signal S
TESTWhether mate, whether decision adjusts offset current I
CPSSize.
Therefore, if second output voltage V
OUT2With test signal S
TESTCoupling is then tested compensating unit 140 uncomfortable reorganizing and bringing up to full strength and is repaid electric current I this moment
CPSSize, and finish the operation of self-calibrating.If second output voltage V
OUT2With test signal S
TESTDo not match, in step S604, test compensating unit 140 can be judged corresponding second output voltage V
OUT2One lose whether sign indicating number (a missing code) is voltage decreases.If losing sign indicating number is voltage decreases, in step S606, test compensating unit 140 increases offset current I
CPSSize; If losing sign indicating number is not voltage decreases, in step S608, test compensating unit 140 reduces offset current I
CPSSize.Therefore, behind control unit 130 end step S506 or S608, self-calibrating digital-to-analogue conversion method can be got back to step S600 once more, to proceed self-calibrating.In other words, the test compensating unit of present embodiment selects to increase or reduce the size of offset current according to its judged result.
Be also can adjust offset current I through test compensating unit 140 with, signal processing system 100
CPSSize, to compensate first output voltage V
OUT1The skew that is caused because of the differential nonlinearity error.
Fig. 7 illustrates the look-up table of one embodiment of the invention.Please refer to Fig. 1 and Fig. 7, in the present embodiment, control unit 130 for example comprises look-up table that Fig. 7 illustrates.Producing numeral input S with the numerical value mapping mode
INThe time, control unit 130 can be found out output valve S in look-up table
DPairing numeral input S
IN, with correcting digital analog converter 110.
In look-up table, each row of first hurdle are represented reference resistance R
ADJCompared to the scope of difference (variation) percentage of standard resistance, the resolution of compensation is depended in the division of its scope.First output voltage V of corresponding each disparity range is represented on four hurdles, second hurdle to the respectively
OUT1, output valve S
DAnd numeral input S
INIn the look-up table of Fig. 7, the magnitude relationship of second hurdle and each parameter of third column is distinguished as follows: V
NX＞...＞V
NB＞V
NA＞V
TYP＞V
PA＞V
PB＞...＞V
PXLevel
NX＞...＞Level
NB＞Level
NA＞Level
PA＞Level
PB＞...＞Level
PX
In the present embodiment, output valve S
DAnd numeral input S
INFor example be respectively one 10 and one 2 s' digital signal, its figure place is the resolution that depends on compensation.For example, be 0% row in difference percentage, suppose first output voltage V
TYP=1.40 volts, reference resistance R
ADJVery nearly the same with the standard resistance, therefore need not adjust.In difference percentage is R
P1%～R
P2The row of %, its reference resistance R
ADJFor just changing (positive resister variation), for example+1%～+ 10%, so first output voltage V
OUT1Can reach V
PA=1.27 volts.On the contrary, in difference percentage be-R
N1%～-R
N2The row of %, its reference resistance R
ADJBe negative change (negative resister variation), for example-1%～-10%, so first output voltage V
OUT1Can reach V
NA=1.55 volts.Under above-mentioned three kinds of situation, the designer can select not to reference resistance R according to actual demand
ADJAdjust, and numeral is imported S
INBe set at wherein a kind of aspect of 2 position digital signals, for example S
IN[0:1]=00, its figure place are the resolution that depends on compensation.
On the other hand, be R in difference percentage
N3%～R
N4The row of %, its reference resistance R
ADJNegative variation for-11%～-17%, first output voltage V at this moment
OUT1Excursion V
NA～V
NBBe between 1.57～1.68 volts.Therefore, comparing unit 120 compares first output voltage V
OUT1With the first reference voltage V
REF1, and the output valve S that produces
DBe between Level
NA～Level
NBDigital signal with 10 is represented it, then output valve S
DBe between 493～527.Numeral input this moment S
INCan be set at wherein a kind of aspect of 2 position digital signals, for example S
IN[0:1]=01.
In addition, be R in difference percentage
P (X-1)%～R
PXThe row of %, its reference resistance R
ADJJust variation for+11%～+ 25%, first output voltage V at this moment
OUT1Variation can reach V
PX=1.26 volts.Therefore, output valve S
DBe at Level
PXBelow.Digital signal with 10 is represented it, then output valve S
DLess than 396.Numeral input this moment S
INCan be set at wherein a kind of aspect of 2 position digital signals, for example S
IN[0:1]=11.Similarly, in difference percentage be-R
N (X-1)%～-R
NXThe row of %, its reference resistance R
ADJNegative variation for-18%～-25%, its V
NX=1.86 volts, Level
NX=528, S
IN[0:1]=10.
In the present embodiment, the designer can divide reference resistance R based on the resolution of compensation
ADJCompared to the scope of the difference percentage of standard resistance, to design suitable look-up table.The illustrative each item numerical value of institute is only explained in order to enforcement in the foregoing description, and need not limit the present invention.In addition, though the look-up table of Fig. 7 only illustrates reference resistance R
ADJExemplary embodiment, yet the adjustment that the mirror of reference current source and current source array utilizes look-up table than, second reference voltage and compensating current element is when can just repeating no more at this by that analogy.
Therefore, in the present embodiment, through the look-up table of Fig. 7, control unit receives output valve S
D, and can utilize firmware or software to produce numeral input S in view of the above with the numerical value mapping mode
IN, with correcting digital analog converter 110.
In sum, in exemplary embodiment of the present invention, build reference resistance in the digital analog converter, and use above-mentioned digital-to-analogue conversion method, it possesses self-calibrating mechanism, can avoid the influence of process variation, increases its yield.In addition, the digital-to-analogue conversion method of exemplary embodiment of the present invention can effectively be improved the gain error and the offset error of digital analog converter.
Though the present invention discloses as above with embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (14)
1. signal processing system comprises:
One digital analog converter receives a numeral input and produces one first output voltage;
One comparing unit receives this first output voltage and relatively this first output voltage and one first reference voltage, to produce an output valve; And
One control unit receives this output valve, and utilizes firmware or software to produce and should numeral import with the numerical value mapping mode in view of the above, to proofread and correct this digital analog converter.
2. signal processing system according to claim 1, wherein this digital analog converter comprises a reference resistance, this control unit is selected increase according to this output valve or is reduced the resistance of this reference resistance, to proofread and correct this digital analog converter.
3. signal processing system according to claim 1; Wherein this digital analog converter comprises a reference current source and a current source array; This control unit selects to increase or reduce the mirror ratio of this reference current source and this current source array according to this output valve, to proofread and correct this digital analog converter.
4. signal processing system according to claim 1, wherein this digital analog converter receives one second reference voltage, and this control unit is selected to increase or reduce this second reference voltage according to this output valve, to proofread and correct this digital analog converter.
5. signal processing system according to claim 1 also comprises:
One test compensating unit is imported a test signal to this digital analog converter, so that this digital analog converter produces one second output voltage, and judges whether this second output voltage matees with this test signal.
6. signal processing system according to claim 5, wherein this digital analog converter comprises a compensating current element, is used to provide an offset current, this test compensating unit selects to increase or reduce the size of this offset current according to its judged result.
7. signal processing system according to claim 1; Wherein this control unit comprises a look-up table; Producing with the numerical value mapping mode should the numeral input time, this control unit finds out in this look-up table that this output valve is pairing should the numeral input, to proofread and correct this digital analog converter.
8. a self-calibrating digital-to-analogue conversion method is used for a digital analog converter, and this self-calibrating digital-to-analogue conversion method comprises:
Receive a numeral input and produce one first output voltage;
Receive this first output voltage and relatively this first output voltage and one first reference voltage, to produce an output valve; And
Receive this output valve, and utilize firmware or software to produce and numeral to import in view of the above, to proofread and correct this digital analog converter with the numerical value mapping mode.
9. self-calibrating digital-to-analogue conversion method according to claim 8; Wherein this digital analog converter comprises a reference resistance; In this step of proofreading and correct this digital analog converter; Select to increase or reduce the resistance of this reference resistance according to this output valve, to proofread and correct this digital analog converter.
10. self-calibrating digital-to-analogue conversion method according to claim 8; Wherein this digital analog converter comprises a reference current source and a current source array; In this step of proofreading and correct this digital analog converter; Select to increase or reduce the mirror ratio of this reference current source and this current source array according to this output valve, to proofread and correct this digital analog converter.
11. self-calibrating digital-to-analogue conversion method according to claim 8; Wherein this digital analog converter receives one second reference voltage; In this step of proofreading and correct this digital analog converter; Select to increase or reduce this second reference voltage according to this output valve, to proofread and correct this digital analog converter.
12. self-calibrating digital-to-analogue conversion method according to claim 8 also comprises:
Import a test signal to this digital analog converter, so that this digital analog converter produces one second output voltage; And
Judge whether this second output voltage matees with this test signal.
13. self-calibrating digital-to-analogue conversion method according to claim 12, wherein this digital analog converter comprises a compensating current element, is used to provide an offset current, and this self-calibrating digital-to-analogue conversion method also comprises:
Select to increase or reduce the size of this offset current according to this judged result.
14. self-calibrating digital-to-analogue conversion method according to claim 8 wherein utilizes firmware or software to comprise with this step that the numerical value mapping mode produces this numeral input:
In a look-up table, find out this output valve pairing should numeral input, to proofread and correct this digital analog converter.
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| CN104065382A (en) * | 2013-03-22 | 2014-09-24 | 西安电子科技大学 | Digital calibration technique for segmented current steering DAC |
| CN108259804A (en) * | 2016-12-29 | 2018-07-06 | 扬智科技股份有限公司 | Video output system and its cohered video compensation method |
| CN109379081A (en) * | 2018-10-29 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | A kind of digital analog converter and its control method |
| CN110880933A (en) * | 2018-09-06 | 2020-03-13 | 格芯公司 | On-chip correction circuit with half-step resolution and method thereof |
| CN111049520A (en) * | 2018-10-11 | 2020-04-21 | 瑞昱半导体股份有限公司 | Digital-to-analog converter device and correction method |
| CN112217517A (en) * | 2020-10-09 | 2021-01-12 | 珠海零边界集成电路有限公司 | Method for adjusting digital-to-analog converter and related equipment |
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| CN104065382B (en) * | 2013-03-22 | 2017-05-31 | 西安电子科技大学 | For the digital calibration circuit of segmented current steering DAC |
| CN104065382A (en) * | 2013-03-22 | 2014-09-24 | 西安电子科技大学 | Digital calibration technique for segmented current steering DAC |
| CN108259804B (en) * | 2016-12-29 | 2021-06-29 | 扬智科技股份有限公司 | Video output system and related video signal compensation method thereof |
| CN108259804A (en) * | 2016-12-29 | 2018-07-06 | 扬智科技股份有限公司 | Video output system and its cohered video compensation method |
| CN110880933A (en) * | 2018-09-06 | 2020-03-13 | 格芯公司 | On-chip correction circuit with half-step resolution and method thereof |
| CN111049520B (en) * | 2018-10-11 | 2023-05-23 | 瑞昱半导体股份有限公司 | Digital-to-analog converter device and correction method |
| CN111049520A (en) * | 2018-10-11 | 2020-04-21 | 瑞昱半导体股份有限公司 | Digital-to-analog converter device and correction method |
| CN109379081B (en) * | 2018-10-29 | 2022-06-10 | 合肥本源量子计算科技有限责任公司 | Digital-analog converter and control method thereof |
| CN109379081A (en) * | 2018-10-29 | 2019-02-22 | 合肥本源量子计算科技有限责任公司 | A kind of digital analog converter and its control method |
| CN112217517A (en) * | 2020-10-09 | 2021-01-12 | 珠海零边界集成电路有限公司 | Method for adjusting digital-to-analog converter and related equipment |
| CN114326900A (en) * | 2021-12-29 | 2022-04-12 | 华中科技大学 | High-precision adjustable reference voltage generation circuit |
| CN114650055A (en) * | 2022-03-24 | 2022-06-21 | 深圳市晶扬电子有限公司 | Adaptive delta modulation analog-digital converter with calibration circuit and calibration method |
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