CN102811058B - Signal processing system and self-calibrating digital-to-analogue conversion method thereof - Google Patents
Signal processing system and self-calibrating digital-to-analogue conversion method thereof Download PDFInfo
- Publication number
- CN102811058B CN102811058B CN201110144370.9A CN201110144370A CN102811058B CN 102811058 B CN102811058 B CN 102811058B CN 201110144370 A CN201110144370 A CN 201110144370A CN 102811058 B CN102811058 B CN 102811058B
- Authority
- CN
- China
- Prior art keywords
- analog converter
- digital analog
- digital
- output voltage
- self
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Abstract
A kind of signal processing system, it comprises a digital analog converter, a comparing unit and a control unit.Digital analog converter receives a numeral and inputs and produce an output voltage.Comparing unit receives output voltage and compares the first output voltage and a reference voltage, to produce an output valve.Control unit receives output valve, and utilizes firmware or software to produce numeral input, with correcting digital analog converter in data value maps mode accordingly.In addition, a kind of self-calibrating digital-to-analogue conversion method is also suggested.
Description
Technical field
The invention relates to a kind of signal processing system and digital-to-analogue conversion method thereof, and relate to a kind of signal processing system and digital-to-analogue conversion method thereof of tool self-calibrating mechanism especially.
Background technology
Digital analog converter (digital-to-analog converter, DAC) is widely used in digital circuit now, is such as output in the digital analog converter (video DAC, TVDAC) of video, TV.Known digital analog converter can have an outer meeting resistance usually, and its object arranged is the reference resistance of reference current in time exporting as digital analog converter inside.But arrange the design of an outer meeting resistance outside digital analog converter, although can be used for reducing the impact of process variation, this design still has probability to cause the loss of yield because of process variation.
Summary of the invention
The invention provides a kind of signal processing system, its digital analog converter can be made to possess self-calibrating mechanism, to avoid the impact of process variation, increase its yield.
The invention provides a kind of self-calibrating digital-to-analogue conversion method, for the digital analog converter of a built-in reference resistance, this digital analog converter can be made to possess self-calibrating mechanism, to avoid the impact of process variation, increase its yield.
The invention provides a kind of signal processing system, it comprises a digital analog converter, a comparing unit and a control unit.Digital analog converter receives a numeral and inputs and produce one first output voltage.Comparing unit receives the first output voltage and compares the first output voltage and one first reference voltage, to produce an output valve.Control unit receives output valve, and utilizes firmware or software to produce numeral input, with correcting digital analog converter in data value maps mode accordingly.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference resistance.Control unit selects according to output valve the resistance increasing or reduce reference resistance, with correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference current source and a current source array.Control unit selects according to output valve the mirror ratio increasing or reduce reference current source and current source array, with correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter receives one second reference voltage.Control unit is selected to increase or reduce by the second reference voltage, with correcting digital analog converter according to output valve.
In an embodiment of the present invention, above-mentioned signal processing system also comprises a test compensating unit.Test compensating unit inputs a test signal to digital analog converter, produces one second output voltage to make digital analog converter.Test compensating unit judges whether the second output voltage mates with test signal.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a compensating current element, for providing an offset current.Test compensating unit selects according to its judged result the size increasing or reduce offset current.
In an embodiment of the present invention, above-mentioned control unit comprises a look-up table.When producing numeral input in data value maps mode, control unit finds out the numeral input corresponding to output valve in a lookup table, with correcting digital analog converter.
The invention provides a kind of self-calibrating digital-to-analogue conversion method, for a digital analog converter.Self-calibrating digital-to-analogue conversion method comprises the steps.Receive a numeral input and produce one first output voltage.Receive the first output voltage and compare the first output voltage and one first reference voltage, to produce an output valve.Receive output valve, and utilize firmware or software to produce numeral input, with correcting digital analog converter in data value maps mode accordingly.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference resistance.In the step of correcting digital analog converter, select according to output valve the resistance increasing or reduce reference resistance, with correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a reference current source and a current source array.In the step of correcting digital analog converter, select according to output valve the mirror ratio increasing or reduce reference current source and current source array, with correcting digital analog converter.
In an embodiment of the present invention, above-mentioned digital analog converter receives one second reference voltage.In the step of correcting digital analog converter, select to increase or reduce by the second reference voltage, with correcting digital analog converter according to output valve.
In an embodiment of the present invention, above-mentioned self-calibrating digital-to-analogue conversion method also comprises the steps.Input a test signal to digital analog converter, produce one second output voltage to make digital analog converter.Judge whether the second output voltage mates with test signal.
In an embodiment of the present invention, above-mentioned digital analog converter comprises a compensating current element, is suitable for providing an offset current.Self-calibrating digital-to-analogue conversion method also comprises the size selecting to increase or reduce offset current according to judged result.
In an embodiment of the present invention, the above-mentioned step utilizing firmware or software to produce the input of this numeral in data value maps mode comprises the steps.The numeral input corresponding to output valve is found out, with correcting digital analog converter in a look-up table.
Based on above-mentioned, in exemplary embodiment of the present invention, the built-in reference resistance of digital analog converter, and use above-mentioned digital-to-analogue conversion method, it possesses self-calibrating mechanism, can avoid the impact of process variation, increases its yield.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate institute's accompanying drawings to be described in detail below.
Accompanying drawing explanation
Fig. 1 illustrates the functional block diagram of the signal processing system of one embodiment of the invention.
Fig. 2 illustrates the circuit diagram of the digital analog converter of Fig. 1.
Fig. 3 illustrates the method flow diagram of the resistance of the adjustment reference resistance of one embodiment of the invention.
Fig. 4 illustrates the method flow diagram of the adjustment reference current source of one embodiment of the invention and the mirror ratio of current source array.
Fig. 5 illustrates the method flow diagram of adjustment second reference voltage of one embodiment of the invention.
Fig. 6 illustrates the method flow diagram of the adjustment offset current of one embodiment of the invention.
Fig. 7 illustrates the look-up table of one embodiment of the invention.
[main element label declaration]
100: signal processing system 110: digital analog converter
112: current source array 120: comparing unit
130: control unit 140: test compensating unit
I
rEF: reference current source I
cPS: compensating current element
R
oUT: output resistance R
aDJ: reference resistance
V
rEF1: the first reference voltage V
rEF2: the second reference voltage
V
oUT1: the first output voltage V
oUT2: the second output voltage
OP: operational amplifier S
d: output valve, digital signal
S
iN: digital defeated S
tEST: test signal
S300, S302, S304, S306, S308, S310, S312: the method step of the resistance of adjustment reference resistance
S400, S402, S404, S406, S408, S410, S412: the method step of adjustment reference current source and the mirror ratio of current source array
S500, S502, S504, S506, S 508, S510, S512: the method step adjusting the second reference voltage
S600, S602, S604, S606, S608: the method step of adjustment offset current
Embodiment
If will be built in wherein in the known reference resistance being external in digital analog converter, this built-in reference resistance will be made to be subject to the impact of processing procedure and to cause its resistance different, so that the operating voltage level that digital analog converter exports produces drift, opereating specification changes, and finally makes the yield of chip decline.
In view of this, in exemplary embodiment of the present invention, by self-calibrating digital-to-analogue conversion method, the voltage that digital analog converter can be exported makes a feedback ratio comparatively, and by the mirror ratio of the resistance of adjustment reference resistance, adjustment reference current source and current source array, adjust reference voltage or adjust the size of offset current, to reduce the impact of processing procedure change, and then promote chip yield, reach low cost, dynamical circuit design.
Fig. 1 illustrates the functional block diagram of the signal processing system of one embodiment of the invention.Please refer to Fig. 1, in the present embodiment, signal processing system 100 comprises digital analog converter 110, comparing unit 120, control unit 130 and a test compensating unit 140.Digital analog converter 110 receives a numeral input S
iNand produce one first output voltage V
oUT1.Comparing unit 120 receives the first output voltage V
oUT1and compare the first output voltage V
oUT1with one first reference voltage V
rEF1, to produce an output valve S
d.And then control unit 130 receives output valve S
d, and utilize firmware or software to produce numeral input S in data value maps mode accordingly
iN, with correcting digital analog converter 110.At this, person handled by signal processing system 100 is such as a video signal.
Specifically, Fig. 2 illustrates the circuit diagram of the digital analog converter of Fig. 1.Please refer to Fig. 2, in the present embodiment, digital analog converter 110 comprises an operational amplifier OP, current source array 112, reference resistance R
aDJ, a reference current source I
rEF, an output resistance R
oUTand a compensating current element I
cPS.
In the present embodiment, digital analog converter 110 couples comparing unit 120, and exports its first output voltage V
oUT1to comparing unit 120, to utilize comparing unit 120 and specific first reference voltage V
rEF1compare.For example, comparing unit 120 can be such as an analog-digital converter or a comparator.If comparing unit 120 implements with a comparator, then this comparator receives the first output voltage V
oUT1with the first reference voltage V
rEF1compare, to obtain the first output voltage V
oUT1level, as shown in Figure 1.If comparing unit 120 implements with an analog-digital converter, then this analog-digital converter can by the first output voltage V
oUT1be converted to a digital signal, to represent the first output voltage V
oUT1level.In other words, now comparing unit 120 does not need to receive the first reference voltage V in addition
rEF1.
Then, signal processing system 100 adjusts reference resistance R by control unit 130 again
aDJresistance, adjust the second reference voltage V
rEF2or adjustment reference current source I
rEFcompare with the mirror of current source array 112 to calibrate.Or signal processing system 100 also adjusts offset current I by test compensating unit 140
cPSsize, to compensate the first output voltage V
oUT1because of differential nonlinearity error (Differentialnon-linearity,
dNL) skew (offset) that causes.
Furthermore, the first output voltage V
oUT1after exporting analog-digital converter or comparator to, its comparative result can be sent to control unit 130.Then, control unit 130 can, by pre-conditioned, decide how to adjust digital analog converter 110 by firmware (firmware) or software (software).Such as, control unit 130 can be selected to adjust reference resistance RADJ by the loop of voltage transitions current source, adjust the second reference voltage V
rEF2or adjustment reference current source I
rEFwith the mirror ratio of current source array 112.Wherein, the loop of this voltage transitions current source such as comprises operational amplifier OP, reference resistance R
aDJand reference current source I
rEF.
Specifically, Fig. 3 illustrates the method flow diagram of the resistance of the control unit adjustment reference resistance of one embodiment of the invention.Please refer to Fig. 1 to Fig. 3, in the present embodiment, self-calibrating digital-to-analogue conversion method is such as be suitable for signal processing system 100 that Fig. 1 and Fig. 2 illustrate and digital analog converter 110, but the present invention is not limited thereto.
First, in step S300, the given numeral input S of control unit 130
iNto digital analog converter 110.Wherein, numeral input S
iNit is such as a video signal.Then, in step s 302, digital analog converter 110 is according to numeral input S
iNexport the first corresponding output voltage V
oUT1to comparing unit 120.Afterwards, in step s 304, control unit 130 reads an output valve S of comparing unit 120
d, to judge the first output voltage V
oUT1level whether in a desired extent.In the present embodiment, comparing unit 120 is such as an analog-digital converter, therefore output valve S
dsuch as the first output voltage V
oUT1the digital signal obtained via Analog-digital Converter, it represents the first output voltage V
oUT1level.
Then, in step S306, control unit 130 judges the first output voltage V
oUT1level whether in desired extent.If the first output voltage V
oUT1level in desired extent, represent that reference resistance RADJ is less by the impact of process variation, then now control unit 130 does not adjust reference resistance R
aDJresistance, and terminate the operation of self-calibrating.On the contrary, if the first output voltage V
oUT1level not in desired extent, then control unit 130 can adjust reference resistance R
aDJresistance, to carry out self-calibrating.If therefore the first output voltage V
oUT1level not in desired extent, self-calibrating digital-to-analogue conversion method can carry out step S308.
In step S308, control unit 130 judges the first output voltage V further
oUT1level whether be greater than a specific desired value.In step S310, if the first output voltage V
oUT1level be greater than this desired value, control unit 130 increases reference resistance R
aDJresistance, to reach the object of self-calibrating.On the contrary, in step S312, if the level of the first output voltage is less than or equal to this desired value, control unit 130 reduces reference resistance R
aDJresistance, the object of self-calibrating can be reached equally.Therefore, when after control unit 130 end step S310 or S312, self-calibrating digital-to-analogue conversion method can get back to step S302 again, to proceed self-calibrating.In other words, by above-mentioned self-calibrating method, control unit 130 is according to the first output voltage V
oUT1level whether in desired extent, determine whether adjust reference resistance R
aDJresistance, to adjust the first output voltage V
oUT1.
It is worth mentioning that, in the loop of voltage transitions current source, as reference resistance R
aDJresistance increase time, reference current source I
rEFthe reference current provided can reduce, to make the first output voltage V
oUT1level can be less than this desired value.On the contrary, as reference resistance R
aDJresistance reduce time, reference current source I
rEFthe reference current provided can increase, to make the first output voltage V
oUT1level can be greater than this desired value.
In other words, in the present embodiment, control unit 130 is at reading output valve S
dafterwards, according to output valve S
dselect to increase or reduce reference resistance R
aDJresistance, with correcting digital analog converter.In addition, the self-calibrating digital-to-analogue conversion method of the present embodiment is the reference resistance R by adjusting digital analog converter 110
aDJresistance reduce processing procedure change impact.In another embodiment, self-calibrating digital-to-analogue conversion method also can select the reference current source I by adjusting digital analog converter 110
rEFwith the mirror ratio of current source array 112, or by adjusting the second reference voltage V that digital analog converter 110 receives
rEF2, reach adjustment first output voltage V
oUT1object, with reduce processing procedure change impact.
Namely Fig. 4 illustrates the control unit adjustment reference current source of one embodiment of the invention and the method flow diagram of the mirror ratio of current source array.Please refer to Fig. 1, Fig. 2 to Fig. 4, in the present embodiment, reference current source I
rEFbe such as utilize multiple current mirror to implement with current source array 112, therefore adjust mirror ratio between the two, the electric current that current source array 112 exports can be changed, and then reach adjustment first output voltage V
oUT1object.
In the present embodiment, so-called " mirror ratio " such as refers at reference current source I
rEFwith master and servant (master/slave) the number of transistors object ratio being used for forming current mirror in current source array 112.Generally speaking, if when the breadth length ratio (width/length ratio) implementing the transistor of current mirror is identical, according to master and servant's number of transistors object ratio, servant side electric current can be estimated by the primary side current of current mirror.For example, in the present embodiment, if reference current source I
rEFthe reference current provided is the primary side current of current mirror, and the electric current that current source array 112 exports is servant side electric current, and when master and servant's number of transistors object ratio is 1: 10 between the two, then the electric current that can estimate current source array 112 output is reference current source I
rEF10 times of the reference current provided.In other words, as reference current source I
rEFwhen the reference current provided is fixed, adjustment mirror ratio between the two, can change the electric current that current source array 112 exports.
In the present embodiment, the self-calibrating digital-to-analogue conversion method of adjustment mirror ratio is similar to the self-calibrating digital-to-analogue conversion method of the adjustment reference resistance resistance of Fig. 3, and only difference between the two is such as step S410 and S412.In step S410, if the first output voltage V
oUT1level be greater than this desired value, control unit 130 reduces reference current source I
rEFwith the mirror ratio of current source array 112; On the contrary, in step S412, if the level of the first output voltage is less than or equal to this desired value, the mirror ratio both control unit 130 increases.Therefore, by adjustment mirror ratio, self-calibrating digital-to-analogue conversion method can reach the object of self-calibrating equally.
In other words, in the present embodiment, control unit 130 is at the more single output valve S of reading
dafterwards, according to output valve S
dselect to increase or reduce reference current source I
rEFwith the mirror ratio of current source array 112, with correcting digital analog converter 110.In another embodiment, self-calibrating digital-to-analogue conversion method also can be selected by the second reference voltage V of receiving of adjustment digital analog converter 110
rEF2, reach adjustment first output voltage V
oUT1object, with reduce processing procedure change impact.
The control unit that namely Fig. 5 illustrates one embodiment of the invention adjusts the method flow diagram of the second reference voltage.Please refer to Fig. 1, Fig. 2 to Fig. 5, in the present embodiment, the non-inverting input of operational amplifier OP is coupled to an adjustable second reference voltage V
rEF2, and its reverse input end is coupled to reference current source I
rEFwith reference resistance R
aDJbetween node.Therefore, as the second reference voltage V
rEF2during change, also can change simultaneously and flow through reference resistance R
aDJelectric current, and then change current source array 112 export electric current, reach adjustment first output voltage V
oUT1object.
In the present embodiment, the self-calibrating digital-to-analogue conversion method adjusting the second reference voltage is similar to the self-calibrating digital-to-analogue conversion method of the adjustment reference resistance resistance of Fig. 3, and only difference between the two is such as step S510 and S512.In step S510, if the first output voltage V
oUT1level be greater than this desired value, control unit 130 reduces by the second reference voltage V
rEF2; On the contrary, in step S512, if the level of the first output voltage is less than or equal to this desired value, control unit 130 increases by the second reference voltage V
rEF2.Therefore, by adjusting the second reference voltage, self-calibrating digital-to-analogue conversion method can reach the object of self-calibrating equally.
In other words, in the present embodiment, control unit 130 is at the more single output valve S of reading
dafterwards, according to output valve S
dselect to increase or reduce by the second reference voltage V
rEF2, with correcting digital analog converter 110.
On the other hand, Fig. 6 illustrates the method flow diagram of the test compensating unit adjustment offset current of one embodiment of the invention.Please refer to Fig. 1, Fig. 2 and Fig. 6, in the present embodiment, test compensating unit 140 inputs a test signal S
tESTto digital analog converter 110, to produce one second output voltage V
oUT2, as step S600.Wherein, test signal S
tESTsuch as a slope (ramp) signal, to carry out linearity test to digital analog converter 110.Then, in step S602, test signal S
tESTjudge the second output voltage V of digital analog converter 110
oUT2whether with test signal S
tESTcoupling.At this, if test signal S
tESTfor acclivity signal, then the second output voltage V
oUT2variation tendency must be that dull (monotonic) rises, begin and test signal S
tESTcoupling.Similarly, if test signal S
tESTfor decline ramp signal, then the second output voltage V
oUT2variation tendency must be monotonic decreasing, begin and test signal S
tESTcoupling.And then test compensating unit 140 is according to the second output voltage V
oUT2with test signal S
tESTwhether mate, determine whether adjust offset current I
cPSsize.
Therefore, if the second output voltage V
oUT2with test signal S
tESTcoupling, then now test uncomfortable the reorganizing and bringing up to full strength of compensating unit 140 and repay electric current I
cPSsize, and terminate the operation of self-calibrating.If the second output voltage V
oUT2with test signal S
tESTdo not mate, in step s 604, test compensating unit 140 can judge corresponding second output voltage V
oUT2one lose code (missing code) whether be that voltage diminishes.If losing code is that voltage diminishes, in step S606, test compensating unit 140 increases offset current I
cPSsize; If lose code not for voltage diminishes, in step S608, test compensating unit 140 reduces offset current I
cPSsize.Therefore, when after control unit 130 end step S506 or S608, self-calibrating digital-to-analogue conversion method can get back to step S600 again, to proceed self-calibrating.In other words, the test compensating unit of the present embodiment selects according to its judged result the size increasing or reduce offset current.
Therefore signal processing system 100 also adjusts offset current I by test compensating unit 140
cPSsize, to compensate the first output voltage V
oUT1because of the skew that differential nonlinearity error causes.
Fig. 7 illustrates the look-up table of one embodiment of the invention.Please refer to Fig. 1 and Fig. 7, in the present embodiment, control unit 130 such as comprises Fig. 7 and illustrates look-up table.Numeral input S is being produced in data value maps mode
iNtime, control unit 130 can find out output valve S in a lookup table
dcorresponding numeral input S
iN, with correcting digital analog converter 110.
In a lookup table, the first hurdle respectively arranges and represents reference resistance R
aDJcompared to the scope of difference (variation) percentage of standard resistance, the resolution of compensation is depended in the division of its scope.Second hurdle to the 4th hurdle represents the first output voltage V of corresponding each disparity range respectively
oUT1, output valve S
dand numeral input S
iN.In the look-up table of Fig. 7, the magnitude relationship of the second hurdle and each parameter of third column is as follows respectively: V
nX> ... > V
nB> V
nA> V
tYP> V
pA> V
pB> ... > V
pX; Level
nX> ... > Level
nB> Level
nA> Level
pA> Level
pB> ... > Level
pX.
In the present embodiment, output valve S
dand numeral input S
iNbe such as the digital signal of one 10 and one 2 respectively, its figure place is the resolution depending on compensation.For example, be the row of 0% in difference percentage, suppose the first output voltage V
tYP=1.40 volts, reference resistance R
aDJvery nearly the same with standard resistance, therefore need not adjust.Be R in difference percentage
p1% ~ R
p2the row of %, its reference resistance R
aDJfor just changing (positive resister variation), such as+1% ~+10%, therefore the first output voltage V
oUT1v can be reached
pA=1.27 volts.On the contrary, be-R in difference percentage
n1% ~-R
n2the row of %, its reference resistance R
aDJfor negative change (negative resister variation), such as-1% ~-10%, therefore the first output voltage V
oUT1v can be reached
nA=1.55 volts.In above-mentioned three kinds of situations, designer according to actual demand, can select not to reference resistance R
aDJadjust, and numeral is inputted S
iNbe set as wherein a kind of aspect of 2 position digital signals, such as S
iN[0:1]=00, its figure place is the resolution depending on compensation.
On the other hand, be R in difference percentage
n3% ~ R
n4the row of %, its reference resistance R
aDJfor the negative change of-11% ~-17%, now the first output voltage V
oUT1excursion V
nA~ V
nBbetween 1.57 ~ 1.68 volts.Therefore, comparing unit 120 compares the first output voltage V
oUT1with the first reference voltage V
rEF1, and the output valve S produced
dbetween Level
nA~ Level
nB.It is represented, then output valve S with the digital signal of 10
dbetween 493 ~ 527.Now numeral input S
iNwherein a kind of aspect of 2 position digital signals can be set as, such as S
iN[0:1]=01.
In addition, be R in difference percentage
p (X-1)% ~ R
pXthe row of %, its reference resistance R
aDJfor the just change of+11% ~+25%, now the first output voltage V
oUT1change can reach V
pX=1.26 volts.Therefore, output valve S
dat Level
pXbelow.It is represented, then output valve S with the digital signal of 10
dbe less than 396.Now numeral input S
iNwherein a kind of aspect of 2 position digital signals can be set as, such as S
iN[0:1]=11.Similarly, be-R in difference percentage
n (X-1)% ~-R
nXthe row of %, its reference resistance R
aDJfor the negative change of-18% ~-25%, its V
nX=1.86 volts, Level
nX=528, S
iN[0:1]=10.
In the present embodiment, designer based on the resolution compensated, can divide reference resistance R
aDJcompared to the scope of the difference percentage of standard resistance, to design applicable look-up table.Every numerical value illustrated in above-described embodiment only in order to implementation, and need not limit the present invention.In addition, although the look-up table of Fig. 7 only illustrates reference resistance R
aDJexemplary embodiment, but the mirror ratio of reference current source and current source array, the second reference voltage and compensating current element utilize the adjustment of look-up table when can by that analogy, just repeat no more at this.
Therefore, in the present embodiment, by the look-up table of Fig. 7, control unit receives output valve S
d, and firmware or software can be utilized accordingly to produce numeral input S in data value maps mode
iN, with correcting digital analog converter 110.
In sum, in exemplary embodiment of the present invention, the built-in reference resistance of digital analog converter, and use above-mentioned digital-to-analogue conversion method, it possesses self-calibrating mechanism, can avoid the impact of process variation, increases its yield.In addition, the digital-to-analogue conversion method of exemplary embodiment of the present invention effectively can improve gain error and the offset error of digital analog converter.
Although the present invention discloses as above with embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended right person of defining.
Claims (12)
1. a signal processing system, comprising:
One digital analog converter, receives a numeral and inputs and produce one first output voltage;
One comparing unit, receives this first output voltage and compares this first output voltage and one first reference voltage, to produce an output valve; And
One control unit, receives this output valve, and utilizes firmware or software to produce the input of this numeral in data value maps mode accordingly, to correct this digital analog converter,
Wherein this digital analog converter comprises a reference resistance, and this control unit selects according to this output valve the resistance increasing or reduce this reference resistance, to correct this digital analog converter.
2. signal processing system according to claim 1, wherein this digital analog converter comprises a reference current source and a current source array, this control unit selects according to this output valve the mirror ratio increasing or reduce this reference current source and this current source array, to correct this digital analog converter.
3. signal processing system according to claim 1, wherein this digital analog converter receives one second reference voltage, and this control unit is selected increase or reduce this second reference voltage, to correct this digital analog converter according to this output valve.
4. signal processing system according to claim 1, also comprises:
One test compensating unit, inputs a test signal to this digital analog converter, to make this digital analog converter produce one second output voltage, and judges whether this second output voltage mates with this test signal.
5. signal processing system according to claim 4, wherein this digital analog converter comprises a compensating current element, and for providing an offset current, this test compensating unit selects according to its judged result the size increasing or reduce this offset current.
6. signal processing system according to claim 1, wherein this control unit comprises a look-up table, when producing the input of this numeral in data value maps mode, this control unit finds out this numeral input corresponding to this output valve in this look-up table, to correct this digital analog converter.
7. a self-calibrating digital-to-analogue conversion method, for a digital analog converter, this self-calibrating digital-to-analogue conversion method comprises:
Receive a numeral input and produce one first output voltage;
Receive this first output voltage and compare this first output voltage and one first reference voltage, to produce an output valve; And
Receive this output valve, and utilize firmware or software to produce the input of this numeral in data value maps mode accordingly, to correct this digital analog converter,
Wherein this digital analog converter comprises a reference resistance, in this step correcting this digital analog converter, selects the resistance increasing or reduce this reference resistance, to correct this digital analog converter according to this output valve.
8. self-calibrating digital-to-analogue conversion method according to claim 7, wherein this digital analog converter comprises a reference current source and a current source array, in this step correcting this digital analog converter, the mirror ratio increasing or reduce this reference current source and this current source array is selected, to correct this digital analog converter according to this output valve.
9. self-calibrating digital-to-analogue conversion method according to claim 7, wherein this digital analog converter receives one second reference voltage, in this step correcting this digital analog converter, select increase or reduce this second reference voltage, to correct this digital analog converter according to this output valve.
10. self-calibrating digital-to-analogue conversion method according to claim 7, also comprises:
Input a test signal to this digital analog converter, produce one second output voltage to make this digital analog converter; And
Judge whether this second output voltage mates with this test signal.
11. self-calibrating digital-to-analogue conversion methods according to claim 10, wherein this digital analog converter comprises a compensating current element, and for providing an offset current, this self-calibrating digital-to-analogue conversion method also comprises:
The size increasing or reduce this offset current is selected according to this judged result.
12. self-calibrating digital-to-analogue conversion methods according to claim 7, this step wherein utilizing firmware or software to produce the input of this numeral in data value maps mode comprises:
This numeral input corresponding to this output valve is found out, to correct this digital analog converter in a look-up table.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110144370.9A CN102811058B (en) | 2011-05-31 | 2011-05-31 | Signal processing system and self-calibrating digital-to-analogue conversion method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110144370.9A CN102811058B (en) | 2011-05-31 | 2011-05-31 | Signal processing system and self-calibrating digital-to-analogue conversion method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102811058A CN102811058A (en) | 2012-12-05 |
| CN102811058B true CN102811058B (en) | 2015-11-04 |
Family
ID=47234655
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110144370.9A Expired - Fee Related CN102811058B (en) | 2011-05-31 | 2011-05-31 | Signal processing system and self-calibrating digital-to-analogue conversion method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102811058B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104065382B (en) * | 2013-03-22 | 2017-05-31 | 西安电子科技大学 | For the digital calibration circuit of segmented current steering DAC |
| CN108259804B (en) * | 2016-12-29 | 2021-06-29 | 扬智科技股份有限公司 | Video output system and related video signal compensation method thereof |
| US10382049B1 (en) * | 2018-09-06 | 2019-08-13 | Globalfoundaries Inc. | On-chip calibration circuit and method with half-step resolution |
| CN111049520B (en) * | 2018-10-11 | 2023-05-23 | 瑞昱半导体股份有限公司 | Digital-to-analog converter device and correction method |
| CN109379081B (en) * | 2018-10-29 | 2022-06-10 | 合肥本源量子计算科技有限责任公司 | Digital-analog converter and control method thereof |
| CN112217517A (en) * | 2020-10-09 | 2021-01-12 | 珠海零边界集成电路有限公司 | Method for adjusting digital-to-analog converter and related equipment |
| CN114326900A (en) * | 2021-12-29 | 2022-04-12 | 华中科技大学 | High-precision adjustable reference voltage generation circuit |
| CN114650055B (en) * | 2022-03-24 | 2023-05-09 | 深圳市晶扬电子有限公司 | Adaptive delta modulation analog-to-digital converter with calibration circuit and calibration method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278558A (en) * | 1992-07-21 | 1994-01-11 | Rockwell International Corporation | High accuracy digital to analog converter adjustment method and apparatus |
| CN101964660A (en) * | 2010-09-07 | 2011-02-02 | 株洲南车时代电气股份有限公司 | Self-correcting analog quantity output circuit |
-
2011
- 2011-05-31 CN CN201110144370.9A patent/CN102811058B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5278558A (en) * | 1992-07-21 | 1994-01-11 | Rockwell International Corporation | High accuracy digital to analog converter adjustment method and apparatus |
| CN101964660A (en) * | 2010-09-07 | 2011-02-02 | 株洲南车时代电气股份有限公司 | Self-correcting analog quantity output circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102811058A (en) | 2012-12-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102811058B (en) | Signal processing system and self-calibrating digital-to-analogue conversion method thereof | |
| US6674185B2 (en) | Temperature sensor circuit having trimming function | |
| CN102594348B (en) | Calibration circuit and method for calibrating capacitive compensation in digital-to-analog converters | |
| US8847677B2 (en) | Amplifier circuit | |
| US8476971B2 (en) | Buffer operational amplifier with self-offset compensator and embedded segmented DAC for improved linearity LCD driver | |
| TW201310897A (en) | Multi-input differential amplifier with dynamic transconductance compensation | |
| EP1906535B1 (en) | Differential offset correction circuit | |
| TWI442710B (en) | Signal processing unit and self-calibration digital-to-analog converting method thereof | |
| CN100565658C (en) | The color correcting method of the target GAMMA curve of target setting display device | |
| CN105210298A (en) | Multiple string digital to analog converter | |
| US7956903B2 (en) | Imaging apparatus | |
| WO2010137088A1 (en) | Interface circuit | |
| US10812094B2 (en) | Calibration method applied to digital-to-analog converter and associated circuit | |
| JP5550849B2 (en) | Resistance variation detection circuit, semiconductor device, and resistance variation detection method | |
| CN101546548A (en) | Composite lookup table method for synchronous correction of Gamma and chrominance of display | |
| CN111156893B (en) | Motor operation angle measuring method and system and joint angle measuring system | |
| CN100542041C (en) | Multi-bit digital-to-analog converter and calibration steps thereof have the transducer of multi-bit digital-to-analog converter | |
| CN103166643B (en) | For minimizing the method and system of converter voltage reference change | |
| CN101645707B (en) | Mistuning self-correctional high-speed data comparison latch | |
| WO2022165921A1 (en) | Digital-to-analog conversion apparatus and method | |
| CN114724513A (en) | AMOLED dimming brightness correction method and device | |
| US9774338B2 (en) | Digital-analog conversion method and device | |
| CN100530952C (en) | An amplifier gain control circuit of wireless transceiver | |
| CN104184476B (en) | Digital conveyer and the unmatched method for being used for compensating the digital conveyer | |
| JP4746792B2 (en) | A / D converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151104 Termination date: 20210531 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |