CN111049520B

CN111049520B - Digital-to-analog converter device and correction method

Info

Publication number: CN111049520B
Application number: CN201811184283.4A
Authority: CN
Inventors: 杨智杰; 黄诗雄; 雷良焕
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2018-10-11
Filing date: 2018-10-11
Publication date: 2023-05-23
Anticipated expiration: 2038-10-11
Also published as: CN111049520A

Abstract

The application discloses a digital-to-analog converter device and a correction method. The digital-to-analog converter device comprises digital-to-analog converter circuitry and correction circuitry. The digital-to-analog converter circuit system generates a first signal and a second signal according to an input signal. The correction circuitry compares the first signal with the second signal to generate a correction signal to correct the digital-to-analog converter circuitry according to the correction signal. The correction circuitry repeatedly compares the first signal with the second signal to generate a plurality of comparison results when determining at least one bit of the plurality of bits of the correction signal, and performs a statistical operation to adjust the at least one bit according to the comparison results, wherein the number of the at least one bit is smaller than the number of the plurality of bits.

Description

Digital-to-analog converter device and correction method

Technical Field

The present invention relates to a digital-to-analog converter device, and more particularly, to a current steering digital-to-analog converter using statistical operations.

Background

Digital-to-analog converters are common in a variety of electronic devices. In the related art, as the number of bits to be processed increases, the number of circuits to be used increases, and the operation time required for the circuits becomes significantly longer.

Disclosure of Invention

In order to solve the above-mentioned problems, some embodiments of the present application provide a digital-to-analog converter (DAC) device, which includes DAC circuitry and correction circuitry. DAC circuitry generates a first signal based on a plurality of least significant bits of the input signal and generates a second signal based on a plurality of most significant bits of the input signal. The correction circuitry compares the first signal with the second signal to generate a correction signal to correct the DAC circuitry according to the correction signal. The correction circuit system repeatedly compares the first signal and the second signal to generate a plurality of comparison results when determining at least one bit of the plurality of bits, and performs a statistical operation according to the plurality of comparison results to adjust the at least one bit, wherein the number of the at least one bit is smaller than the number of the plurality of bits.

Some embodiments of the present application provide a correction method comprising the following operations: generating a first signal according to a plurality of least significant bits of the input signal and a second signal according to a plurality of most significant bits of the input signal by DAC circuitry; comparing the first signal with the second signal to generate a correction signal to correct the DAC circuitry according to the correction signal; and repeatedly comparing the first signal with the second signal to generate a plurality of comparison results when at least one bit of the plurality of bits of the correction signal is determined, and performing a statistical operation according to the plurality of comparison results to adjust the at least one bit, wherein the number of the at least one bit is smaller than the number of the plurality of bits.

In summary, the DAC device and the correction method provided by the present application can utilize statistical operation to adjust part of bits. Therefore, the operation time of the correction process can be saved, and the accuracy of correction can be improved to improve the output resolution of the DAC device.

Drawings

FIG. 1 is a schematic diagram of a digital-to-analog converter (DAC) device according to some embodiments;

FIG. 2 is a schematic diagram illustrating the arrangement of current source circuits in the multiple DAC circuits of FIG. 1 according to some embodiments;

FIG. 3 is a flow chart of a calibration method according to some embodiments;

FIG. 4 is a schematic diagram illustrating an operation of FIG. 3 according to some embodiments;

FIG. 5 is a diagram illustrating performing majority operations according to some embodiments; and

FIG. 6 is a schematic diagram illustrating performing a weighting operation according to some embodiments.

Detailed Description

The term "circuitry" is used herein to refer broadly to a single system comprising one or more circuits (circuits). The term "circuit" generally refers to an article of manufacture that is connected in a manner to process signals by one or more transistors and/or one or more active and passive elements.

For ease of understanding, like elements in the various figures will be designated with the same reference numerals.

Fig. 1 is a schematic diagram of a digital-to-analog converter (DAC) device 100 according to some embodiments.

DAC device 100 includes multiplexer circuitry 110, DAC circuitry 120, and correction circuitry 130. The multiplexer circuitry 110 outputs one of the data signal DIN or the test signal DT as the input signal SIN according to the mode control signal CAL. For example, when the mode control signal CAL has a logic value of 0, the dac device 100 operates in the normal mode, and the multiplexer circuitry 110 outputs the data signal DIN as the input signal SIN. Alternatively, when the mode control signal CAL has a logic value of 1, the dac device 100 operates in the calibration mode, and the multiplexer circuitry 110 outputs the test signal DT as the input signal SIN.

DAC circuitry 120 is coupled to input circuitry 110 to receive an input signal SIN. DAC circuitry 120 includes a plurality of

DAC circuits

121 and 122 and resistors RO 1-RO 2. The DAC circuit 121 generates a signal AO1 from N least significant bits (least significant bit, LSB) in the input signal SIN. The DAC circuit 122 generates the signal AO2 according to M most significant bits (most significant bit, MSB) of the input signal SIN.

In some embodiments, DAC circuitry 120 may be implemented by a current-steering (DAC) circuit. The current steering DAC circuit may be implemented by a plurality of current source circuits, which may be activated according to the input signal SIN to output a corresponding current signal as the signal AO1 or AO2. The resistors RO1 to RO2 are coupled to the output terminals OP and ON of the

DAC circuits

121 and 122, respectively, to convert the sum of the signals AO1 and AO2 into the analog output SOUT in voltage form.

In some embodiments, DAC device 100 further includes a plurality of switches SW 1-SW 2. The switches SW1 and SW2 are coupled to the outputs of the DAC circuit 120 and the resistors RO 1-RO 2, respectively. When operating in the correction mode, the switches SW 1-SW 2 are turned off in response to a mode control signal CAL' that is complementary to the mode control signal CAL. Thus, in the calibration mode, the signals AO1 and AO2 can be correctly transmitted to the detection circuit 131. Alternatively, when operating in the normal mode, the switches SW1 to SW2 are turned on in response to the mode control signal CAL'. Thus, in the normal mode, the signals AO 1-AO 2 are transferred to the resistors RO 1-RO 2.

In some embodiments, the calibration circuitry 130 is coupled to the DAC circuitry 120 and calibrates the DAC circuitry 122 based on the signals AO1 and AO2 in the calibration mode. In some embodiments, the calibration circuitry 130 includes a detection circuit 131, a digital controller circuit 132, and a DAC circuit 133.

The detection circuit 131 is coupled to the outputs OP and ON of the DAC circuits 121-122 to receive the signals AO1 and AO2. In some embodiments, the detection circuit 131 is configured to compare the signal AO1 with the signal AO2 to generate the detection signal SD. The detection signal SD is used for indicating the comparison result of the signal AO1 and the signal AO2. In some embodiments, the detection circuit 131 may be implemented by a current comparator or a quantizer, but the present application is not limited thereto.

The digital controller circuit 132 is coupled to the multiplexer circuitry 110 and the detection circuit 131. In some embodiments, the digital controller circuit 132 is provided with a memory (not shown) for storing the predetermined test signal DT (and/or the predetermined time value TH mentioned later) to provide the test signal DT to the multiplexer circuitry 110 in the operation mode. In some embodiments, the digital controller circuit 132 further performs a correction operation in response to the detection signal SD to generate the correction signal S1.

For example, the digital controller circuit 132 may perform a successive approximation method according to the detection signal SD to determine a plurality of bits B1-BN of the correction signal S1. In some embodiments, when determining the last K bits of the correction signal S1, the digital controller circuit 132 further controls the detection circuit 131 to repeat the comparison signals AO1 and AO2 to generate a plurality of comparison results, and performs a statistical operation to adjust the K bits according to the comparison results. In some embodiments, K is a non-zero positive integer. In some embodiments, the number of the whole bits of the correction signal S1 is N, and K is smaller than N.

In some embodiments, the digital controller 132 may be implemented by digital signal processing circuitry, one or more logic circuits, and/or processing circuitry executing a finite state machine, but the disclosure is not limited thereto.

DAC circuit 133 is coupled to DAC circuit 122 and digital controller circuit 132. In some embodiments, the DAC circuit 133 outputs the compensation signal SP according to the correction signal S1 to correct the DAC circuit 122. For example, if the DAC circuit 122 is a current steering DAC implemented by a plurality of unit current sources, the compensation signal SP can be directly input to the DAC circuit 122 to correct the bias voltage of the corresponding unit current source. In this way, the signal AO2 output by the DAC circuit 122 can be equivalently corrected.

Alternatively, as shown in FIG. 1, in some embodiments DAC circuit 133 is directly coupled to the output of DAC circuit 122. In this setting mode, the DAC circuit 133 can turn ON the corresponding current source circuit according to the correction signal S1 to generate the corresponding current signal (i.e. the compensation signal SP) to the plurality of output terminals OP and ON of the DAC circuit 122. In this way, the compensation signal SP can be directly added to the signal AO2 to equivalently correct the offset of the DAC circuit 122.

Fig. 2 is a schematic diagram illustrating the arrangement of the current source circuits in the plurality of

DAC circuits

121, 122 and 133 in fig. 1 according to the arrangement in some embodiments.

In some embodiments,

DAC circuits

121, 122, and 133 may all be implemented as current steering DAC circuits. In this example, the plurality of current source circuits 121A are controlled by the plurality of bits L1 to L3 of the LSB, the plurality of current source circuits 122A are controlled by the plurality of bits M1 to M3 of the MSB, and the plurality of current source circuits 133A are controlled by the plurality of bits B1 to BN in the correction signal SP, respectively. In such embodiments, there is a correspondence between the plurality of current source circuits 121A in DAC circuit 121 and the plurality of current source circuits 122A in DAC circuit 122.

For example, if LSBs are encoded in binary code (binary code) and MSBs are encoded in thermal code (thermo code), the currents of the plurality of current source circuits 121A (hereinafter referred to as current ILSB) are sequentially different by 2 times. For example, as shown in fig. 2, the currents ILSB of the plurality of current source circuits 121A (e.g., the current sources 121A corresponding to the bits L1 to L3) are sequentially different by 2 times. As shown in fig. 2, the DAC circuit 133 includes a plurality of current source circuits 133A whose currents are sequentially 2 times different (e.g., 1/2I, 1/4I, 1/8I, 1/16I, etc.). In some embodiments, the resolution of DAC circuit 133 is higher than the resolution of DAC circuit 122.

Ideally, the sum of the plurality of currents ILSB should be equal to the current of the single current source circuit 122A (hereinafter referred to as current IMSB). That is, Σilsb=imsb (hereinafter, expression 1). However, due to process variations, the current IMSB will deviate, such that equation 1 cannot be established. In some embodiments, DAC circuit 121 further comprises an additional current source circuit 121B whose current is I and is controlled by bit L4, in which case, ideally, Σilsb=imsb.

Thus, when operating in the calibration mode, the digital controller circuit 132 may output the test signal DT with a particular bit value. In the initial test, the lower weight bits (e.g., bits L1-L4 of LSB) of the test signal DT are all 1, and one of the higher weight bits (e.g., bits M1-M3 of MSB) of the test signal DT is 1. Under this condition, all the current source circuits 121A are turned ON to output all the currents ILSB to an output terminal (e.g., ON) as the signal AO1. A corresponding current source circuit 122A is turned on to output a single current IMSB to another output terminal (e.g., the output terminal OP) as the signal AO2. By this arrangement, the detection circuit 131 can compare the signal AO1 and the signal AO2 to determine whether they satisfy the equation 1. If the equation 1 is not satisfied, the detection circuit 131 can output a corresponding detection signal SD.

Furthermore, the digital controller circuit 132 may perform a correction operation (e.g., binary search or successive approximation) to determine a plurality of bits B1-BN of the correction signal S1 in response to the detection signal SD. At least one current source circuit 133A is turned on according to the plurality of bits B1 to BN to output a corresponding current as the compensation signal SP. In some embodiments, the compensation signal SP may be directly summed with the signal AO2 to equivalently calibrate the DAC circuit 122 (shown in fig. 1). In other words, expression 1 can be modified to Σilsb=imsb+sp (hereinafter expression 2). Thus, by performing one or more operations in succession, the digital controller circuit 132 can determine the offset to be corrected by the single current source circuit 133A and record the corresponding correction signal S1 into the memory (not shown).

After recording the compensation signal SP corresponding to one current source circuit 122A, the digital controller circuit 132 may update the corresponding one of the MSBs of the test signal DT to 0 and the next corresponding one of the MSBs of the test signal DT to 1, and perform the above operation again. By analogy, the digital controller circuit 132 can record the correction signals S1 corresponding to all the current source circuits 122A by means of a lookup table. Thus, when the current source circuit 122A is activated, the digital controller circuit 132 can output the corresponding correction signal S1 to control the DAC circuit 133 to output the compensation signal SP to correct the DAC circuit 122.

For ease of understanding, the signals AO 1-AO 2 and the compensation signal SP in FIG. 1 are presented in a simplified manner. In practical applications, the signal AO1 may be a sum of a plurality of current (or voltage) signals (e.g., current ILSB) output by the DAC circuit 121, the signal AO2 may be a sum of a plurality of current (or voltage) signals (e.g., current IMSB) output by the DAC circuit 122, and the compensation signal SP may be a sum of a plurality of current signals output by the DAC circuit 133. Along with the different signal forms, the detection circuit 131 may also use different circuit configurations to determine whether the above equation 2 is satisfied. For example, when the signals are all current signals, the detection circuit 131 may be implemented by a current comparator and a switching circuit. The switching circuit can be used for switching the transmission paths of the current signals corresponding to the signals AO 1-AO 2, so that the current comparator can acquire enough information to judge whether the formula 2 is satisfied.

FIG. 3 is a flow chart of a calibration method 300 according to some embodiments. In some embodiments, the correction method 300 may be performed by the DAC device 100 of FIG. 1.

In operation S310, the digital controller circuit 132 performs a correction operation in response to the detection signal SD to determine a plurality of bits B1-BN of the correction signal S1.

Fig. 4 is a schematic diagram illustrating operation S310 in fig. 3 according to some embodiments. In this example, the digital controller circuit 132 performs a successive approximation method according to the detection signal SD to determine a plurality of bits B1-BN of the correction signal S1. During the successive approximation, the digital controller 132 enters a one-bit conversion stage. The bit transition stage includes a plurality of transition periods P1-PN. Each of the transition periods P1-PN is used to determine a corresponding bit. For example, bit BN is determined during the transition period PN.

For easy understanding, N is set to 4 in this example, but the present application is not limited thereto. During the transition period P1, the detection circuit 131 compares the signals AO1 (corresponding to Σilsb) and AO2 (corresponding to imsb+sp) for the 1 st time, and determines that Σilsb is smaller than imsb+sp. The detection circuit 131 generates a corresponding detection signal SD to indicate the comparison result. The digital controller circuit 132 determines the bit B1 of the correction signal S1 to be 0 in response to the detection signal SD. Then, during the transition period P2, the detection circuit 131 performs the 2 nd comparison on the signals AO1 and AO2, and determines that Σilsb is larger than imsb+sp. The digital controller circuit 132 determines the bit B2 of the correction signal S1 to be 1 in response to the comparison result. Similarly, bit B3 is determined to be 0 during transition period P3, and bit B4 is determined to be 1 during transition period P4.

With continued reference to fig. 3, in operation S320, the digital controller circuit 132 performs a statistical operation to adjust the reciprocal K bits of the correction signal S1 in response to the multiple comparison results represented by the detection signal SD.

In operation S330, the DAC circuit 133 generates the compensation signal SP in response to the correction signal S1 to correct the DAC circuit 122.

As previously described, K is less than N. For ease of understanding, the following paragraphs are illustrated with k=1, but the present application is not limited thereto. For the last 1 bit B4, the digital controller circuit 132 can control the detection circuit 131 to repeatedly compare the signal AO1 with the signal AO2 to generate the multi-detection signal SD. Based on the comparison results respectively represented by the detection signals SD, the digital controller circuit 132 can perform a statistical operation to adjust the last 1 bit B4. In some embodiments, the statistical operation may be a majority operation. Alternatively, in some embodiments, the statistical operation may be a weight operation.

FIG. 5 is a diagram illustrating performing multi-block operations according to some embodiments. As shown in fig. 5, in the transition period P4 of the decision bit B4, the detection circuit 131 compares the signals AO1 and AO 25 times to sequentially generate 5 detection signals SD. In response to the 5 detection signals SD, the digital controller circuit 132 sequentially sets the bit B4 determined by the correction operation to 1, 0. In this case, since the number of 1 s is large, the digital controller circuit 132 decides the bit B4 to be 1 according to the majority operation. Conversely, if the determined bit B4 is 0, 1, 0 in order. In this case, bit B4 will be determined to be 0 because the number of 0 s is relatively large.

FIG. 6 is a schematic diagram illustrating performing a weighting operation according to some embodiments. As shown in fig. 6, in the transition period P4 of the decision bit B4, the detection circuit 131 compares the signals AO1 and AO 25 times to sequentially generate 5 detection signals SD.

If the 5 detection signals SD are all 1, the digital controller circuit 132 encodes the bit B4 as 2. If there are 4 1 s and 1 s 0 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 1. If there are 31 s and 20 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 0.5. If there are 21 s and 30 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 0.25. If there are 1 and 4 0 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as 0. If there are 5 0 s in the 5 detection signals SD, the digital controller circuit 132 encodes the bit B4 as-1.

In this example, different codes correspond to different levels. In some embodiments, the DAC circuit 133 includes more current source circuits to generate different levels corresponding to different codes, for example, the DAC circuit 133 further includes a first current source circuit having a current of (1/16) I, and when the bit B4 is coded to 2, two current source circuits (the original current source circuit and the first current source circuit) having a current of (1/16) I are turned on simultaneously and connected to the same output terminal as the current source circuit 122A corresponding to the MSB; when bit B4 is encoded as-1, the first current source circuit will be on, but the current source circuit 122A corresponding to MSB is connected to a different output terminal; in another example, DAC circuit 133 also includes a current source circuit having a current of (1/32) I, which will be on when bit B4 is encoded to 0.5, and a current source circuit 122A corresponding to MSB is connected to the same output.

Compared to fig. 5, the bit B4 can be encoded as a digital code with multiple levels (multi-level) according to the multiple comparison results. In this manner, DAC circuit 133 may generate a more accurate compensation signal SP to calibrate DAC circuit 122.

In some related art, to improve the correction accuracy, N bits (e.g., B1-BN) of the correction signal are set to be determined by the average value of a plurality of sets of digital codes generated in a plurality of bit conversion stages. For example, if the correction signal has 4 bits, 1024 bits of conversion stages are required to obtain 1024 sets of digital codes (e.g., B1-B4) in the multiple techniques, and the 1024 sets of digital codes are averaged to determine the 4 bits of the correction signal. Thus, the whole correction process takes at least 1024×4 conversion cycles.

In contrast to the above technique, the digital controller circuit 132 repeats the comparison only when determining the last K bits of the correction signal. In this way, the time taken for the correction process can be reduced. In addition, since the analog signal corresponding to the last K bits (i.e. the input of the detection circuit 131) is relatively small, the comparison result of the detection circuit 131 is more susceptible to noise and error. By adjusting the last K bits according to the statistical operation of the multiple comparison results, the error probability of the detection circuit 131 can be effectively reduced, so as to improve the correction accuracy. In some embodiments, the higher the number of comparison operations performed by the detection circuit 131 in determining the transition period of the last K bits, the higher the accuracy of the correction. In some embodiments, the number of comparison operations performed by the detection circuit 131 may be preset according to actual requirements (calibration time, accuracy, etc.).

In some embodiments, the value of K may be preset. In other words, when the transition period of determining K bits is entered, the digital controller circuit 132 starts to execute operation S320.

Alternatively, in other embodiments, the digital controller circuit 132 may determine whether the operation S320 needs to be performed according to the transition time of the detection signal SD (i.e. the time of switching from logic 1 to logic 0 or the time of switching from logic 0 to logic 1). As described above, the analog signal (i.e., the input of the detection circuit 131) corresponding to the last K bits is relatively small, and the detection circuit 131 may require a long operation time to generate the detection signal SD. Equivalently, the transition time of the detection signal SD may be longer when determining the last K bits. In some embodiments, as shown in fig. 1, the digital controller circuit 132 can compare the transition time of the detection signal SD with a predetermined time value TH. In determining one of the bits B1-BN, if the transition time of the detection signal SD is longer than the predetermined time value TH, the digital controller circuit 132 may determine that a plurality of comparisons are needed to perform statistical operations to adjust the corresponding bit in the correction signal S1. In some embodiments, the predetermined time value TH may be set according to the transition time of the detection signal SD to the current ILSB (e.g. the current I), and may be adjusted according to practical applications.

In summary, the DAC device and the correction method provided by the present application can utilize statistical operation to adjust part of bits. Thus, the operation time of the correction process can be saved, and the accuracy of correction can be improved to improve the output resolution of the DAC device.

The above embodiments are for example, and various modifications and adaptations may be made without departing from the spirit and scope of the present application, the scope of which is defined in the appended claims.

Symbol description

100: digital-to-analog converter device

120: digital-to-analog converter circuitry

DT: test signal

SIN: input signal

AO1, AO2: signal signal

MSB: most significant bit

RO1, RO2: resistor

132: digital controller circuit

SD: detection signal

S1: correction signal

B1 to BN: bit position

TH: predetermined time value

133A: current source circuit

I: unit current

S310, S320, S330: operation of

L1 to L4: bit 110: multiplexer circuitry

130: correction circuit system

DIN: data signal

CAL, CAL': mode control signal

121 to 122: digital-to-analog converter circuit

133: digital-to-analog converter circuit

LSB: least significant bit

SOUT: analog output

OP, ON: an output terminal

131: detection circuit

SP: compensation signal

SW1, SW2: switch

121A, 122A: current source circuit

ILSB, IMSB: electric current

300: correction method

P1 to P4: during conversion

M1 to M3: bit position

Claims

1. A digital-to-analog converter device, comprising:

a digital-to-analog converter circuit system for generating a first signal according to a plurality of least significant bits of an input signal and generating a second signal according to a plurality of most significant bits of the input signal; and

a correction circuit system for comparing the first signal and the second signal to generate a correction signal for correcting the digital-to-analog converter circuit system according to the correction signal,

wherein the correction signal has a plurality of bits, the correction circuitry is further configured to repeatedly compare the first signal with the second signal to generate a plurality of comparison results when determining at least one of the plurality of bits, and perform a statistical operation to adjust the at least one bit according to the plurality of comparison results, and the number of the at least one bit is less than the number of the plurality of bits,

wherein the correction circuitry comprises:

a detection circuit for comparing the first signal with the second signal to generate a detection signal for indicating the comparison results;

a digital controller circuit for performing a correction operation according to the detection signal to generate the correction signal, wherein when determining the at least one bit, the digital controller circuit is further configured to perform the statistics operation according to the detection signal to adjust the at least one bit; and

a digital-to-analog converter circuit is used for generating a compensation signal according to the plurality of bits of the correction signal so as to correct the digital-to-analog converter circuit system.

2. The digital-to-analog converter device of claim 1, wherein the at least one bit is a last bit of the plurality of bits.

3. The digital-to-analog converter device of claim 1, wherein the at least one bit comprises a last K bits of the plurality of bits, K being a non-zero positive integer.

4. The digital-to-analog converter device of claim 1, wherein the statistical operation is a majority operation, and the digital controller circuit performs the majority operation according to the plurality of comparison results indicated by the detection signal to adjust the at least one bit.

5. The digital-to-analog converter device of claim 1, wherein the statistical operation is a weight operation, and the digital controller circuit performs the weight operation according to the plurality of comparison results indicated by the detection signal to adjust the at least one bit.

6. The digital-to-analog converter device of claim 5, wherein the at least one bit is encoded as a digital code having multiple levels.

7. The digital-to-analog converter device of claim 1, wherein the digital controller circuit is further configured to compare a transition time of the detection signal with a predetermined time value to determine whether to perform the statistical operation.

8. The digital-to-analog converter apparatus of claim 1, wherein the digital-to-analog converter circuitry comprises:

a first DAC circuit for generating the first signal according to the plurality of least significant bits; and

a second digital-to-analog converter circuit for generating the second signal according to the most significant bits,

wherein each of the first digital-to-analog converter circuit and the second digital-to-analog converter circuit is implemented by a current steering digital-to-analog converter circuit.

9. A correction method for use in a digital to analog converter circuit system, the correction method comprising:

generating a first signal according to a plurality of least significant bits of an input signal and generating a second signal according to a plurality of most significant bits of the input signal by the digital-to-analog converter circuitry;

comparing the first signal with the second signal to generate a detection signal, wherein the detection signal is used for indicating a comparison result;

performing a correction operation according to the detection signal to generate a correction signal, wherein the correction signal has a plurality of bits;

repeatedly comparing the first signal with the second signal to generate a plurality of comparison results when determining at least one bit of the plurality of bits of the correction signal, and performing a statistical operation to adjust the at least one bit according to the plurality of comparison results, wherein the number of the at least one bit is smaller than the number of the plurality of bits; and

the digital-to-analog converter circuit system is used for correcting the digital-to-analog converter circuit system by generating a compensation signal according to the plurality of bits of the correction signal.