CN115996058A - Successive approximation register type analog-digital converter and signal conversion method - Google Patents

Abstract

The disclosure relates to a successive approximation register analog-to-digital converter and a signal conversion method. The successive approximation register type analog-to-digital converter comprises a charge injection type digital-to-analog converter circuit, a comparator circuit and control logic circuit system. The charge injection type digital-to-analog converter circuit comprises a plurality of capacitors for sampling a plurality of input signals to generate a first signal and a second signal and a plurality of charge injection circuits for selectively adjusting the first signal or the second signal according to a plurality of enabling signals and a plurality of decision signals. The comparator circuit compares the first signal with the second signal to generate a decision signal. The control logic circuitry controls the circuitry in the plurality of charge injection circuits to adjust the first signal and the second signal during an initial period to adjust a switching sequence of the circuitry according to a decision signal corresponding to the initial period, and generates a plurality of enable signals during a transition period according to the decision signal and the adjusted switching sequence to generate a digital output.

Description

Successive approximation register type analog-digital converter and signal conversion method

Technical Field

The present invention relates to an analog-to-digital converter, and more particularly, to a successive approximation register analog-to-digital converter using a charge injection type digital-to-analog converter circuit and a signal conversion method.

Background

In the successive approximation register type analog-digital converter, the digital-analog converter circuit can be switched in sequence in the process of analog-digital conversion so as to finish the related operation of the successive approximation algorithm. In some techniques, the digital-to-analog converter circuit may be implemented by a current-mode digital-to-analog converter. However, in these techniques, in order to reduce the effect of mismatch between the plurality of current source circuits in the current-mode digital-to-analog converter, an additional digital-to-analog converter is used to calibrate (or compensate for) the current source circuits. To ensure the accuracy of the additional digital-to-analog converter, the additional digital-to-analog converter is implemented using a large circuit area. In this way, the overall circuit area and the device cost are significantly increased.

Disclosure of Invention

In some embodiments, the successive approximation register analog-to-digital converter includes a charge injection digital-to-analog converter circuit, a comparator circuit, and control logic circuitry. The charge injection type digital-to-analog converter circuit comprises a plurality of capacitors and a plurality of charge injection circuits. The capacitors are used for respectively sampling a plurality of input signals to generate a first signal and a second signal. The charge injection circuits are used for selectively adjusting at least one of the first signal or the second signal according to a plurality of enabling signals and a plurality of decision signals. The comparator circuit is used for comparing the first signal with the second signal to generate the decision signals. The control logic circuitry is configured to control a first one of the charge injection circuits to adjust the first signal and the second signal during an initial period, to adjust a switching sequence of the first charge injection circuit according to the decision signals corresponding to the initial period, and to generate the enable signals during an analog-to-digital conversion period according to the decision signals and the adjusted switching sequence, to generate a digital output.

In some embodiments, the signal conversion method comprises the following operations: sampling a plurality of input signals by a plurality of capacitors respectively to generate a first signal and a second signal; selectively adjusting at least one of the first signal or the second signal by a plurality of charge injection circuits according to a plurality of enable signals and a plurality of decision signals; comparing the first signal with the second signal to generate the decision signals; controlling a first charge injection circuit of the charge injection circuits to adjust the first signal and the second signal in an initial period, so as to adjust a switching sequence of the first charge injection circuit according to the decision signals corresponding to the initial period; and generating the enable signals according to the decision signals and the adjusted switching sequence during an analog-to-digital conversion period to generate a digital output.

The features, acts and effects of the present application are described in detail below with respect to preferred embodiments with reference to the accompanying drawings.

Drawings

FIG. 1 is a schematic diagram of a successive approximation register analog-to-digital converter according to some embodiments of the present application;

FIG. 2 is a schematic diagram depicting the charge injection circuit of FIG. 1, according to some embodiments of the present application;

FIG. 3A is a flowchart depicting a number of operations performed during an initial period by the control logic circuitry of FIG. 1, in accordance with some embodiments of the present application;

FIG. 3B is a conceptual diagram illustrating some of the operations of FIG. 3A according to some embodiments of the present application; and

fig. 4 is a flow chart of a signal conversion method according to some embodiments of the present application.

Detailed Description

All terms used herein have their ordinary meaning. The foregoing definitions of words and phrases are provided throughout this specification and in an exemplary embodiment, and are not intended to limit the scope and meaning of the present application. Likewise, the present application is not limited to the various embodiments shown in this specification.

As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or that two or more elements may operate or function with each other. As used herein, the term "circuitry" may be a single system formed of at least one circuit, and the term "circuit" may be a device connected in a manner by at least one transistor and/or at least one active and passive element to process signals.

As used herein, the term "and/or" includes any combination of one or more of the listed associated items. The terms first, second, third, etc. are used herein to describe and distinguish between various elements. Thus, a first element could also be termed a second element herein without departing from the spirit of the present application. For ease of understanding, like elements in the various figures will be designated with like reference numerals.

Fig. 1 is a schematic diagram of a successive approximation register (successive approximation register) analog-to-digital converter 100 according to some embodiments of the present application. The successive approximation register type adc 100 includes a switch SW1, a switch SW2, a comparator circuit 120, a charge injection type adc circuit 140 and a control logic circuit 160.

Based on the control of the control logic 160, the switches SW1 and SW2 are turned on during sampling to transmit the input signal VIP and the input signal VIN to the charge injection dac 140. Based on the control of the control logic 160, the switches SW1 and SW2 are not turned on during the successive approximation register ADC 100 is operated.

The charge injection type DAC 140 includes a capacitor C1, a capacitor C2, and a plurality of charge injection circuits 141[1] to 141[4]. When the successive approximation register type adc 100 operates in the sampling period, the capacitor C1 and the capacitor C2 can sample the input signal VIP and the input signal VIN respectively to generate the signal VP and the signal VN. When the register type ADC 100 is operated in the ADC period, the charge injection circuits 141[1] to 141[4] can selectively adjust the charge stored in at least one of the capacitor C1 or the capacitor C2 according to the enable signals EN1[1] to EN1[8], EN2[1] to EN2[4], EN3[1] to EN3[2] and EN4[1], the decision signal VOP and the decision signal VON, thereby adjusting the level of the signal VP and/or the level of the signal VN.

In this embodiment, the plurality of charge injection circuits 141[1] to 141[4] are configured to draw current from the capacitor C1 or the capacitor C2. For example, the charge injection circuit 141[1] can be enabled according to the enable signals EN1[1] to EN1[8], and can determine to draw current from the capacitor C1 or the capacitor C2 or not draw current from the capacitors C1 and C2 according to the decision signal VOP and the decision signal VON. The charge injection circuit 141[2] can be enabled according to the enable signals EN2[1] to EN2[4], and can be used for determining to draw current from the capacitor C1 or the capacitor C2 or not drawing current from the capacitor C1 and the capacitor C2 according to the decision signal VOP and the decision signal VON. The charge injection circuit 141[3] can be enabled according to the enable signals EN3[1] to EN3[2], and can be used for determining to draw current from the capacitor C1 or the capacitor C2 or not drawing current from the capacitor C1 and the capacitor C2 according to the decision signal VOP and the decision signal VON. The charge injection circuit 141[4] can be enabled according to the enable signals EN4[1], and can determine to draw current from the capacitor C1 or the capacitor C2 or not draw current from the capacitor C1 and the capacitor C2 according to the decision signal VOP and the decision signal VON. For easy understanding, the current values extracted by the charge injection circuits 141[1] to 141[4] can be sequentially set to 8I, 4I, 2I and 1I based on binary encoding, wherein I is a unit current, but the present application is not limited thereto. The arrangement of the plurality of charge injection circuits 141[1] to 141[4] will be described later with reference to FIG. 2.

In some embodiments, the control logic 160 may control the timing of the switch SW1, the switch SW2, the comparator circuit 120 and the charge injection type digital-to-analog converter circuit 140. The control logic 160 may control at least one of the plurality of charge injection circuits 141[1] to 141[4] (hereinafter referred to as the first charge injection circuit) to adjust the signal VP and the signal VN during the initial period, and the comparator 120 may compare the signal VP and the signal VN during the initial period to generate the decision signal VON and the decision signal VOP corresponding to the initial period. The control logic 160 may adjust a switching sequence of the first charge injection circuit according to the decision signal VON and the decision signal VOP corresponding to the initial period. In this way, the linearity of the first charge injection circuit can be improved, and the resolution of the digital output DOUT can be further improved. In some embodiments, the control logic 160 may adjust the switching sequence during the initial period based on the currents of the plurality of current source circuits (e.g., the plurality of current source circuits 203[1] to 203[8 ]) in the first charge injection circuit (FIG. 3A). The operation thereof will be described later with reference to fig. 3A and 3B.

In some embodiments, the initial period may be, but is not limited to, a predetermined period after the initial start-up of the analog-to-digital converter 100. In some embodiments, the first charge injection circuit may be a charge injection circuit (e.g., charge injection circuit 141[1 ]) corresponding to the most significant bit in the charge injection digital-to-analog converter circuit 140. In other embodiments, the first charge injection circuit may be all of the charge injection circuits (e.g., the charge injection circuits 141[1] to 141[3 ]) having multiple current source circuits in the charge injection DAC circuit 140.

During the analog-to-digital conversion, the comparator circuit 120 may compare the signal VP and the signal VN to generate the decision signal VON and the decision signal VOP. The control logic 160 generates the enable signals EN1[1] to EN1[8], EN2[1] to EN2[4], EN3[1] to EN3[2] and EN4[1] according to the decision signals VON and VOP and the adjusted switching sequence during the analog-to-digital conversion, and generates the digital output DOUT. For example, the control logic 160 may perform a successive approximation algorithm (e.g., without limitation, a binary search algorithm) according to the decision signal VON and the decision signal VOP corresponding to the analog-to-digital conversion period, and generate a plurality of enable signals EN1[1] to EN1[8], EN2[1] to EN2[4], EN3[1] to EN3[2] and EN4[1] according to the adjusted switching sequence.

In the above process, the control logic 160 may perform a successive approximation algorithm according to the decision signal VON and the decision signal VOP generated by each comparison to determine a bit of the digital output DOUT. In some embodiments, the control logic 160 may be implemented by one or more digital signal processing circuits that may be used to perform a successive approximation algorithm, control the timing of other circuits in the successive approximation register analog-to-digital converter 100, and correct the first charge injection circuit during the initial period (i.e., the operations of fig. 3A).

FIG. 2 is a schematic diagram depicting the charge injection circuit 141[1] of FIG. 1 according to some embodiments of the present application. In this example, the charge injection circuit 141[1] comprises a plurality of control circuits 201[1] to 201[8], a plurality of switching circuits 202[1] to 202[8], and a plurality of current source circuits 203[1] to 203[8]. For simplicity, the above circuits are omitted from the figures.

Each of the plurality of control circuits 201[1] to 201[8] generates one of the plurality of switching signals E1[1] to E1[8] according to a corresponding one of the plurality of enable signals EN1[1] to EN1[8], the decision signal VOP and the decision signal VON. In detail, the control circuit 201[1] generates the switching signal E1[1] according to the enable signal EN1[1], the decision signal VOP and the decision signal VON. The control circuit 201[2] generates the switching signal E1[2] according to the enable signal EN1[2], the decision signal VOP and the decision signal VON. And so on, the control circuit 201[8] generates the switching signal E1[8] according to the enable signal EN1[8], the decision signal VOP and the decision signal VON. In some embodiments, each of the plurality of control circuits 201[1] 201[8] may be implemented by a plurality of logic gates to generate a plurality of control bits for a corresponding one of the plurality of switching signals E1[1] E1[8].

Each of the plurality of switching circuits 202[1] to 202[8] is selectively connected to one of the capacitor C1 and the capacitor C2 or not connected to the capacitor C1 and the capacitor C2 according to a corresponding one of the plurality of switching signals E1[1] to E1[8]. For example, each of the plurality of switching circuits 202[1] to 202[8] may be implemented by a number of switches. The switches can be selectively turned on to connect to the capacitor C1 or the capacitor C2 according to a plurality of bits of a corresponding one of the switching signals E1[1] to E1[8], or can be turned off not to connect to the capacitor C1 or the capacitor C2 according to the bits. Each of the plurality of current source circuits 203[1] 203[8] can be connected to the capacitor C1 or the capacitor C2 via a corresponding one of the plurality of switching circuits 202[1] 202[8] to discharge the capacitor C1 or the capacitor C2 (i.e., draw current from the capacitor C1 or the capacitor C2). For example, the switching circuit 202[1] may be connected to the capacitor C1 according to the switching signal E1[1], and the current source circuit 203[1] may be connected to the capacitor C1 via the switching circuit 202[1] to discharge the capacitor C1. In this way, the level of the signal VP will become low. Alternatively, if a corresponding switching circuit (e.g., the switching circuit 202[1 ]) of the plurality of switching circuits 202[1] to 202[8] is not connected to the capacitor C1 and the capacitor C2, a corresponding one (e.g., the current source circuit 203[1 ]) of the current source circuits 203[1] to 203[8] cannot discharge the capacitor C1 or the capacitor C2 (i.e., does not draw current from the capacitor C1 and the capacitor C2) through the corresponding switching circuit. By analogy, the arrangement between the remaining switching circuits 202[2] to 202[8] and the remaining current source circuits 203[2] to 203[8] should be understood.

As previously described, the current drawn by the charge injection circuit 141[1] is 8I, in this example, the plurality of current source circuits 203[1] to 203[8] are arranged based on thermometer codes. In other words, the current drawn by each of the plurality of current source circuits 203[1] to 203[8] is a unit current I. When all the current source circuits 203[1] to 203[8] are enabled (i.e., the corresponding plurality of switching circuits 202[1] to 202[8] are all turned on to be connected to the capacitor C1 or the capacitor C2), the total current that the charge injection circuit 141[1] can draw from the capacitor C1 or the capacitor C2 is 8I.

The arrangement of the plurality of charge injection circuits 141[2] to 141[4] is similar to that of the charge injection circuit 141[1], and thus the description thereof will not be repeated here. It should be understood that the number of circuits in fig. 1 and 2 and the above-mentioned current values are only examples, and the present application is not limited thereto. According to different practical requirements, the number of circuits and/or the current value in fig. 1 and fig. 2 can be adjusted accordingly.

Fig. 3A is a flow chart depicting a number of operations performed by the control logic circuitry 160 of fig. 1 during an initial period in accordance with some embodiments of the present application. Fig. 3B is a conceptual diagram illustrating some of the operations of fig. 3A according to some embodiments of the present application. For easy understanding of the operation related to adjusting the switching sequence of the current injection circuit 141[1], please refer to fig. 3A and 3B together.

As shown in fig. 3B, a plurality of current source circuits 203[1]]～203[8]The current of (a) is I in sequence ₁ ～I ₈ . Ideally, a plurality of currents I ₁ ～I ₈ Each of which is a unit current I (i.e., a plurality of current source circuits 203[1]]～203[8]The weights of each of them are mutually equalAnd the control logic 160 switches the current source circuits 203[1] according to the digital code and a predetermined sequence]～203[8]To produce a corresponding analog output. The predetermined order may be in accordance with a plurality of current source circuits 203[1]]～203[8]The numbers of which enable a corresponding number of current source circuits in sequence. For example, if the digital code corresponds to a value of 1, the control logic 160 may enable the current source circuit 203[1]]To produce a corresponding analog output (i.e., unit current I). If the digital code corresponds to a value of 2, the control logic 160 may enable the current source circuit 203[1]]Current source circuit 203[2]]To produce a corresponding analog output (i.e., 2 times the unit current I). However, due to the effect of actual process variations, a plurality of current source circuits 203[1]]～203[8]There may be a mismatch between them such that there are multiple currents I ₁ ～I ₈ An offset occurs (i.e., a plurality of current source circuits 203[1]]～203[8]Error in the weights of (c). Under this condition, if the control logic circuitry 160 enables the plurality of current source circuits 203[1] in the predetermined order]～203[8]An analog output with poor linearity is produced. To improve linearity, the control logic 160 may perform the operations of FIG. 3A during initial operation to adjust the current source circuits 203[1]]～203[8]Is equivalent to correcting the switching sequence of the plurality of current source circuits 203[1]]～203[8]Weights between).

Referring to fig. 3A, in operation S310, a first current source circuit (e.g., current source circuit 203[4] of fig. 2) of the plurality of current source circuits is controlled to adjust a charge stored in a first capacitor (e.g., capacitor C1) of the plurality of capacitors during an initial period, so as to adjust a first signal (e.g., signal VP) output by the first capacitor. In operation S320, a second current source circuit (e.g., the current source circuit 203[1] of fig. 2) of the plurality of current source circuits is controlled in an initial period to adjust the charge stored in a second capacitor (e.g., the capacitor C2) of the plurality of capacitors, so as to adjust a second signal (e.g., the signal VN) output by the second capacitor.

For example, during the initial period, the capacitors C1 and C2 may be reset by a predetermined voltage (such as, but not limited to, a common mode voltage) to store a predetermined charge amount. If using current source circuit 203[4]]Is the current I of (2) ₄ As a reference value, control logic 160 may output enable signal EN1[4]To control the current source circuit 203[4]]Draw current I into capacitor C1 ₄ . Thus, the charge stored in the capacitor C1 becomes low to adjust the level of the signal VP. Similarly, during the initial period, control logic 160 may output enable signal EN1[1]]To control the current source circuit 203[1]]Drawing current I towards capacitor C2 ₁ . Thus, the amount of charge stored in the capacitor C2 becomes low to adjust the level of the signal VN.

With continued reference to fig. 3A, in operation S330, the first signal and the second signal are repeatedly compared to generate a plurality of decision signals (e.g., decision signal VON and decision signal VOP) corresponding to the initial period. In operation S340, a difference between the current value of the first current source circuit and the current value of the second current source circuit is confirmed according to a plurality of decision signals corresponding to the initial period.

In the previous example, if the signal VP is lower than the signal VN, the comparator circuit 120 outputs the decision signal VON with a first logic value (e.g. logic value 1) and the decision signal VOP with a second logic value (e.g. logic value 0). Under this condition, the amount of charge stored in the capacitor C1 is smaller than the amount of charge stored in the capacitor C2. In other words, compared with the current source circuit 203[1]]Current source circuit 203[4]]More charge can be extracted during the same period. Thus, control logic circuitry 160 may infer current source circuitry 203[4]]Is the current I of (2) ₄ Higher than the current source circuit 203[1]]Is the current I of (2) ₁ . Alternatively, if the signal VP is higher than the signal VN, the comparator circuit 120 outputs the decision signal VON with the second logic value (e.g. logic value 0) and the decision signal VOP with the first logic value (e.g. logic value 1). Under this condition, the charge amount stored in the capacitor C1 is greater than the charge amount stored in the capacitor C2. In other words, compared with the current source circuit 203[1]]Current source circuit 203[4]]Less charge can be extracted during the same period. Thus, control logic circuitry 160 may infer current source circuitry 203[4]]Is the current I of (2) ₄ Lower than the current source circuit 203[1]]Is the current I of (2) ₁ 。

Based on the above operation, the comparator circuit 120 may repeatedly compare the signals VP and VN to obtain a plurality of sets (e.g., but not limited to, 1000 sets) of decision signals VON and VOP. The comparator circuit 120 can record the decision signals VON and VOP to determine the current source circuit 203[4]]Is the current I of (2) ₄ The value of (1) and current source circuit 203[1]]Is the current I of (2) ₁ Is a difference between the values of (a).

With continued reference to fig. 3A, operations S310 to S340 are repeated in operation S350 to confirm the current value of each of the remaining current source circuits and the current value of the first current source circuit (e.g., current I ₄ A value of (c) are provided. For example, the control logic 160 can reset the capacitor C1 and the capacitor C2 again and control the current source 203[4]]Draw current I into capacitor C1 ₄ (As previously mentioned, assume a current I ₄ A reference value) and controls the current source circuit 203[2]]Drawing current I towards capacitor C2 ₂ . Then, the comparator circuit 120 can repeatedly compare the signals VP and VN to obtain a plurality of sets of decision signals VON and VOP. The comparator circuit 120 can record the decision signals VON and VOP to determine the current source circuit 203[4]]Is the current I of (2) ₄ And current source circuit 203[2]]Is the current I of (2) ₂ Differences between them. By analogy, the control logic 160 may obtain multiple sets of decision signals VOP and VON to determine multiple currents I ₁ ～I ₈ Is a difference between the values of (a).

For example, in current source circuit 203[4]]And current source circuit 203[1]]Of the 1000 comparison results of (1) 700 comparison results (e.g. the number of times the decision signal VON has a logic value of 1 and the decision signal VOP has a logic value of 0) indicate the current I ₄ Greater than current I ₁ . In the current source circuit 203[4]]And current source circuit 203[2]]Of the 1000 comparison results of (1), 800 comparison results (e.g. the number of times the decision signal VON has a logic value of 0 and the decision signal VOP has a logic value of 1) indicate the current I ₄ Less than current I ₂ . In the current source circuit 203[4]]And current source circuit 203[3]]Of the 1000 comparison results of (a) 990 comparison results (e.g. the number of times the decision signal VON has a logic value of 0 and the decision signal VOP has a logic value of 1) indicate the current I ₄ Less than current I ₃ . Based on the multiple sets of decision signals VOP and VON, the control logic 160 can determine the current I ₄ Is greater than the current I ₁ And current I ₃ Is greater than the current I ₂ And is greater than the current I ₄ Can be expressed as I ₃ ＞I ₂ ＞I ₄ ＞I ₁ . Similarly, as shown in FIG. 3B, the control logic 160 may provide a plurality of decision signals VOP and decision signals VON for a plurality of currents I ₁ ～I ₈ Is ordered by the value of (2).

The above embodiment of operation S350 is only described with multiple decisions, but the present application is not limited thereto. In other embodiments, the control logic 160 may perform a statistical operation based on the plurality of decision signals VOP and VON to determine the plurality of currents I ₁ ～I ₈ Is a difference between the values of (a). In addition, the numerical values mentioned in the above examples are examples, and the present application is not limited thereto.

With continued reference to fig. 3A, in operation S360, the currents of the current source circuits are gradually added up based on an ascending order to adjust the switching sequence of the current source circuits.

For example, as shown in FIG. 3B, the control logic 160 may switch the plurality of current source circuits 203[1] according to the increasing order of the digital codes]～203[8]. For example, in response to digital code D1, with minimum current I ₁ Current source circuit 203[1]]Is selected (i.e., enabled) to produce a corresponding analog output (i.e., current I ₁ ). In response to the digital code D2, the current source circuit 203[1]And has the highest current I ₃ Current source circuit 203[3]]Selected to produce a corresponding analog output (i.e., current I ₁ And current I ₃ Is added up). In response to the digital code D3, the current source circuit 203[1]Current source circuit 203[3]]With the next lowest current I ₈ Current source circuit 203[8]]Selected to produce a corresponding analog output (i.e., current I ₁ Current I ₃ Current I ₈ Is added up). In response to the digital code D4, the current source circuit 203[1]Current source circuit 203[3]]Current source circuit 203[8]]With the next highest current I ₂ Current source circuit 203[2]]Selected to produce a corresponding analog output (i.e., current I ₁ Current I ₃ Current I ₈ Current I ₂ Is added up). By analogy, the control logic 160 may gradually sum the current source circuits 203[1] according to the remaining digital codes D5-D8]～203[8]To adjust the switching sequence. In this way, a more linear (as shown by the dashed line in FIG. 3B) analog output can be produced.

In some embodiments, the control logic 160 further includes a register circuit (not shown) that records the correspondence between the enable signals EN1[1] to EN1[8] and the adjusted switching sequence. For example, after recording the correspondence, during the adc, if the control logic 160 determines a digital code D1 in the digital output DOUT in response to the decision signal VOP and the decision signal VON, the control logic 160 may output the enable signal EN1[1] with the corresponding logic value to enable the current source circuit 203[1]. Alternatively, if the control logic 160 determines the digital code in the digital output DOUT to be the digital code D2 in response to the decision signal VOP and the decision signal VON, the control logic 160 may output the enable signal EN1[1] and the enable signal EN1[3] with corresponding logic values so as to enable the current source circuit 203[1] and the current source circuit 203[3].

By doing so, the control logic 160 may calibrate the charge injection digital-to-analog converter circuit 140 without using additional digital-to-analog converters or current source circuits. In this way, the linearity of the charge injection type digital-to-analog converter circuit 140 can be improved without significantly increasing the circuit area.

Fig. 4 is a flow chart of a signal conversion method 400 according to some embodiments of the present application. In operation S410, a plurality of input signals (e.g., the input signal VIP and the input signal VIN) are sampled by a plurality of capacitors (e.g., the capacitor C1 and the capacitor C2) to generate a first signal and a second signal (e.g., the signal VP and the signal VN), respectively. In operation S420, at least one of the first signal or the second signal is selectively adjusted by a plurality of charge injection circuits (e.g., the charge injection circuits 141[1] to 141[4 ]) according to a plurality of enable signals and a plurality of decision signals. In operation S430, the first signal and the second signal are compared to generate the decision signals. In operation S440, a first charge injection circuit of the charge injection circuits is controlled to adjust the first signal and the second signal in an initial period, so as to adjust a switching sequence of the first charge injection circuit according to the decision signals corresponding to the initial period. In operation S450, the enable signals are generated during the adc according to the decision signals and the adjusted switching sequence to generate a digital output (e.g., digital output DOUT).

The above operations may be understood by referring to the above embodiments, and thus the description thereof will not be repeated here. The various operations of the signal conversion method 400 described above are merely examples and are not limited to being performed in the order illustrated in this example. The various operations under the signal conversion method 400 may be added, substituted, omitted, or performed in a different order (e.g., concurrently or with partial concurrence) as appropriate without departing from the manner and scope of operation of the various embodiments herein. For example, operation S440 may be performed during an initial period after the gradually-approximated register analog-to-digital converter 100 is turned on, and the plurality of operations S410, S420, S430, and S450 may be performed during the period during which the gradually-approximated register analog-to-digital converter 100 performs analog-to-digital conversion.

In summary, the successive approximation register analog-to-digital converter and the signal conversion method provided in some embodiments of the present application can reorder the switching sequence of the plurality of current source circuits in the charge injection circuit by using the initial period after the device is turned on. In this way, the influence of mismatch can be reduced without using an additional digital-to-analog converter to improve linearity.

Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application, and those skilled in the art may make various changes to the technical features of the present application according to the explicit or implicit disclosure of the present application, where the various changes may be within the scope of patent protection sought herein, in other words, the scope of patent protection of the present application should be defined by the claims of the present application.

[ symbolic description ]

100 gradually approaching register type A/D converter

120 comparator circuit

140 charge injection type digital-to-analog converter circuit

141[1] to 141[4] charge injection circuit

160 control logic circuitry

201[1] to 201[8]: control circuit

202[1] to 202[8]: switching circuit

203[1] to 203[8] are current source circuits

400 signal conversion method

C1, C2 capacitance

D1-D8 digital codes

DOUT digital output

E1[1] to E1[8] switching signals

EN1[1] to EN1[8], EN2[1] to EN2[4], EN3[1] to EN3[2], EN4[1] to enable signal

I: unit current

I ₁ ～I ₈ Current flow

S310, S320, S330, S340, S350, S360: operation

S410, S420, S430, S440, S450: operation

SW1, SW2 switch

VIN, VIP input signal

VN, VP: signal

VON, VOP: decision signal.

Claims (10)

1. A successive approximation register analog-to-digital converter comprising:

the charge injection type digital-analog converter circuit comprises a plurality of capacitors and a plurality of charge injection circuits, wherein the capacitors are used for respectively sampling a plurality of input signals to generate a first signal and a second signal, and the charge injection circuits are used for selectively adjusting at least one of the first signal and the second signal according to a plurality of enabling signals and a plurality of decision signals;

a comparator circuit for comparing the first signal and the second signal to generate the decision signals; and

the control logic circuitry is configured to control a first charge injection circuit of the plurality of charge injection circuits to adjust the first signal and the second signal during an initial period, to adjust a switching sequence of the first charge injection circuit according to the plurality of decision signals corresponding to the initial period, and to generate the plurality of enable signals during an analog-to-digital conversion according to the plurality of decision signals and the adjusted switching sequence to generate a digital output.

2. The successive approximation register analog-to-digital converter of claim 1, wherein the control logic circuitry is configured to adjust the switching sequence during the initial period based on currents of a plurality of current source circuits in the first charge injection circuit.

3. The successive approximation register adc of claim 1, wherein during the initial period, the control logic circuitry is configured to control a first current source circuit in the first charge injection circuit to adjust the first signal and a second current source circuit in the first charge injection circuit to adjust the second signal, the comparator circuitry is further configured to repeatedly compare the first signal with the second signal to generate the plurality of decision signals corresponding to the initial period, and the control logic circuitry is further configured to determine a difference between the current values of the first current source circuit and the second current source circuit according to the plurality of decision signals corresponding to the initial period to adjust the switching sequence.

4. The successive approximation register analog-to-digital converter of claim 1, wherein the first charge injection circuit comprises a plurality of current source circuits, and the control logic circuitry is configured to gradually sum currents of the plurality of current source circuits based on an increasing order to adjust the switching order.

5. The successive approximation register analog-to-digital converter of claim 1, wherein the control logic circuitry is further configured to record a correspondence between the plurality of enable signals and the adjusted switching sequence.

6. The successive approximation register analog-to-digital converter of claim 1, wherein the plurality of charge injection circuits are configured to selectively adjust the charge stored in at least one of the plurality of capacitors according to the plurality of enable signals and the plurality of decision signals to adjust at least one corresponding one of the first signal and the second signal.

7. The successive approximation register analog-to-digital converter of claim 1, wherein the first charge injection circuit comprises:

a plurality of control circuits, wherein each of the plurality of control circuits is configured to generate one of a plurality of switching signals according to a corresponding one of the plurality of enable signals and the plurality of decision signals;

a plurality of switching circuits, wherein each of the plurality of switching circuits is configured to selectively connect to one of the plurality of capacitors or not connect to the plurality of capacitors according to a corresponding one of the plurality of switching signals; and

a plurality of current source circuits, wherein each of the plurality of current source circuits is configured to discharge the one of the plurality of capacitors via a corresponding one of the plurality of switching circuits.

8. A signal conversion method, comprising:

sampling a plurality of input signals by a plurality of capacitors respectively to generate a first signal and a second signal;

selectively adjusting at least one of the first signal and the second signal by a plurality of charge injection circuits according to a plurality of enable signals and a plurality of decision signals;

comparing the first signal with the second signal to generate a plurality of decision signals;

controlling a first charge injection circuit of the plurality of charge injection circuits to adjust the first signal and the second signal in an initial period, so as to adjust a switching sequence of the first charge injection circuit according to the plurality of decision signals corresponding to the initial period; and

the plurality of enable signals are generated during an analog-to-digital conversion according to the plurality of decision signals and the adjusted switching sequence to generate a digital output.

9. The signal conversion method according to claim 8, wherein controlling the first charge injection circuit to adjust the first signal and the second signal during the initial period to adjust the switching sequence according to the plurality of decision signals corresponding to the initial period comprises:

the switching sequence is adjusted during the initial period based on currents of a plurality of current source circuits in the first charge injection circuit.

10. The signal conversion method according to claim 8, wherein controlling the first charge injection circuit to adjust the first signal and the second signal during the initial period to adjust the switching sequence according to the plurality of decision signals corresponding to the initial period comprises:

adjusting the first signal during the initial period by a first current source circuit in the first charge injection circuit;

adjusting the second signal during the initial period by a second current source circuit in the first charge injection circuit;

repeatedly comparing the first signal with the second signal to generate a plurality of decision signals corresponding to the initial period; and

the switching sequence is adjusted by confirming a difference between a current value of the first current source circuit and a current value of the second current source circuit according to the decision signals corresponding to the initial period.

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