CN110958021A - High-speed high-precision current rudder digital-to-analog converter self-calibration system and method - Google Patents
High-speed high-precision current rudder digital-to-analog converter self-calibration system and method Download PDFInfo
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Abstract
A high-speed high-precision current steering digital-to-analog converter self-calibration system and a method belong to the technical field of digital-to-analog converters. The invention comprises the following steps: the reference current source is connected to the positive input end of the current comparator, and the current source to be calibrated and the DAC module are connected to the negative input end of the current comparator for current comparison; the initial value of the calibration code is all 0, firstly, the highest bit of the calibration code is changed into 1, and whether the current calibration bit is 1 or not is determined according to the output result of the comparator; if the output result of the current comparator is high level 1, the current calibration bit is 1, otherwise, the current calibration bit is 0; then repeating the above processes from the second highest position to the lowest position in sequence until the K-bit calibration codes are all determined, and stopping comparison; latching the current calibration code in an error latch; the calibration DAC module generates calibration error compensation current under the control of the calibration code, and the current source calibration is completed; and the size of the total current obtained by adding the calibration error compensation current and the current of the current source to be calibrated is consistent with that of the current of the reference current source.
Description
Technical Field
The invention relates to a high-speed high-precision current steering digital-to-analog converter self-calibration method, and belongs to the technical field of digital-to-analog converters.
Background
The high-speed high-precision digital-to-analog converter is an important component of modern broadband communication, radar and other equipment, and the current-steering digital-to-analog converter is widely applied to a high-speed high-precision system due to the fact that the current-steering digital-to-analog converter has high working speed and can directly drive a resistive load. For a long time, due to the matching error limitation of the CMOS process, the current steering digital-to-analog converter realized only by intrinsic matching of the CMOS process can only achieve the precision of 10-12 bits generally. The static performance of the current steering digital-to-analog converter is mainly determined by the matching between current source tubes, the matching of a current source can be generally improved by increasing the sizes of the current source tubes, but the method is difficult to realize along with the improvement of the resolution of the digital-to-analog converter, because the resolution of the digital-to-analog converter is improved by 1 bit, the area of the current source tubes is increased in a geometric mode to meet the matching requirement, and the larger the area is, the higher the cost of a chip is.
With the increase of the conversion rate of the analog-to-digital converter, the dynamic performance of the current steering digital-to-analog converter is reduced along with the increase of the signal frequency and the clock frequency, and the dynamic performance of the current steering digital-to-analog converter can be improved by reducing the parasitic capacitance and resistance of the transistor and shortening the establishment time; however, to ensure the static performance of the current-steering dac, reducing the random mismatch and the system mismatch requires increasing the size of the transistor and the complex layout, which increases the parasitic capacitance and resistance of the transistor, which is in contrast to improving the dynamic performance of the current-steering dac.
In order to better solve the contradiction between the static performance and the dynamic performance improvement of the current steering analog-to-digital converter, a current source calibration technology is generally adopted, the requirement of matching on the area of a current source is reduced, and the improvement of the dynamic performance is not influenced; the current source calibration technology can effectively calibrate the current mismatch among all current sources, and ensures that the current steering analog-to-digital converter has high precision and high dynamic performance.
The digital-to-analog converter calibration technology can be divided into analog calibration and digital calibration according to the processing mode of a calibration control signal, and can be divided into foreground static calibration and background dynamic calibration according to whether a converter circuit works normally during calibration. The method is realized by continuous comparison and feedback in an analog domain, capacitor charging and discharging is generally adopted to maintain the grid source voltage of the current source tube, but the bias voltage of the current source tube needs to be continuously refreshed and adjusted due to the leakage phenomenon of the capacitor, and the calibration precision is not high. The digital background calibration technology can carry out calibration operation while a converter circuit works, and has the defects that a certain current source to be calibrated must be continuously replaced by a substitute current source, and the dynamic performance of a digital-to-analog converter is reduced due to the fact that switching current burrs are introduced when the substitute current source and the current source to be calibrated are continuously switched.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provides a high-speed high-precision self-calibration method for a current steering digital-to-analog converter. The self-calibration process does not need human interference, is in a completely automatic mode, can be completed by only once calibration, solves the problems of inaccurate analog calibration and repeated refreshing, solves the problem of reduced dynamic performance caused by digital background calibration, improves the calibration precision and the circuit performance, and can expand the calibration range and precision by adjusting the full-scale output current and the minimum weight current of the calibration DAC.
The technical solution of the invention is as follows: a high-speed high-precision current steering digital-to-analog converter self-calibration system comprises a reference current source, a current source to be calibrated, a current comparator, a calibration control logic module, an error latch and a calibration DAC module;
the reference current source provides reference current for comparison, and the output end of the reference current source is connected with the positive input end of the current comparator;
the output end of the current source to be calibrated is connected with the negative input end of the current comparator;
the current comparator is used for comparing the magnitude of the current input by the positive input end and the negative input end and outputting a comparison result to the input end of the calibration control logic module from the output end of the comparator;
the calibration control logic module is used for generating a calibration control signal by utilizing an internal state machine under the driving of the received calibration clock; the calibration control signal comprises a reference current source gating signal for controlling the on-off of a reference current source, a comparator enabling signal for controlling the on-off of a comparator, a current source gating signal to be calibrated for controlling the on-off of a current source to be calibrated, a calibration DAC module gating signal for controlling the on-off of a calibration DAC module and a calibration code for controlling the output current of the calibration DAC module;
the input end of the error latch is connected with the output end of the calibration control logic module, and the output end of the error latch is connected with the input end of the calibration DAC module, and is used for receiving and storing the calibration code and sending the calibration code to the calibration DAC module;
and the output end of the calibration DAC module is connected with the current comparator and is used for receiving the calibration code, generating comparison error current according to the calibration code and compensating the comparison error current to the current source to be calibrated.
Further, the reference current source includes a middle bit reference current source and a high bit reference current source, and the current comparator includes a middle bit comparator and a high bit comparator; the input ends of the middle-position reference current source and the high-position reference current source are connected with the output end of the calibration control logic module, and the output ends of the middle-position reference current source and the high-position reference current source are respectively connected with the positive input ends of the middle-position comparator and the high-position comparator; and the middle-position reference current source and the high-position reference current source respectively receive corresponding reference current source gating signals.
Further, the current source to be calibrated comprises a middle current source to be calibrated and a high current source to be calibrated; the input ends of the middle current source to be calibrated and the high current source to be calibrated are both connected with the output end of the calibration control logic module, the output end of the middle current source to be calibrated is connected with the negative input ends of the middle comparator and the high comparator, and the output end of the high current source to be calibrated is connected with the negative input end of the high comparator; and the middle current source to be calibrated and the high current source to be calibrated respectively receive corresponding gating signals of the current source to be calibrated.
Further, the calibration DAC module comprises a reference calibration DAC module for compensating the reference current source, and a middle position calibration DAC module and a high position calibration DAC module for compensating the middle position current source to be calibrated and the high position current source to be calibrated respectively; the input ends of the reference calibration DAC module, the middle calibration DAC module and the high calibration DAC module are connected with respective error latches; the output end of the reference calibration DAC module is connected with the positive input end of the middle-level comparator and the positive input end of the high-level comparator, the output ends of the middle-level calibration DAC module and the high-level calibration DAC module are respectively connected with the negative input ends of the middle-level comparator and the high-level comparator, and the calibration DAC module gating signals and the calibration codes are respectively received.
Further, a high-speed high-precision current steering digital-to-analog converter self-calibration method comprises the following steps:
and S1, carrying out middle current source calibration: the calibration control logic module sends enable ENP1 and enable SW1 signals, the enable ENP1 signal gates a median reference current source, the enable SW1 signal gates a matched calibration DAC module, and the current of the current median reference current source is I1<0>Current I1<0>The current weight is the same as that of the current source to be calibrated in the middle position; meanwhile, the calibration control logic module is used for referencing a median current sourceSetting the initial value of the calibration code of the matched calibration DAC module as INT<K:i>10 … 00, outputting the initial value compensation current IINTCurrent I1 of the current median reference current source<0>And the calibration initial value compensation current IINTGenerating a median reference current I1 by summing<0>+IINTThe current is used as a target for calibrating the self current of other middle current sources to be calibrated; i is a serial number;
s2, after the middle reference current setting is finished, the calibration control logic module sends enable S11<1>Signal gating a middle standby current source, transmit enable S33<1>The signal gates the matched middle position calibration DAC module, and simultaneously sends an enable SW3 signal to connect the middle position current source to be calibrated and the matched middle position calibration DAC module thereof to the negative input end of the middle position current comparator, and the middle position reference current I1<0>+IINTComparing the currents to generate a middle calibration code CAL1<K:i>(ii) a Calibrating the middle position code CAL1<K:i>Latching in a matched error latch, and forwarding to a corresponding middle position calibration DAC module, and controlling the middle position calibration DAC module to output a middle position calibration error compensation current I1A<1>(ii) a Output current I1 of median current source to be calibrated<1>Middle position calibration error compensation current I output by middle position calibration DAC module matched with middle position calibration current I1A<1>Generating an output current I1 by summing<1>+I1A<1>Completing the calibration of a middle-position current source to be calibrated;
s3, repeating S2 to finish the calibration of all the current sources to be calibrated in the middle position;
and S4, carrying out high-order current source calibration: calibration control logic module outputs enable S11 at the same time<M:1>Signal gating all the middle to-be-calibrated current sources, and enabling S33<M:1>Signal gating all the calibration DAC modules matched with the middle position current sources to be calibrated, and outputting an enabling SW4 signal to enable the output current I of all the calibrated middle position current sources1A<1>+I1<1>+I1A<2>+I1<2>+…+I1A<M>+I1<M>The negative input end of the high-order current comparator is accessed through addition; at the same time, the calibration control logic module sends an ENP2 enable signal and an SW2 enable signal, the ENP2 enable signal gates the high reference currentThe source, the enable SW2 signal gates the matched calibration DAC module thereof to be connected to the positive input end of the high-order current comparator for comparison, and the generated high-order reference compensation current is ISOutput current I2 of high-order reference current source<0>High-order reference compensation current I output by DAC module matched with the high-order reference compensation current ISGenerating a high level reference current I2 by summing<0>+ISThe current is used as a target for calibrating the self current of other high-order current sources to be calibrated;
s5, after the high-level reference current setting is completed, the calibration control logic module sends enable S22<1>The signal gates a high-order current source to be calibrated and sends an enable S44<1>The signal gates the matched calibration DAC module, and simultaneously sends an enable SW5 signal to connect the high-order current source to be calibrated and the matched calibration DAC module thereof into the negative input end of the high-order comparator, and the high-order current source to be calibrated and the matched calibration DAC module thereof are compared with the high-order reference current to generate a high-order calibration code CAL2<K:i>(ii) a Calibrating the high-order calibration code CAL2<K:i>Latched in a matched error latch, and forwarded to the corresponding high-order calibration DAC module to control the high-order calibration DAC module to output high-order calibration error compensation current I2A<1>(ii) a Output current I2 of high-order current source to be calibrated<1>High-order calibration error compensation current I output by DAC module matched with the high-order calibration error compensation current I2A<1>Generating an output current I2 by summing<1>+I2A<1>Completing the calibration of a high-order current source to be calibrated;
and S6, repeating S5, and completing the calibration of all the high-order current sources to be calibrated.
Further, the method for comparing the current with the reference current of the middle position or the high position comprises the following steps: a successive approximation method.
Compared with the prior art, the invention has the beneficial effects that:
(1) the digital self-calibration method of the high-speed high-precision current steering digital-to-analog converter is different from a permanent fixed and irreversible manual fuse trimming calibration mode, can automatically complete calibration according to different application environments, and has the advantages of simple and flexible calibration process and strong environmental adaptability.
(2) Compared with the analog calibration mode of correcting the grid source bias voltage of the current source tube, the digital self-calibration method of the high-speed high-precision current rudder digital-to-analog converter has high calibration precision, and can be completed by one-time calibration without repeated refreshing calibration.
(3) According to the digital self-calibration method of the high-speed high-precision current steering digital-to-analog converter, each current source to be calibrated is matched with one calibration DAC module and one error latch, and compared with a calibration mode with only one calibration DAC module, the digital self-calibration method of the high-speed high-precision current steering digital-to-analog converter is simple in calibration error information storage address decoding, small in digital logic scale and high in calibration speed.
(4) The digital self-calibration method of the high-speed high-precision current steering digital-to-analog converter can expand the precision and range of calibration by changing the digit of the calibration DAC module and the full-scale output current.
Drawings
FIG. 1 is a schematic diagram of the operation of the digital self-calibration system of the present invention;
FIG. 2 is a schematic diagram of a digital self-calibration system circuit configuration according to the present invention;
FIG. 3 is a schematic diagram of a high-level reference current source and a current source array to be calibrated according to the present invention;
FIG. 4 is a schematic diagram of the structure of the DAC calibration module according to the present invention, which is exemplified by a 6-bit 2+4 segmented structure.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and specific examples.
A modern high-speed high-precision digital-to-analog converter usually adopts an A + B + C segmented current rudder structure, wherein a high-A bit and a middle-B bit are decoded by thermometers and respectively control a unit current source, and a low-C bit is decoded by a binary system and controls a binary system weighted current source; thermometer coded high A bit to 2A-1 bit, control 2A-1 current weight of (2)B+C)I0The middle B bit thermometer coded to 2B-1 bit, control 2B-1 current weight of (2)C)I0The low C bit adopts binary decoding to control a binary weighted current source, and the total current weight is (2)C-1)I0The low C-bit current is split from a mid-bit current source by binary weighting, I0Is the most importantThe small weight current, called the digital to analog converter 1LSB current.
A high-speed high-precision current steering digital-to-analog converter self-calibration system comprises a reference current source, a current source to be calibrated, a current comparator, a calibration control logic module, an error latch and a calibration DAC module, and is respectively a working schematic diagram and a circuit structure schematic diagram of the digital self-calibration system as shown in figures 1 and 2.
The reference current source provides a reference current for comparison, all current sources to be calibrated are compared with, and the output end of the reference current source is connected with the positive input end of the current comparator. The reference current source comprises a middle bit reference current source and a high bit reference current source, and the current comparator comprises a middle bit comparator and a high bit comparator; the input ends of the middle-position reference current source and the high-position reference current source are connected with the output end of the calibration control logic module, and the output ends of the middle-position reference current source and the high-position reference current source are respectively connected with the positive input ends of the middle-position comparator and the high-position comparator; and the middle-position reference current source and the high-position reference current source respectively receive corresponding reference current source gating signals.
The current source to be calibrated is a current source to be calibrated, all middle-order current sources and high-order current sources of the current steering digital-to-analog converter in the self-calibration method need to be calibrated, and N is 2 in totalA-1 high-side current sources, M2BThe middle current source, as shown in fig. 3, is a schematic diagram of the structures of the middle and high reference current sources and the current source to be calibrated. The output end of the current comparator is connected with the negative input end of the current comparator. The current source to be calibrated comprises a middle current source to be calibrated and a high current source to be calibrated; the input ends of the middle current source to be calibrated and the high current source to be calibrated are both connected with the output end of the calibration control logic module, the output end of the middle current source to be calibrated is connected with the negative input ends of the middle comparator and the high comparator, and the output end of the high current source to be calibrated is connected with the negative input end of the high comparator; and the middle current source to be calibrated and the high current source to be calibrated respectively receive corresponding gating signals of the current source to be calibrated.
The current comparator is used for comparing the current input by the positive input end and the negative input end, and outputting a comparison result from the output end of the comparator to the input end of the calibration control logic module. The current comparator comprises a middle-position current comparator and a high-position current comparator; if the input current of the positive input end is larger than the input current of the negative input end, the current comparator outputs a high level 1, and if the input current of the positive input end is smaller than the input current of the negative input end, the current comparator outputs a low level 0.
The calibration control logic module is used for generating a calibration control signal by utilizing an internal state machine under the driving of the received calibration clock; the calibration control signal comprises a reference current source gating signal for controlling the on-off of a reference current source, a comparator enabling signal for controlling the on-off of a comparator, a current source gating signal to be calibrated for controlling the on-off of a current source to be calibrated, a calibration DAC module gating signal for controlling the on-off of a calibration DAC module and a calibration code for controlling the output current of the calibration DAC module. The calibration control signals comprise reference current source gating signals ENP1 and ENP2, a comparator enabling signal ENP3, current source gating signals S11< M:1>, S22< N:1>, calibration DAC gating signals S33< M:1>, S44< N:1>, SW1, SW2, SW3, SW4 and SW5 to be calibrated, calibration codes CAL < K:1> and INT < K:1 >.
The input end of the error latch is connected with the output end of the calibration control logic module, and the output end of the error latch is connected with the input end of the calibration DAC module, and the error latch is used for receiving and storing the calibration code and sending the calibration code to the calibration DAC module. The error latch is a K-bit register and can be implemented by simple latch, and each calibration DAC is matched with an error latch.
And the output end of the calibration DAC is connected with the current comparator and is used for receiving the calibration code, generating a comparison error current according to the calibration code and compensating the comparison error current to the current source to be calibrated. The calibration DAC module comprises a reference calibration DAC module for compensating a reference current source, and a middle position calibration DAC module and a high position calibration DAC module which are respectively used for compensating a middle position current source to be calibrated and a high position current source to be calibrated; the input ends of the reference calibration DAC module, the middle calibration DAC module and the high calibration DAC module are connected with respective error latches; the output end of the reference calibration DAC module is connected with the positive input ends of the middle-level comparator and the high-level comparator, and the middle-level calibration DAC moduleAnd the output end of the high-order calibration DAC module is respectively connected with the negative input ends of the middle-order comparator and the high-order comparator, and respectively receives the gating signal and the calibration code of the calibration DAC module. Each reference current source and the current source to be calibrated are matched with a calibration DAC. The calibration DAC is structurally a K-bit current steering DAC, and a calibration code CAL<K:1>Determining the output current of the DAC, and calibrating the DAC to adopt an i + j segmented current steering structure, wherein i + j is equal to K; in general, to ensure the accuracy of the calibration, the minimum weight current of the calibration DAC is less than 1/3 of the minimum weight current of the main DAC, and in this method, the minimum weight current of the calibration DAC is set to 1/4, i.e. I, of the minimum weight current of the main DAC1＝I0/4. Fig. 4 is a schematic diagram of a structure of a calibration DAC module according to the present invention, which takes a 6-bit 2+4 segmented current steering structure as an example.
The self-calibration method of the high-speed high-precision current steering digital-to-analog converter adopts a one-way calibration mode, namely, the current of a current source to be calibrated is set to be smaller than the current of a reference current source, the current of the current source to be calibrated is compensated by a calibration DAC, the current value of the current source to be calibrated approaches the current value of the reference current source by adopting a successive approximation comparison mode until the current value is approximately equal, and the calibration is finished; the current of the reference current source is the target of DAC current source calibration, and when the DAC current source is designed, the current of the reference current source is set to be larger than the current of the current source to be calibrated, and the set value is usually half of the total output current of the DAC to be calibrated. The self-calibration specific implementation method of the high-speed high-precision current steering digital-to-analog converter is as follows:
and S1, carrying out middle current source calibration: the calibration control logic module sends enable ENP1 and enable SW1 signals, the enable ENP1 signal gates a median reference current source, the enable SW1 signal gates a matched calibration DAC module, and the current of the current median reference current source is I1<0>Current I1<0>The current weight is the same as that of the current source to be calibrated in the middle position; meanwhile, the calibration control logic module sets the initial value of the calibration code of the calibration DAC module matched with the middle-position reference current source to INT<K:i>10 … 00, outputting the initial value compensation current IINTCurrent I1 of the current median reference current source<0>And the calibration initial value compensation current IINTGenerating a median reference by summingCurrent I1<0>+IINTThe current is used as a target for calibrating the self current of other middle current sources to be calibrated;
s2, after the middle reference current setting is finished, the calibration control logic module sends enable S11<1>Signal gating a middle standby current source, transmit enable S33<1>The signal gates the matched middle position calibration DAC module, and simultaneously sends an enable SW3 signal to connect the middle position current source to be calibrated and the matched middle position calibration DAC module thereof into the negative input end of the middle position current comparator, and the negative input end of the middle position reference current I1<0>+IINTComparing the currents to generate a middle calibration code CAL1<K:i>(ii) a Calibrating the middle position code CAL1<K:i>Latching in a matched error latch, and forwarding to a corresponding middle position calibration DAC module, and controlling the middle position calibration DAC module to output a middle position calibration error compensation current I1A<1>(ii) a Output current I1 of median current source to be calibrated<1>Middle position calibration error compensation current I output by middle position calibration DAC module matched with middle position calibration current I1A<1>Generating an output current I1 by summing<1>+I1A<1>Completing the calibration of a middle-position current source to be calibrated;
s3, repeating S2 to finish the calibration of all the current sources to be calibrated in the middle position;
and S4, carrying out high-order current source calibration: calibration control logic module outputs enable S11 at the same time<M:1>Signal gating all the middle to-be-calibrated current sources, and enabling S33<M:1>Signal gating all the calibration DAC modules matched with the middle position current sources to be calibrated, and outputting an enabling SW4 signal to enable the output current I of all the calibrated middle position current sources1A<1>+I1<1>+I1A<2>+I1<2>+…+I1A<M>+I1<M>The negative input end of the high-order current comparator is accessed through addition; meanwhile, the calibration control logic module sends an enable ENP2 signal and an enable SW2 signal, the enable ENP2 signal gates the high-order reference current source, the enable SW2 signal gates a matched calibration DAC module thereof to be connected to the positive input end of the high-order current comparator for comparison, and the generated high-order reference compensation current is ISOutput current I2 of high-order reference current source<0>High-order reference matched with high-order reference for calibrating DAC module outputCompensating current ISGenerating a high level reference current I2 by summing<0>+ISFinishing the setting of the high-level reference current;
s5, after the high-level reference current setting is completed, the calibration control logic module sends enable S22<1>The signal gates a high-order current source to be calibrated and sends an enable S44<1>The signal gates the matched calibration DAC module, and simultaneously sends an enable SW5 signal to connect the high-order current source to be calibrated and the matched calibration DAC module thereof into the negative input end of the high-order comparator, and the high-order current source to be calibrated and the matched calibration DAC module thereof are compared with the high-order reference current to generate a high-order calibration code CAL2<K:i>(ii) a Calibrating the high-order calibration code CAL2<K:i>Latched in a matched error latch, and forwarded to the corresponding high-order calibration DAC module to control the high-order calibration DAC module to output high-order calibration error compensation current I2A<1>(ii) a Output current I2 of high-order current source to be calibrated<1>High-order calibration error compensation current I output by DAC module matched with the high-order calibration error compensation current I2A<1>Generating an output current I2 by summing<1>+I2A<1>Completing the calibration of a high-order current source to be calibrated;
and S6, repeating S5, and completing the calibration of all the high-order current sources to be calibrated.
A high-speed high-precision current steering digital-to-analog converter self-calibration method is characterized in that a successive approximation method is adopted for current comparison, and a calibration code changes from a high bit to a low bit one by one, so that the output current of a calibration DAC is changed; the initial value of the calibration code is all 0, the highest bit of the calibration code is changed into 1 when the calibration is started, whether the current calibration bit is 1 or not is determined according to the output result of the current comparator, if the output result of the current comparator is high level 1, the current calibration bit is 1, and if not, the current calibration bit is 0; and repeating the processes from the second highest bit to the lowest bit in sequence until the K-bit calibration codes are all determined, and stopping comparison.
The above description is only for the best mode of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention.
Those skilled in the art will appreciate that those matters not described in detail in the present specification are well known in the art.
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| CN112886964A (en) * | 2021-01-12 | 2021-06-01 | 中国电子科技集团公司第五十八研究所 | Digital foreground calibration circuit and method applied to high-speed high-precision current steering DAC |
| CN113867463A (en) * | 2021-10-08 | 2021-12-31 | 深圳市乾鸿微电子有限公司 | One-time trimming and calibrating structure of current source |
| CN114019415A (en) * | 2022-01-06 | 2022-02-08 | 宜矽源半导体南京有限公司 | Integrated short-circuit current detector with variable threshold, self-calibration and high precision |
| CN114095021A (en) * | 2021-11-24 | 2022-02-25 | 北京博瑞微电子科技有限公司 | A method and circuit for calibrating resistance mismatch of a resistance digital-to-analog converter |
| CN114326900A (en) * | 2021-12-29 | 2022-04-12 | 华中科技大学 | A high-precision adjustable reference voltage generating circuit |
| CN114337664A (en) * | 2022-03-09 | 2022-04-12 | 华南理工大学 | A current rudder digital-to-analog converter with multi-level calibration |
| CN118054792A (en) * | 2024-03-22 | 2024-05-17 | 深圳大学 | Current rudder data conversion circuit and synthetic aperture radar single-bit system |
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| CN114019415A (en) * | 2022-01-06 | 2022-02-08 | 宜矽源半导体南京有限公司 | Integrated short-circuit current detector with variable threshold, self-calibration and high precision |
| CN114337664A (en) * | 2022-03-09 | 2022-04-12 | 华南理工大学 | A current rudder digital-to-analog converter with multi-level calibration |
| CN114337664B (en) * | 2022-03-09 | 2022-06-03 | 华南理工大学 | A current rudder digital-to-analog converter with multi-level calibration |
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