WO2020020092A1

WO2020020092A1 - Digital to analog converter

Info

Publication number: WO2020020092A1
Application number: PCT/CN2019/097020
Authority: WO
Inventors: 刘菁
Original assignee: 圣邦微电子（北京）股份有限公司
Priority date: 2018-07-24
Filing date: 2019-07-22
Publication date: 2020-01-30
Also published as: CN110752847A

Abstract

A digital to analog converter (300) comprises: a first resistor string (310), comprising multiple first resistors connected between a reference voltage and a reference ground; a second resistor string (340), comprising multiple second resistors connected between a first input end (26) and a second input end (28); a first switch network (320), for selecting at least one first resistor from the first resistor string (310) according to a first valid bit of an input digital signal; and a second switch network (350), for selecting at least one second resistor from the second resistor string (340) according to a second valid bit of the input digital signal. The digital to analog converter (300) also comprises a third switch network (330) that provides a current path from the first switch network (320) to the second resistor string (340). When switching is performed on the first resistor string (310), voltages across the resistors of the second resistor string (340) change uniformly, and the degree of matching is greatly improved, thereby eliminating the case in which an output analog signal difference between adjacent codes has a strong correlation with an absolute code, affecting the accuracy of digital to analog conversion.

Description

D / A converter

This application claims priority from a Chinese patent application filed on July 24, 2018 with an application number of 201810820578.X and an invention name of "digital-to-analog converter", the entire contents of which are incorporated herein by reference.

Technical field

The invention relates to the field of integrated circuit manufacturing, and more particularly to a digital-to-analog converter.

Background technique

With the rapid development of computer technology, multimedia technology, and signal processing technology, advanced electronic systems continue to emerge. Both front-end and back-end of modern electronic systems will be applied to digital-to-analog converters (DACs).

Digital-to-analog converters are used to convert digital signals into analog signals. In integrated circuit design, resistive digital-to-analog converters are a more common type. FIG. 1 shows a schematic structural diagram of a resistive digital-to-analog converter. As shown in FIG. 1, a conventional resistive digital-to-analog converter 100 connects resistors R1 to R64 having the same resistance value in series with each other, and access reference Between the voltage Vref and the reference ground, the switches S0-S64 connected in parallel are connected to the connection node between the resistors. Multiple switches S0-S64 are controlled by the decoded digital signal, and the voltage of each node between the resistors is selected to be output as the ground. An analog voltage corresponding to a digital signal. For a digital-to-analog converter with a conventional structure, when the accuracy N = 10 bits or more, 2 ^N switches are needed, the circuit will occupy a larger area, and the stray capacitance of the switch will also limit the speed of the digital-to-analog conversion.

Summary of the Invention

In view of this, an object of the present invention is to provide a digital-to-analog converter, which has higher efficiency and accuracy.

According to the present invention, a digital-to-analog converter is provided, including: a first resistor string including a plurality of first resistors connected between a reference voltage and a reference ground; and a second resistor string including a first input terminal and a second resistor. A plurality of second resistors between the input terminals; a first switch network for selecting at least one first resistor in the first resistor string according to a first significant bit of the input digital signal; a second switch network for At least one second resistor is selected in the second resistor string according to the second significant bit of the input digital signal, wherein the digital-to-analog converter further includes a third switch network for A current path from a first switching network to the second resistor string.

Preferably, both ends of the first resistor include a first terminal, and both ends of the second resistor include a second terminal.

Preferably, adjacent first resistors in the first resistance string share the first terminal, and adjacent second resistors in the second resistance string share the second terminal.

Preferably, the first switch network includes a plurality of first switches, a first path end of the plurality of first switches is correspondingly connected to the first terminal, and a second path end is connected to an output of the first switch network. The second switch network includes a plurality of second switches, a first path end of the second switch is correspondingly connected to the second terminal, and a second path end is connected to an output end of the second switch network The output terminal of the second switch network is used to output an analog signal corresponding to the digital signal.

Preferably, the first switch network includes a first output terminal and a second output terminal, wherein a second path terminal of an even number of the first switches is connected to the first output terminal, and an odd number of the first A second path end of a switch is connected to the second output end.

Preferably, the first switch network includes a first output end and a second output end, wherein the second path end of the odd number of the first switches is connected to the first output end, and the even number of the first A second path end of a switch is connected to the second output end.

Preferably, the third switch network includes a first switch circuit and a second switch circuit, and the first switch circuit and the second switch circuit each include a third switch and a fourth switch, wherein the first switch A first path end of the third switch in the circuit is connected to the first output end, a second path end is connected to the first input end, and a first path end of the fourth switch is connected to the first The output end is connected, the second path end is connected to the second input end, the first path end of the third switch in the second switch circuit is connected to the second output end, and the second path end is connected to the second output end. The second input terminal is connected, the first path terminal of the fourth switch is connected to the second output terminal, and the second path terminal is connected to the first input terminal.

Preferably, the digital-to-analog converter further includes: a first decoding circuit, configured to obtain a first control signal according to the first significant bit of the digital signal, and the first control signal is used to control the plurality of A closed / open state of a first switch; a second decoding circuit, configured to obtain a second control signal according to the second significant bit of the digital signal, and the second control signal is used to control the plurality of second On / off state of the switch.

Preferably, the first control signal and the second control signal are independent of each other.

Preferably, the first significant bit is the most significant bit, and the second significant bit is the least significant bit.

In summary, the digital-to-analog converter of the present invention includes a third switching network for coupling both ends of the selected resistor in the first resistor string to the first of the second resistor string during the operation of the digital-to-analog converter. An input terminal and a second input terminal, when the resistance on the first resistor string is switched, the first input terminal and the second input terminal of the second resistor string are switched simultaneously. Therefore, when the resistance on the first resistance string is switched, the first input terminal and the second input terminal of the second resistance string increase the same voltage to ground. Therefore, each time the first resistance string is switched, the voltage across the resistance in the second resistance string changes uniformly, and the matching is greatly improved, so that the output analog signal will not be different due to different codes, which will affect the conversion accuracy of digital-to-analog conversion. .

At the same time, because the resistance of the first resistance string is switched, the direction of the current in the second resistance string is always fixed and will not change with the resistance of the first resistance string. Therefore, the logic of the second switch network is switched. The switching logic is independent from the first switching network. In the end, the first control signal and the second control signal are independent from each other, which makes the first decoding circuit and the second decoding circuit independent from each other, which makes the decoding complexity greatly. Reduce, improve work efficiency and reduce power consumption.

At the same time, since the third switch and the fourth switch in the third switch network are only sequentially switched in accordance with the selection order of the resistance of the first resistor string, the complexity is not high. Therefore, the digital-to-analog converter of the present invention has higher conversion efficiency and smaller area under high bits.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features, and advantages of the present invention will be more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings.

FIG. 1 shows a schematic structural diagram of a conventional resistive digital-to-analog converter.

FIG. 2 shows a schematic diagram of a typical 4-bit digital-to-analog converter composed of a master and a slave resistor string.

FIG. 3 is a schematic structural diagram of an existing digital-to-analog converter when the input digital signal is 0011.

FIG. 4 is a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present invention.

FIG. 5 is a schematic diagram showing the relationship between the bits of the digital signals I4I3I2I1 and the closed / open states of the switches SM1-SM5, switches SHI and SH2, and switches SL1-SL4 in FIG.

FIG. 6 is a schematic structural diagram of a digital-to-analog converter according to a first embodiment of the present invention when an input digital signal is 0000.

FIG. 7 is a schematic structural diagram of a digital-to-analog converter according to a first embodiment of the present invention when the input digital signal is 0100.

detailed description

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are denoted by similar reference numerals. For clarity, the various elements in the drawings have not been drawn to scale. In addition, some well-known parts may not be shown in the drawings.

In the following, many specific details of the invention are described, such as the structure, materials, dimensions, processing techniques, and techniques of the components, in order to better understand the invention. As will be understood by those skilled in the art, the invention may be practiced without these specific details.

It should be understood that, in the following description, “circuit” refers to a conductive loop formed by at least one element or sub-circuit through an electrical connection or an electromagnetic connection. When an element or circuit is "connected" to another element or an element / circuit is "connected" between two nodes, it can be directly coupled or connected to another element or an intermediate element can exist. The connection between the elements can be Is physical, logical, or a combination. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it means that there are no intervening elements present.

FIG. 2 shows a typical 4-bit digital-to-analog converter 200 composed of a master and a slave resistor string, including a first resistor string 210, a second resistor string 230, a first switching network 220, a second switching network 240, and Decoding module 260.

The decoding module 260 is configured to obtain M control signals according to the received digital signals, where the M control signals are divided into a first control signal and a second control signal. For example, in this embodiment, the decoding module 260 obtains the first control signals C0-C4 and the second control signals D0-D3 according to the four-bit digital signals I4I3I2I1. Among them, I4 and I3 represent the most significant bits (MSB), and the first control signals C0-C4 are, for example, high-order bit control signals; I1 and I2 represent the least significant bits (Least, Significant Bit, LSB), and the second control The signals D0-D3 are, for example, low-order bit control signals.

Specifically, the decoding module 260 includes a first decoding circuit 261 and a second decoding circuit 262. The first decoding circuit 261 is configured to generate a first decoding circuit according to the two most significant bits I4 and I3 of the four-bit digital signals I4, I3, I2, and I1. A control signal C0-C4. In this embodiment, the first decoding circuit 461 is implemented using, for example, a first decoder, and decodes by using a Gray code.

The second decoding circuit 262 is configured to generate second control signals D0-D3 according to I3, I2, and I1 of the four-bit digital signals I4, I3, I2, and I1. The second decoding circuit 262 includes a second decoder 263 and a selection circuit 264.

The second decoder 263 receives the two least significant bits I2 and I1 and generates a binary signal at the output terminals A0, A1, A2, and A3 according to I2 and I1. The selection circuit 264 includes a first input terminal A and a second input terminal B. The first input terminal A is connected to the output terminals A0, A1, A2, and A3, and the second input terminal B is connected to the output terminals A0, A5 through multiple inverters 51, A1, A2, and A3 are connected, output terminals A0, A1, A2, and A3 are correspondingly connected to the input terminals of the plurality of inverters 51, and the output terminal of the inverter 51 is connected to the second input terminal B of the selection circuit 264. The selection circuit 264 is, for example, a multiplexer for selectively coupling one of the first input terminal A or the second input terminal B to the output terminal of the selection circuit 264 according to the bit I3. More specifically, when the binary signal of bit I3 is logic 0, the selection circuit 264 couples the output terminals A0, A1, A2, and A3 to the output, respectively, as shown by the solid line 52 in FIG. 8 to decode the second The converter 263 generates binary signals at the output terminals A0, A1, A2, and A3 and directly outputs the binary signals as the second control signals D0-D3. When the binary signal of bit I3 is logic 1, the output terminals A0, A1, A2, and A3 are connected to the output of the selection circuit 264 after passing through the inverter 51, as shown by the dotted line 54 in FIG. The two decoders 263 generate binary signals at the output terminals A0, A1, A2, and A3 and output the inverted signals as the second control signals D0-D3.

The first resistor string 210 is composed of a plurality of resistors Ra4-Ra1 having the same resistance value in series, and the plurality of resistors Ra4-Ra1 are connected between the reference voltage Vref and the reference ground. The second resistor string 230 is composed of a plurality of resistors Rb3-Rb1 having equal resistance values connected in series. The first switch network 220 includes a plurality of switches SM0-SM4, and the second switch network includes a plurality of switches SL0-SL3. The first switching network 220 is controlled by the first control signals C0-C4 generated by the first decoding circuit 261, and the second switching network 240 is controlled by the second control signals D0-D3 generated by the second decoding circuit. Assuming the reference voltage Vref is equal to 1V, Table 1 shows the relationship between the output result of the DAC and the first switching network 220 and the second switching network 240 under ideal conditions.

Table 1

FIG. 3 shows a schematic structural diagram of an existing digital-to-analog converter when the digital signal is 0011. As shown in Figure 3, when the input is 0011, the switches SM1, SM0, and SL3 are closed. It is assumed that the resistance of the resistors Ra4-Ra1 on the first resistor string are all R1, and that of the resistors Rb3-Rb1 on the second resistor string. The value is R2, then the total resistance of the circuit connected from the reference voltage Vref can be obtained.

Then the voltage generated on the resistor Ra1 is

In an ideal 4-bit digital-to-analog converter: R1 = R2, the voltage Va1 = 3 / 15Vref on Ra1 can be obtained according to the above formula, and resistors Rb1-Rb3 are connected in parallel on Ra1, that is, 3 LSB ( Least Significant Bit, so we can get that one LSB of the 4-bit digital-to-analog converter is 1 / 15Vref. Of course, this is only an ideal situation. In the actual circuit design of a resistive digital-to-analog converter, the resistance values of the main and second resistor strings are often not equal.

The prior art digital-to-analog converter has the following disadvantages: 1. In order to eliminate the interference of the closed current on the second resistor string 230 to the first resistor string 210 and cause each LSB error, the existing digital-to-analog converter is in the main A voltage buffer is inserted between the second resistor string. However, due to the error of the voltage buffer itself, this will increase the error of the output voltage, and the voltage buffer will consume additional power consumption and chip area. 2. It can be seen from Table 1 that when different resistors are selected in the first resistor string, the logic of the second switch network of the second resistor string is different, for example: switch SM0 and switch SM1 are closed, that is, When the resistor string Ra1 is selected, the corresponding DAC output voltage is 0-3 / 15V, and the switches closed by the second switch network are SL0-SL3 in turn; when the switches SM1 and SM2 are closed, the resistor Ra2 is selected in the first resistor string. At this time, corresponding to the DAC output voltage is 4 / 15V-7 / 15V, the switches closed by the second switch network are SL3-SL0, as shown in Table 1. Therefore, the decoding logic of the second switching network in the existing digital-to-analog converter changes according to the resistance selected by the first resistor string, which increases the complexity of digital decoding of the digital-to-analog converter and increases the workload of decoding. 3. The change in the voltage of each resistor on the second resistor string is related to the selected resistor on the first resistor string. For example: when the first resistor string is switched from resistor Ra1 to resistor Ra2, the top voltage of resistor Rb3 of the second resistor string is unchanged, but the bottom voltage of resistor Rb1 is increased; and when the first resistor string is switched from resistor Ra2 to resistor At Ra3, the top voltage of the resistor Rb3 of the second resistance string 230 increases, but the bottom voltage of the resistor Rb1 does not change. Under the same 1LSB change, due to the different resistances selected in the first resistor string 210, the voltage changes at the head and tail of the second resistor string 230 change, which may cause the output of the digital-to-analog converter under different codes. Different changes will occur, which will affect the output voltage value and the conversion accuracy of digital-to-analog conversion.

FIG. 4 is a schematic structural diagram of a digital-to-analog converter 300 according to an embodiment of the present invention. The digital-to-analog converter 300 is used to convert an N-bit digital signal into an analog signal. The digital-to-analog converter 300 may be implemented as an independent module by an integrated circuit or combined with other modules.

The periphery of the digital-to-analog converter 300 includes a first reference input terminal 16, a second reference input terminal 17, and an analog signal output terminal 18. The first reference input terminal 16 is configured to receive a reference voltage Vref, and the second reference input terminal 17 is configured to receive an analog ground signal. The reference voltage Vref enables the digital-to-analog converter 300 to generate an analog output according to a reference frame.

As shown in FIG. 4, the digital-to-analog converter 300 includes a first resistor string 310, a first switch network 320, a second resistor string 340, a second switch network 350, and a decoding module 360. The first resistor string 310 includes 2 ^{N / 2} resistors connected in series, and the second resistor string 340 includes (2 ^{N / 2} -1) resistors connected in series. N is an even number greater than 0. In this embodiment, the digital-to-analog converter 300 is used as an example for description. Therefore, the first resistor string 310 includes four resistors connected in series, and the second resistor string includes three resistors connected in series.

The decoding module 360 is configured to obtain M control signals according to the received digital signals, where the M control signals are divided into a first control signal and a second control signal. For example, in this embodiment, the decoding module 360 obtains the first control signals C0-C4 and the second control signals D0-D3 according to the four-digit numbers I4, I3, I2, and I1. Among them, I4 and I3 represent the most significant bits (MSB), and the first control signals C0-C4 are, for example, high-order bit control signals; I1 and I2 represent the least significant bits (Least, Significant Bit, LSB), and the second control The signals D0-D3 are, for example, low-order bit control signals.

Specifically, the decoding module 360 includes a first decoding circuit 361 and a second decoding circuit 362. The first decoding circuit 361 is configured to generate a first decoding circuit according to the two most significant bits I4 and I3 of the four-bit digital signals I4, I3, I2, and I1. A control signal C0-C4. In this embodiment, the first decoding circuit 361 is implemented using, for example, a decoder, and decodes by using a Gray code.

The second decoding circuit 362 is configured to generate second control signals D0-D3 according to the two least significant bits I2 and I1 of the four-bit digital signals I4, I3, I2, and I1. The second decoding circuit 362 is implemented using, for example, a decoder, and decodes by using a Gray code.

The first resistor string 310 includes resistors Ra4-Ra1 connected in series between the reference voltage Vref and the ground. Among them, the resistance values of the resistors Ra1-Ra4 are equal. It is worth noting that the two ends of the resistors Ra1, Ra2, Ra3, and Ra4 have connection terminals, for example: the two ends of resistor Ra1 have terminals T1 and T2, the resistor Ra2 has terminals T2 and T3, and the resistor Ra3 has terminals T3 and The terminal T4 and the resistor Ra4 have a terminal T4 and a terminal T5, as shown in FIG. 4. In response to the current fed by the reference voltage Vref, the resistors Ra1-Ra4 in the first resistor string 310 generate a voltage at the terminals T1-T5.

The second resistor string 340 includes resistors Rb1, Rb2, and Rb3 connected in series between the first input terminal 26 and the second input terminal 28 of the second resistor string 340, and the resistances of the resistors Rb1, Rb2, and Rb3 are substantially equal. Similarly, resistors Rb1, Rb2, and Rb3 have connection terminals at both ends, for example: resistor Rb1 has terminals Q1 and Q2, resistor Rb2 has terminals Q2 and Q3, and resistor Rb3 has terminals Q3 and Q4, as shown in Figure 4. As shown. The terminal Q3 is connected to the first input terminal 26 of the second resistor string 340, and the terminal Q0 is connected to the second input terminal 28 of the second resistor string 340.

The first switch network 320 includes (2 ^{N / 2} +1) switches, N is an even number greater than 0, and the plurality of switches are correspondingly connected to a plurality of connection terminals in the first resistor string 310. For example, in this embodiment, the first switch network 320 includes switches SM1-SM5. As shown in FIG. 4, the first path ends of the switches SM1, SM2, SM3, SM4, and SM5 are connected to terminals T1, T2, and T3, respectively. T4 and T5. The second path ends of the even-numbered switches SM2 and SM4 are connected to the first output terminal 36 of the first switching network 320; the second path ends of the odd-numbered switches SM1, SM3, and SM5 are connected to the second switching network 320. Output 38. Of course, in other embodiments of the present invention, the second path end of the odd-numbered switches SM2 and SM4 is connected to the first output end 36 of the first switch network 320; the second path of the even-numbered switches SM1, SM3, and SM5 Is connected to the second output terminal 38 of the first switching network 320. The present invention is not limited thereto, and those skilled in the art may select according to specific situations.

In addition, the closed and open states of the switches SM1, SM2, SM3, SM4, and SM5 are controlled by the first control signals C0-C4, respectively.

The second switch network 350 includes 2 ^{N / 2} switches, N is an even number greater than 0, and the plurality of switches are correspondingly connected to the plurality of connection terminals in the second resistor string 340. For example, as shown in FIG. 4, the second switch network 350 includes switches SL1, SL2, SL3, and SL4. The first path ends of the switches SL1, SL2, SL3, and SL4 are connected to the terminals Q1, Q2, Q3, and Q4, respectively. The second path ends of the switches SL1, SL2, SL3, and SL4 are connected to the analog signal output end 18. The closed and open states of the switches SL1, SL2, SL3, SL4 are controlled by the second control signals D0-D3.

The digital-to-analog converter 300 further includes a third switching network 330. The third switching network 330 is configured to provide a current path from the first switching network 320 to the second resistor string 340. The third switch network 330 includes a first switch circuit and a second switch circuit, and each of the first switch circuit and the second switch circuit includes switches SH1 and SH2. The first path terminal of the first switching circuit is connected to the first output terminal 36 of the first switching network 320, and the second path terminal of the first switching circuit is connected to the first input terminal 26 and the second input of the second resistor string 340. Terminal 28 is connected. The first path terminal of the second switching circuit is connected to the second output terminal 38 of the first switching network 320, and the second path terminal of the second switching circuit is connected to the first input terminal 26 and the second input terminal 28 of the second resistor string 340. connection. Specifically, the first path terminals of the switches SH1 and SH2 of the first switching circuit are connected to the first output terminal 36 of the first switching network 320, and the second path terminal of the switch SH1 is connected to the first input terminal 26 of the second resistor string 340. The second path terminal of the switch SH2 is connected to the second input terminal 28 of the second resistor string 340. A first path terminal of the switches SH1 and SH2 of the second switching circuit is connected to the second output terminal 38 of the first switching network 320, and a second path terminal of the switch SH1 is connected to the second input terminal 28 of the second resistor string 340. The second path terminal of SH2 is connected to the first input terminal of the second resistor string 340.

The first switching network 320 is used to select a resistor from the resistors Ra1-Ra4 of the first resistor string 310 according to the most significant bits I4 and I3 in the digital signal, and the third switching network 330 is used to select the resistance of the selected resistor. Both ends are coupled to the first input terminal 26 and the second input terminal 28 of the second resistor string 340. In response to the current flowing between the first resistor string 310 and the second resistor string 340 through the first switching network 320 and the third switching network 330, the resistors Rb1-Rb4 in the second resistor string 340 are at the terminal Q1 A voltage is generated at -Q4. The second switching network 350 is configured to select a resistor from the resistors Rb1 to Rb3 of the second resistor string 340 and couple a voltage generated at a terminal of the resistor to the analog signal output terminal 18 of the digital-to-analog converter 300.

FIG. 5 shows the relationship between the bits of the four-bit digital signal I4I3I2I1 and the closed / open states of the switches SM1-SM5, switches SH1 and SH2, and switches SL1-SL4.

In actual operation, as shown in FIG. 5, when the resistance selected in the first resistance string 310 is an odd number of resistances, the switch SH1 in the third switch network 330 is closed; when the resistance selected in the first resistance string 310 is For the even number of resistors, the switch SH2 in the third switching network 330 is closed. Based on this, the switching sequence of the second switching network 350 always follows the bits of the digital signals I4I3I2I1 from small to large, and is sequentially switched by the switches SL1-SL4. In this way, the logic switching of the second switching network 350 and the switching logic of the first switching network 320 are independent of each other. In the end, the first control signal and the second control signal are independent of each other, thereby greatly reducing the complexity of decoding and improving work. Efficiency and reduce power consumption.

In addition, as a first example, when the input digital signal is 0000, the switches SM1 and SM2 are closed in the first switch network 320, the switch SH1 is closed in the third switch network 330, and the second switch network 350 is closed. Lieutenant switch SL1 is closed. The terminal T2 of the resistor Ra1 is coupled to the first input terminal 26 of the second resistor string 340 through the switch SM2 and the switch SH1 of the first switching circuit in the third switching network 330, as shown by the dotted line 61 in FIG. 6. The terminal T1 of the resistor Ra1 is coupled to the second input terminal 28 of the second resistor string 340 through the switch SM1 and the switch SH1 of the second switching circuit in the third switching network 330, as shown by the dotted line 62 in FIG. 6.

When the input is 0100, the switches SM2 and SM3 are closed in the first switch network 320, the switch SH2 is closed in the third switch network 330, and the switch SL1 is closed in the second switch network 350. The terminal T3 of the resistor Ra2 is coupled to the first input terminal 26 of the second resistor string 340 through the switch SM3 and the switch SH2 of the second switching circuit in the third switching network 330, as shown by the dashed line 71 in FIG. 7. The terminal T2 of the resistor Ra2 is coupled to the second input terminal 28 of the second resistor string 340 through the switch SM2 and the switch SH2 of the first switching circuit in the third switching network 330, as shown by the dashed line 72 in FIG. 7.

According to the above two specific examples, we can obtain that in the embodiment of the present invention, when the resistance on the first resistance string 310 is switched, the first input terminal 26 and the second input terminal 28 of the second resistance string 340 are performed simultaneously. Switch. Therefore, when the resistance on the first resistance string 310 is switched, the first input terminal 26 and the second input terminal 28 of the second resistance string 340 increase the same voltage to ground. For example: when the first resistor string 310 is switched from Ra1 to resistor Ra2, the voltage across ground of each resistor on the second resistor string 340 is increased by 1 / 4Vref; when the first resistor string 310 is switched from resistor Ra2 to resistor At Ra3, the voltage rising to ground across each resistor on the second resistor string 340 is also 1 / 4Vref. Therefore, each time the first resistor string 310 is switched, the voltage across the resistors in the second resistor string 340 changes uniformly, so that the output analog signal will not be different due to different codes, which will affect the conversion accuracy of digital-to-analog conversion.

The “resistance” mentioned in the above embodiments may be a single physical resistor or a resistance element, or may be a combination of multiple physical resistors or resistance elements. In other words, the resistive digital-to-analog converter shown in the present invention is applicable to various types of impedance elements, and the impedance of each impedance element corresponds to the required resistance. Therefore, the "resistance" referred to here is any number of different types of resistance elements, such as precision thin film resistors, based on circuit layout, which are made of SiCr or other materials, or in the case of integrated circuits (mixed with Hetero-p- or n-) polysilicon. It is also understood that the "resistance" described herein may include any circuit element that can generate a voltage proportional to the current passing through it across its terminals.

In the above embodiments, the present invention is described in detail by taking a 4-digit digital-to-analog converter as an example. However, as known to those skilled in the art, the digital-to-analog converter disclosed in the present invention is also suitable for converting digital signals of other bits The present invention is not limited thereto.

At the same time, since the switches SH1 and SH2 in the third switch network are only sequentially switched in accordance with the selection order of the resistances of the first resistor string, the complexity is not high. Therefore, the digital-to-analog converter of the present invention has higher conversion efficiency and smaller area under high bits.

It should be noted that in this article, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that these entities or operations There is any such actual relationship or order among them. Moreover, the terms "including", "comprising", or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements includes not only those elements but also those that are not explicitly listed Or other elements inherent to such a process, method, article, or device. Without more restrictions, the elements defined by the sentence "including a ..." do not exclude the existence of other identical elements in the process, method, article, or equipment including the elements.

The embodiments according to the present invention are described above. These embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the above description. These embodiments are selected and described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

A digital-to-analog converter includes:

A first resistor string including a plurality of first resistors connected between a reference voltage and a reference ground;

A second resistor string including a plurality of second resistors connected between the first input terminal and the second input terminal;

A first switch network, configured to select at least one first resistor in the first resistor string according to a first significant bit of an input digital signal;

A second switch network, configured to select at least one second resistor in the second resistor string according to a second significant bit of the digital signal input,

The digital-to-analog converter further includes a third switching network for providing a current path from the first switching network to the second resistor string.
The digital-to-analog converter according to claim 1, wherein both ends of the first resistor include a first terminal, and both ends of the second resistor include a second terminal.
The digital-to-analog converter according to claim 2, wherein adjacent first resistors in the first resistor string share the first terminal, and adjacent second ones in the second resistor string The resistor shares the second terminal.
The digital-to-analog converter according to claim 2, wherein the first switch network includes a plurality of first switches, a first path end of the plurality of first switches is correspondingly connected to the first terminal, and a second The path end is connected to the output end of the first switch network;

The second switch network includes a plurality of second switches. A first path end of the second switch is correspondingly connected to the second terminal. A second path end is connected to an output end of the second switch network. An output terminal of the second switching network is used to output an analog signal corresponding to the digital signal.
The digital-to-analog converter according to claim 4, wherein the first switching network includes a first output terminal and a second output terminal,

Wherein, the second path terminal of the even-numbered first switch is connected to the first output terminal, and the second path terminal of the odd-numbered first switch is connected to the second output terminal.
The digital-to-analog converter according to claim 4, wherein the first switching network includes a first output terminal and a second output terminal,

Wherein, the second path end of the odd-numbered first switch is connected to the first output terminal, and the second path end of the even-numbered first switch is connected to the second output terminal.
The digital-to-analog converter according to claim 5 or 6, wherein the third switching network includes a first switching circuit and a second switching circuit, and the first switching circuit and the second switching circuit each include a third Switch and fourth switch,

The first path end of the third switch in the first switch circuit is connected to the first output end, the second path end is connected to the first input end, and the first path end of the fourth switch is The path end is connected to the first output end, and the second path end is connected to the second input end.

A first path terminal of the third switch in the second switch circuit is connected to the second output terminal, a second path terminal is connected to the second input terminal, and a first path terminal of the fourth switch It is connected to the second output terminal, and the second path terminal is connected to the first input terminal.
The digital-to-analog converter according to claim 4, further comprising:

A first decoding circuit configured to obtain a first control signal according to the first significant bit of the digital signal, where the first control signal is used to control the on / off states of the plurality of first switches;

A second decoding circuit is configured to obtain a second control signal according to the second significant bit of the digital signal, and the second control signal is used to control the on / off states of the plurality of second switches.
The digital-to-analog converter according to claim 7, wherein the first control signal and the second control signal are independent of each other.
The digital-to-analog converter according to claim 1, wherein the first significant bit is a most significant bit, and the second significant bit is a least significant bit.