CN101777917A - Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof - Google Patents
Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof Download PDFInfo
- Publication number
- CN101777917A CN101777917A CN201010022813A CN201010022813A CN101777917A CN 101777917 A CN101777917 A CN 101777917A CN 201010022813 A CN201010022813 A CN 201010022813A CN 201010022813 A CN201010022813 A CN 201010022813A CN 101777917 A CN101777917 A CN 101777917A
- Authority
- CN
- China
- Prior art keywords
- analog
- module
- given
- digital
- level circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
The invention relates to a pipeline analog-to-digital converter and a quick calibration method of capacitance mismatch thereof. The quick calibration method is characterized by carrying out inverted order calibration from a level circuit module of the last level. The calibration method of the level circuit module of each level comprises the following steps of: 1. starting calibration: closing the second transfer switch and the fourth transfer switch and cutting off the first transfer switch and the third transfer switch to enable the level circuit modules to work in the calibration state; 2. measuring quantitative results: setting input signals for the level circuit modules, and carrying out analog-to-digital conversion by the level circuit modules following the corresponding level and the back analog-to-digital conversion module of the pipeline analog-to-digital converter to obtain a set of corresponding quantitative results; and 3. measuring quantitative step length: subtracting the corresponding quantitative results to obtain the actual quantitative step length of the level circuit modules and storing the step length in a storage module. Roughly quantitative calibration results are added by the invention, thereby improving the linearity of the transmission function of the pipeline analog-to-digital converter and increasing the significant digit of analog-to-digital conversion.
Description
Technical field
The present invention relates to a kind of analog to digital converter and calibration steps thereof, the quick calibration method of particularly a kind of production line analog-digital converter and capacitance mismatch thereof.
Background technology
See also shown in Figure 1, existing production line analog-digital converter keeps the analog signal sampling of 100 pairs of inputs of module by the sampling that is provided with, some grades of circuit modules 200 and back analog-to-digital conversion module 300 by series connection carry out analog-to-digital quantification, and the quantized result at different levels that obtain are by numeral dislocation summation module 400 weighting summations output digital signal.
See also shown in Figure 2ly, each grade circuit module 200 is subjected to the non-overlapping clock control of two-phase.When phase place 1, the analog signal sampling of 230 pairs of this grade inputs of level circuit sampling module, 210 pairs of these signals of analog-to-digital conversion module are converted to thick quantized result D
OutWhen phase place 2, D/A converter module 220 changes into thick quantized analog signal again with thick quantized result; Level circuit sampling module 230 deducts thick quantized analog signal from input signal then, and will proceed thick quantification to next stage after the subtraction result amplification.Each grade level circuit module 200 is all as sampling, slightly quantize, subtract each other amplification as the streamline.The thick quantized result of each grade circuit module 200 also outputs to numeral dislocation summation module 400.
See also switched-capacitor circuit shown in Figure 3, by with analog-to-digital conversion module 210 mating reactions, realized jointly Fig. 2 middle rank circuit module 200 sampling, slightly quantize, subtract each other the process of amplification.When phase place 1,1 switch conduction, 2 switches open circuit, C
S1To C
SNTo input voltage V
InSampling; Analog-to-digital conversion module 210 total N level decision level V
REF1To V
REFN, to input voltage V
InSlightly quantize; When phase place 2,2 switch conductions, 1 switch open circuit is by the thick quantized result decision C of analog-to-digital conversion module 210
S1To C
SNWhat connect is that reference voltage is+V
RStill-V
R, this has realized the function of D/A converter module 220 among Fig. 2.
Please cooperate referring to Fig. 4 and shown in Figure 5,, access the desirable transfer function of level circuit module 200 as shown in phantom in Figure 4 by charge conservation formula transformation energy if the electric capacity in the above-mentioned switched-capacitor circuit all is ideal value.Suppose that at different levels grades of circuit modules 200 all are desirable analog to digital converters, so wherein the analog signal surplus V of every grade of output
OutCarry out the quantized result that analog-to-digital conversion obtains by level circuit module 200 after this grade and back analog-to-digital conversion module 210, with the thick quantized result D of this grade
OutWeighting summation obtains the complete transmission function of grade circuit module 200.Ideally, this complete transfer function (V
Out+ D
Out) should be the fixing straight line of a slope as shown in phantom in Figure 5, by each decision level V
REFAdd ideal quantized step-length V
STEP_IDEALBe Δ D
Out=1 weight obtains.
But in actual conditions, there is mismatch in the electric capacity of switched-capacitor circuit, comprises systematic error (there is the parasitic capacitance of mismatch in domain when realizing) and random error (during design the electric capacity of identical size make not be equal).The mismatch of electric capacity can cause the variation of transfer function gain and the variation (this also is called the digital-to-analogue conversion noise) of zero crossing, so the transfer function and the complete transmission function of actual level circuit module 200 are shown in solid line among Fig. 4 and Fig. 5.Because the existence of digital-to-analogue conversion noise, make desirable Δ D
Out=1 weight is not equal to actual weight, i.e. ideal quantized step-length V
STEP_IDEALAnd be not equal to V
REFThe actual quantization step-length V at place
STEP_REALTherefore in Fig. 4, show as the inconsistent of straight slope, and in Fig. 5 complete transfer function at V
REFGo out to have produced " jump ".
The mismatch of electric capacity can limit the linearity and the number of significant digit of production line analog-digital converter.The matching precision of electric capacity is not less than 0.1% usually, and the precision of not doing the production line analog-digital converter of any calibration is limited in 10 to 12.
Existing calibration steps for capacitance mismatch by adding random perturbation, uses related algorithm to estimate the size of capacitance mismatch, deducts the error that mismatch causes again.But the alignment time of this calibration steps is long, and can be along with the increase of number of significant digit, and the alignment time can prolong with index.
Summary of the invention
The object of the present invention is to provide the quick calibration method of a kind of production line analog-digital converter and capacitance mismatch thereof, can improve the linearity of production line analog-digital converter transfer function, reduce the alignment time of production line analog-digital converter, increase analog-to-digital number of significant digit.
In order to achieve the above object, technical scheme of the present invention provides a kind of production line analog-digital converter, some grades of circuit modules by series connection carry out analog-to-digital conversion with the back analog-to-digital conversion module to analog signal, export digital signal by the weighting summation as a result that numeral dislocation summation module will be changed;
Above-mentioned each grade circuit module comprises cascade analog input port, level circuit sampling module, subtracter block, the gain amplification module that connects successively, the analog-to-digital conversion module that is connected with above-mentioned cascade analog input port also is connected with above-mentioned subtracter block by D/A converter module, it is characterized in that:
Above-mentioned level circuit module also comprises given analog input port, given digital input port, first to the 4th diverter switch, memory module;
Above-mentioned cascade analog input port first diverter switch of connecting is connected with the positive input terminal of above-mentioned subtracter block by above-mentioned level circuit sampling module;
Above-mentioned cascade analog input port, first diverter switch also are connected with the negative input end of above-mentioned subtracter block by analog-to-digital conversion module, the 3rd diverter switch, the D/A converter module of connecting successively;
Above-mentioned subtracter block will deduct the thick quantized analog signal of above-mentioned D/A converter module output from the analog signal of above-mentioned level circuit sampling module input, and will be sent to above-mentioned gain amplification module;
Above-mentioned gain amplification module output amplified analog signal surplus is to the level circuit module of next stage;
Above-mentioned given analog input port second diverter switch of connecting is connected with above-mentioned level circuit sampling module, analog-to-digital conversion module respectively;
Above-mentioned analog-to-digital conversion module is connected with above-mentioned memory module, exports thick quantized result and controls the thick numeral dislocation summation module that quantizes calibration result to above-mentioned production line analog-digital converter of above-mentioned memory module output;
Above-mentioned given digital input port is connected with above-mentioned D/A converter module by the 4th diverter switch.
A kind of quick calibration method of capacitance mismatch of production line analog-digital converter is characterized in that, begins inverted order calibration from afterbody level circuit module, comprises following steps for the calibration of each grade level circuit module:
Second diverter switch, the 4th diverter switch closure, first diverter switch, the 3rd diverter switch disconnect, and make a grade circuit module be operated in align mode;
Be the given input signal of level circuit module, carry out analog-to-digital conversion, obtain one group of corresponding quantized result by the level circuit module after this grade and the back analog-to-digital conversion module of above-mentioned production line analog-digital converter;
Corresponding quantized result is subtracted each other the actual quantization step-length that obtains about the level circuit module, and it is kept in the memory module.
Above-mentioned steps 2 also comprises following steps:
Step 2.1 signal feeding
The simulate given signal of importing for the given analog input port of level circuit module is decision level, is that the digital given signal that its given digital input port is imported is given quantized result;
The output of this grade of step 2.2 surplus
The simulate given signal of input stage circuit module deducts the thick quantized analog signal that digital given signal obtains through digital-to-analogue conversion behind over-sampling, after amplifying through gain, export the analog signal surplus of this grade level circuit module;
Grade surplus output of step 2.3 back
The analog signal surplus of level circuit module is slightly quantized successively the analog signal surplus of each grade after obtaining by all grades circuit module after this grade;
Step 2.4 back analog-to-digital conversion
By the analog signal surplus of afterbody level circuit module output, carry out analog-to-digital conversion through analog-to-digital conversion module later and obtain quantized result;
Above-mentioned steps 2.1 also comprises following steps:
Step 2.1.1 is one group of decision level for the simulate given signal of the given analog input port input of level circuit module, and the digital given signal of importing for its given digital input port is one group of given quantized result i (wherein i increases progressively from 1 to N);
Step 2.1.2 is above-mentioned one group of decision level for the simulate given signal of the given analog input port input of level circuit module, and the digital given signal of importing for its given digital input port is one group of given quantized result i+1 (wherein i increases progressively from 1 to N).
Slightly quantize at each grade level circuit module in the above-mentioned steps 2.3, also comprise following steps:
The analog signal surplus of the given analog input port input upper level of step 2.3.1 level circuit module obtains thick quantized result through analog-to-digital conversion;
Step 2.3.2 is by thick quantized result
The thick quantification calibration result of corresponding this grade level circuit module in the control output storage array, and be sent to given digital input port;
Step 2.3.3 slightly quantizes calibration result and obtains thick quantized analog signal through digital-to-analogue conversion, and sends to the negative input end of subtracter block;
The analog signal surplus of the upper level of the given analog input port input of step 2.3.4 sends to the positive input terminal of subtracter block through level circuit sampling module;
Step 2.3.5 upper level analog signal surplus deducts thick quantized analog signal, after amplifying through gain, exports the analog signal surplus of this grade;
Above-mentioned steps 2.4 also comprises following steps:
Step 2.4.1 is level circuit module input above-mentioned given signal in step 2.1.1, be that given analog input port is imported one group of decision level, given digital input port is imported one group of given quantized result i (wherein i increases progressively from 1 to N), and the one group of quantized result that obtains by level circuit module after this grade and back analog-to-digital conversion module is first quantized result successively;
Step 2.4.2 is level circuit module input above-mentioned given signal in step 2.1.2, be that given analog input port is imported one group of decision level, for its given digital input port is imported one group of given quantized result i+1 (wherein i increases progressively from 1 to N), obtain one group of second quantized result by level circuit module after this grade and back analog-to-digital conversion module successively.
The thick quantification calibration result of above-mentioned each grade level circuit module output has kept some redundant digits.
The quick calibration method of a kind of production line analog-digital converter provided by the invention and capacitance mismatch thereof, compared with prior art, its advantage is: the present invention has reduced the time of calibration because some grades of circuit modules that are provided with are carried out the inverted order calibration;
The present invention outputs to numeral dislocation summation module owing to will slightly quantize calibration result at each grade level circuit module, what be weighted addition is slightly to quantize the pairing actual quantization step-length of calibration result, so in level circuit module transfer function, " jump " that the digital-to-analogue conversion noise causes has been eliminated, improve the linearity of production line analog-digital converter transfer function, increased analog-to-digital number of significant digit.
Description of drawings
Fig. 1 is the general structure schematic diagram of prior art production line analog-digital converter;
Fig. 2 is the structural representation of the level circuit module of prior art production line analog-digital converter;
Fig. 3 is the circuit theory diagrams of the level circuit module of prior art production line analog-digital converter;
Fig. 4 is the transfer function schematic diagram of the level circuit module of prior art production line analog-digital converter;
Fig. 5 is the complete transmission function schematic diagram of the level circuit module of prior art production line analog-digital converter;
Fig. 6 is the structural representation of the level circuit module of production line analog-digital converter of the present invention;
Fig. 7 is the transfer function schematic diagram of level circuit module of the present invention;
Fig. 8 is the complete transmission function schematic diagram of level circuit module of the present invention;
Fig. 9 is the general structure schematic diagram of production line analog-digital converter of the present invention;
Figure 10 is the static non linear error schematic diagram before the production line analog-digital converter calibration of the present invention;
Figure 11 is the static non linear error schematic diagram after the production line analog-digital converter calibration of the present invention;
Figure 12 is the kinematic nonlinearity error schematic diagram before the production line analog-digital converter calibration of the present invention;
Figure 13 is the kinematic nonlinearity error schematic diagram after the production line analog-digital converter calibration of the present invention.
Embodiment
Below in conjunction with description of drawings the specific embodiment of the present invention.
See also shown in Figure 9, the quick calibration method of a kind of production line analog-digital converter provided by the invention and capacitance mismatch thereof, relate to a kind of production line analog-digital converter, keep module to the sampling of input analog signal by sampling, some grades of circuit modules 20 and back analog-to-digital conversion module 30 by series connection carry out analog-to-digital quantification, quantized result at different levels is passed through numeral dislocation summation module 40 weighting summations, and by redundant processing module 50 output digital signals.This production line analog-digital converter improves the some grades of circuit modules 20 that existing production line analog-digital converter is provided with.
See also shown in Figure 6ly, each grade circuit module 20 comprises 3 input ports, 4 diverter switch sw1 to sw4, level circuit sampling module 23, subtracter block 24, gain amplification module 25, analog-to-digital conversion module 21, D/A converter module 22, memory module 26 among the present invention.
Input port comprises cascade analog input port V
InWith given analog input port Forced V
In, given digital input port Forced D
In
Cascade analog input port V
InAfter the first diverter switch sw1 connects, be connected with level circuit sampling module 23, analog-to-digital conversion module 21 respectively; Given analog input port Forced V
InAfter the second diverter switch sw2 connects, also be connected with level circuit sampling module 23, analog-to-digital conversion module 21 respectively.In normal operation, the first diverter switch sw1 closure, the second diverter switch sw2 disconnect, with the simulation primary signal of upper level level circuit module 20 outputs by cascade analog input port V
InBe transferred to a grade circuit sampling module 23, analog-to-digital conversion module 21.Under align mode, the second diverter switch sw2 closure, the first diverter switch sw1 disconnect the simulate given signal by given analog input port Forced V
InBe transferred to a grade circuit sampling module 23, analog-to-digital conversion module 21.
Analog-to-digital conversion module 21 is flash type (Flash) analog to digital converters.Analog-to-digital conversion module 21 will simulate primary signal from the higher level of input port input or the simulate given conversion of signals becomes thick quantized result D at the corresponding levels
Out, and send to memory module 26; Analog-to-digital conversion module 21 also can be by the 3rd diverter switch sw3 control of series connection, with the thick quantized result D after the conversion
OutSend to D/A converter module 22.
Given digital input port Forced D
InThe 4th diverter switch sw4 by series connection is connected with D/A converter module 22.By the 3rd diverter switch sw3, the 4th diverter switch sw4 control, select the at the corresponding levels thick quantized result D after D/A converter module 22 input analog-to-digital conversion
Out, or by given digital input port Forced D
InThe given signal of input digit.Thick quantized analog signal after D/A converter module 22 will be changed sends to the negative input end mouth of subtracter block 24.
The input and the cascade analog input port V of level circuit sampling module 23
In, given analog input port Forced V
InConnect, the simulation primary signal or the simulate given signal of the upper level of input are sampled by the first diverter switch sw1, second diverter switch sw2 control, and send to the positive input terminal of subtracter block 24.
Subtracter block 24 will deduct the thick quantized analog signal of D/A converter module 22 outputs from the signal of level circuit sampling module 23 outputs, and by after 25 amplifications of gain amplification module, obtain analog signal surplus V
OutBe sent to next stage level circuit module 20.
The quick calibration method of a kind of production line analog-digital converter provided by the invention and capacitance mismatch thereof, owing to there is not switched-capacitor circuit, back analog-to-digital conversion module 30 does not need the calibration capacitance mismatch, since the calibration of N level level circuit inverted order, comprises following steps:
The second diverter switch sw2, the 4th diverter switch sw4 closure, the first diverter switch sw1, the 3rd diverter switch sw3 disconnect, and make grade circuit module 20 be operated in align mode;
Step 2.1 signal feeding
(following j successively decreases from N to 1)
Change is input to the simulate given signal of j level level circuit module 20, digital given signal at interval, and is as shown in table 1 below.Be the given analog input port Forced V of j level level circuit module 20
InThe simulate given signal of input is decision level V
REF1To V
REFN, be its given digital input port Forced D
InThe digital given signal of input is given quantized result 1 to N+1.
Step 2.1.1 makes Forced V to j level level circuit module 20 input decision level, given quantized result
In=V
REF (i), Forced D
In=i (wherein i increases progressively from 1 to N);
Step 2.1.2 makes ForcedV to j level level circuit module 20 input decision level, given quantized result
In=V
REF (i), Forced D
In=i+1 (wherein i increases progressively from 1 to N);
| ??DL | ??Forced?V in | ??Forced?D in |
| ??DL STEP1A | ??V REF1 | ??1 |
| ??DL STEP1B | ??V REF1 | ??2 |
| ??DL STEP2A | ??V REF2 | ??2 |
| ??DL STEP2B | ??V REF2 | ??3 |
| ??…… | ??…… | ??…… |
| ??DL STEP(N-1)A | ??V REF(N-1) | ??N-1 |
| ??D LSTEP(N-1)B | ??V REF(N-1) | ??N |
| ??DL STEPNA | ??V REFN | ??N |
| ??DL STEPNB | ??V REFN | ??N+1 |
The given input signal of table 1 grade circuit module and the table of comparisons of exporting quantized result;
Step 2.2 surplus output at the corresponding levels
The given digital input port Forced D of step 2.2.1 j level level circuit module 20
InThe digital given signal of input is converted to thick quantized analog signal through D/A converter module 22, and sends to the negative input end of subtracter block 24;
The given analog input port Forced V of step 2.2.2 j level level circuit module 20
InThe simulate given signal of input sends to the positive input terminal of subtracter block 24 through level circuit sampling module 23;
Step 2.2.3 simulate given signal deducts thick quantized analog signal, after amplifying through gain, and output analog signal surplus V
Out (j)
Grade surplus output of step 2.3 back
Slightly quantize to N level level circuit module 20 by the j+1 level successively, all comprise following steps for each grade level circuit module 20 wherein:
The given analog input port of step 2.3.1 Forced V
InThe analog signal surplus of input upper level obtains thick quantized result D through analog-to-digital conversion
Out
Step 2.3.2 is by thick quantized result D
OutThe thick quantification calibration result ROM (D of j+1 level level circuit module 20 in the control output storage array
Out)
(j+1), and be sent to given digital input port Forced D
In
Step 2.3.3 slightly quantizes calibration result ROM (D
Out)
(j+1)Obtain thick quantized analog signal through digital-to-analogue conversion, and send to the negative input end of subtracter block 24;
The given analog input port of step 2.3.4 Forced V
InThe analog signal surplus V of the upper level of input
Out (j)Send to the positive input terminal of subtracter block 24 through level circuit sampling module 23;
Step 2.3.5 upper level analog signal surplus deducts thick quantized analog signal, after amplifying through gain, and output analog signal surplus V
Out (j+1)
Step 2.4 back analog-to-digital conversion
By the analog signal surplus V of j+1 level to 20 outputs of N level level circuit module
Out, carry out analog-to-digital conversion through analog-to-digital conversion module 30 later and obtain quantized result DL;
Among step 2.4.1 such as the step 2.1.1, to j level level circuit module 20 input ForcedV
In=V
REF (i), Forced D
In=i, successively by the level circuit module 20 after at the corresponding levels (promptly from j+1 level level circuit module 20 to N level level circuit module 20) and afterwards analog-to-digital conversion module 30 carry out analog-to-digital conversion and obtain one group of first quantized result DL
STEP (i) A
Among step 2.4.2 such as the step 2.1.2, to j level level circuit module 20 input Forced V
In=V
REF (i), Forced D
In=i+1, successively by the level circuit module 20 after at the corresponding levels (promptly from j+1 level level circuit module 20 to N level level circuit module 20) and afterwards analog-to-digital conversion module 30 carry out analog-to-digital conversion and obtain one group of second quantized result DL
STEP (i) B
With the corresponding first quantized result DL
STEP (i) AWith the second quantized result DL
STEP (i) BSubtract each other the one group of actual quantization step-length V that obtains about j level level circuit module 20
STEP_REAL (i), i.e. V
STEP_REAL (i)=DL
STEP (i) A-DL
STEP (i) B, and it is kept in the memory module 26, use during for the level circuit module 20 of calibration prime and operate as normal.
In above-mentioned steps 2.3.2, when j level level circuit module 20 is calibrated, owing to the level circuit module 20 after it (promptly from j+1 level level circuit module 20 to N level level circuit module 20) was carried out calibration, suppose that a level circuit module 20 afterwards at the corresponding levels all is desirable analog to digital converter, therefore need get thick quantification calibration result ROM (D
Out) be input to given digital input port Forced D
In, guarantee the calibration effect of level circuit module 20 at the corresponding levels.
Because the non-ideal factor that exists in the production line analog-digital converter, grade circuit module 20 after can influencing after the analog-to-digital conversion module 30 and the corresponding levels is as the hypothesis of ideal mode number converter, so the thick quantification calibration result that each grade level circuit module 20 is exported has kept some redundant digits to guarantee to calibrate effect.
The numeral dislocation summation module of production line analog-digital converter is with the thick quantification calibration result ROM (D of each grade level circuit module 20 outputs
Out) and the quantized result DL of the back analog-to-digital conversion module 30 output addition that misplaces, and after having omitted redundant digit, the analog-to-digital conversion result of output stream pipeline analog-to-digital converter.
As the step 2.2 of above-mentioned align mode in the level circuit module 20 before the corresponding levels is calibrated or during in normal operating conditions, as shown in table 2 below, level circuit module 20 is by thick quantized result D
OutControl is from the corresponding thick quantification calibration result ROM (D of memory module 26 outputs
Out); If the thick quantized result D of level circuit module 20
Out=1, then read ROM (1)=0 as the thick calibration result that quantizes from memory module 26; If thick quantized result D
Out=2, then read ROM (2)=V
STEP_REAL1As thick quantification calibration result; And the like, if the D of this level
Out=N+1 then reads ROM (N+1)=V
STEP_REAL1+ V
STEP_REAL2+ ... V
STEP_REALNAs thick quantification calibration result output.
| ??D out | ??ROM(D out) |
| ??1 | ??0 |
| ??2 | ??V STEP_REAL1 |
| ??3 | ??V STEP_REAL1+V STEP_REAL2 |
| ??D out | ??ROM(D out) |
| ??…… | ??…… |
| ??N+1 | ??V STEP_REAL1+V STEP_REAL2+…V STEP_REALN |
The thick quantized result of table 2 grade circuit module and the thick table of comparisons that quantizes calibration result;
Please cooperate referring to Fig. 6, Fig. 7 and shown in Figure 8, be in normal operating conditions at production line analog-digital converter, during the i.e. first diverter switch sw1, the 3rd diverter switch sw3 closure, the second diverter switch sw2, the 4th diverter switch sw4 disconnection, the simulation primary signal is carried out analog-to-digital conversion by at different levels grades of circuit modules 20 and back analog-to-digital conversion module 30 successively; Because each grade level circuit module 20 all will slightly quantize calibration result ROM (D
Out) rather than thick quantized result D
OutOutput to numeral dislocation summation module, so what be weighted addition is slightly to quantize calibration result ROM (D
Out) pairing actual quantization step-length V
STEP_REAL, rather than thick quantized result D
OutPairing ideal quantized step-length V
STEP_IDEALSo in level circuit module 20 transfer functions, " jump " that the digital-to-analogue conversion noise causes has been eliminated, the linearity of the complete transmission function of production line analog-digital converter can not be affected.
Seeing also shown in Figure 9ly, below is example with the production line analog-digital converter of 16 outputs, by software MATLAB emulation, the calibration effect of the present invention for capacitance mismatch in the production line analog-digital converter is described.
Setting production line analog-digital converter has 6 level circuit modules 20, wherein first three grade circuit module 20 each be 17 grades of quantized result, gain is 8, exports 5 bit digital value; Each is 9 grades of quantized result for three level circuit modules in back 20, and gain is 4, exports 4 bit digital value; Back analog-to-digital conversion module 30 is 33 grades of quantized result, exports 6 bit digital value.The output figure place of each grade circuit obtains 20 bit digital value after through the dislocation addition, during calibration and operate as normal all be to use 20, but finally export 16 bit digital value, omit last 4 redundant digits.In the emulation, except capacitance mismatch, some other non-ideal factor such as comparator imbalance, amplifier finite gain are all taken into account, and the result after the output stream pipeline analog-to-digital converter is not calibrated and calibrated simultaneously as a comparison.
Please cooperate referring to Figure 10 to shown in Figure 13, be respectively the static non linear sum of errors kinematic nonlinearity error after production line analog-digital converter is not calibrated and calibrated, and is summarized in the following table 3.Wherein Figure 10 and Figure 11 are the static non linear errors of production line analog-digital converter, and maximum DNL (DNL) and maximum INL (integral nonlinearity) are 3.20LSB and 2921LSB before the calibration, exist to lose sign indicating number and nonmonotonicity; Maximum DNL (DNL) and maximum INL (integral nonlinearity) reduce to 0.14LSB and 0.31LSB after the calibration, eliminate and lose sign indicating number and bonding tonality.
Figure 12 and Figure 13 are the kinematic nonlinearity errors of production line analog-digital converter, being that a unifrequency is sinusoidal wave quantizes the spectrum analysis that export the back through production line analog-digital converter before the calibration and calibration back production line analog-digital converter, 1st represents fundamental signal among the figure, 2nd, 3rd ... the distortion of expression high-order harmonic wave.The SFDR ratio of maximum harmonic distortion (signal with) was 55.24dB before calibration, became 115.5dB after the calibration, had improved about 60dB; The ENOB (number of significant digit) that the SINAD ratio of harmonic distortion and noise (signal with) is characterized 16 from 8.3 bit recoveries to the inviscid flow pipeline analog-to-digital converter.Significantly improving on static state and the dynamic property suffices to show that the validity of calibration steps of the present invention for capacitance mismatch.
| Original output | Calibration output | |
| DNL (DNL)/LSB | ??3.20 | ??0.14 |
| Original output | Calibration output | |
| INL (integral nonlinearity)/LSB | ??2921 | ??0.31 |
| The FFT SINAD/dB ratio of harmonic distortion and noise (signal with) | ??51.90 | ??98.98 |
| FFT ENOB (number of significant digit)/bit | ??8.32 | ??15.98 |
| FFT SNR (signal to noise ratio)/dB | ??58.59 | ??98.07 |
| The FFT SFDR/dB ratio of maximum harmonic distortion (signal with) | ??55.24 | ??115.5 |
Table 3 is calibration front and back error comparison sheets of production line analog-digital converter of the present invention;
It is (16+16+16+8+8+8) * 2=144 ≈ 2^7 that the production line analog-digital converter required time of calibration counts, on average get 2^10 time to eliminate the influence of thermal noise at each point in addition, overall still only need about 2^17 cycle, far below have now calibration steps need 2^27 cycle.And along with the increase of number of significant digit, the alignment time of the present invention is a linear growth, far below the exponential growth of existing calibration steps.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be conspicuous.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (8)
1. a production line analog-digital converter carries out analog-to-digital conversion by the some grades of circuit modules (20) and the back analog-to-digital conversion module (30) of connecting to analog signal, exports digital signal by the weighting summation as a result that numeral dislocation summation module (40) will be changed;
Described each grade circuit module (20) comprises cascade analog input port, level circuit sampling module (23), subtracter block (24), the gain amplification module (25) that connects successively, the analog-to-digital conversion module (21) that is connected with described cascade analog input port also is connected with described subtracter block by D/A converter module (22), it is characterized in that:
Described level circuit module (20) also comprises given analog input port, given digital input port, first to the 4th diverter switch, memory module (26).
2. production line analog-digital converter as claimed in claim 1 is characterized in that, described cascade analog input port first diverter switch of connecting is connected with the positive input terminal of described subtracter block (24) by described level circuit sampling module (23);
Described cascade analog input port, first diverter switch also are connected with the negative input end of described subtracter block (24) by analog-to-digital conversion module (21), the 3rd diverter switch, the D/A converter module (22) of connecting successively;
Described subtracter block (24) will deduct the thick quantized analog signal of described D/A converter module (22) output from the analog signal of described level circuit sampling module (23) input, and will be sent to described gain amplification module (25);
Described gain amplification module (25) output amplified analog signal surplus is to the level circuit module (20) of next stage;
Described given analog input port second diverter switch of connecting is connected with described level circuit sampling module (23), analog-to-digital conversion module (21) respectively;
Described analog-to-digital conversion module (21) is connected with described memory module (26), exports thick quantized result and controls the thick numeral dislocation summation module (40) that quantizes calibration result to described production line analog-digital converter of described memory module (26) output;
Described given digital input port is connected with described D/A converter module (22) by the 4th diverter switch.
3. the quick calibration method of the capacitance mismatch of a production line analog-digital converter is characterized in that, from the calibration of afterbody level circuit module (20) beginning inverted order, comprises following steps for the calibration of each grade level circuit module (20):
Step 1 calibration is opened
Second diverter switch, the 4th diverter switch closure, first diverter switch, the 3rd diverter switch disconnect, and make a grade circuit module (20) be operated in align mode;
Step 2 quantized result is measured
Be the given input signal of level circuit module (20), carry out analog-to-digital conversion, obtain one group of corresponding quantized result by the level circuit module (20) after this grade and the back analog-to-digital conversion module (30) of described production line analog-digital converter;
Step 3 quantization step is measured
Corresponding quantized result is subtracted each other the actual quantization step-length that obtains about level circuit module (20), and it is kept in the memory module (26).
4. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 3 is characterized in that, described step 2 also comprises following steps:
Step 2.1 signal feeding
The simulate given signal of importing for the given analog input port of level circuit module (20) is decision level, is that the digital given signal that its given digital input port is imported is given quantized result;
The output of this grade of step 2.2 surplus
The simulate given signal of input stage circuit module (20) deducts the thick quantized analog signal that digital given signal obtains through digital-to-analogue conversion behind over-sampling, after amplifying through gain, export the analog signal surplus of this grade level circuit module (20);
Grade surplus output of step 2.3 back
The analog signal surplus of level circuit module (20) is slightly quantized successively the analog signal surplus of each grade after obtaining by all grades circuit module (20) after this grade;
Step 2.4 back analog-to-digital conversion
By the analog signal surplus of afterbody level circuit module (20) output, carry out analog-to-digital conversion through analog-to-digital conversion module (30) later and obtain quantized result.
5. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 4 is characterized in that, described step 2.1 also comprises following steps:
Step 2.1.1 is one group of decision level for the simulate given signal of the given analog input port input of level circuit module (20), and the digital given signal of importing for its given digital input port is one group of given quantized result i, and wherein i increases progressively from 1 to N;
Step 2.1.2 is above-mentioned one group of decision level for the simulate given signal of the given analog input port input of level circuit module (20), and the digital given signal of importing for its given digital input port is one group of given quantized result i+1, and wherein i increases progressively from 1 to N.
6. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 4 is characterized in that, slightly quantizes at each grade level circuit module (20) in the described step 2.3, also comprises following steps:
The analog signal surplus of the given analog input port input upper level of step 2.3.1 level circuit module (20) obtains thick quantized result through analog-to-digital conversion;
Step 2.3.2 exports the thick quantification calibration result of corresponding this grade level circuit module (20) in the storage array by thick quantized result control, and is sent to given digital input port;
Step 2.3.3 slightly quantizes calibration result and obtains thick quantized analog signal through digital-to-analogue conversion, and sends to the negative input end of subtracter block (24);
The analog signal surplus of the upper level of the given analog input port input of step 2.3.4 sends to the positive input terminal of subtracter block (24) through level circuit sampling module (23);
Step 2.3.5 upper level analog signal surplus deducts thick quantized analog signal, after amplifying through gain, exports the analog signal surplus of this grade.
7. the quick calibration method of the capacitance mismatch of production line analog-digital converter as claimed in claim 5 is characterized in that, described step 2.4 also comprises following steps:
Step 2.4.1 is that level circuit module (20) input is at given signal described in the step 2.1.1, be that given analog input port is imported one group of decision level, given digital input port is imported one group of given quantized result i, wherein, i increases progressively from 1 to N, and the one group of quantized result that obtains by level circuit module (20) after this grade and back analog-to-digital conversion module (30) is first quantized result successively;
Step 2.4.2 is that level circuit module (20) input is at given signal described in the step 2.1.2, be that given analog input port is imported one group of decision level, for its given digital input port is imported one group of given quantized result i+1, wherein, i increases progressively from 1 to N, obtains one group of second quantized result by level circuit module (20) after this grade and back analog-to-digital conversion module (30) successively.
8. the quick calibration method of production line analog-digital converter as claimed in claim 6 and capacitance mismatch thereof is characterized in that, the thick quantification calibration result of described each grade level circuit module (20) output has kept some redundant digits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010022813 CN101777917B (en) | 2010-01-14 | 2010-01-14 | Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010022813 CN101777917B (en) | 2010-01-14 | 2010-01-14 | Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101777917A true CN101777917A (en) | 2010-07-14 |
| CN101777917B CN101777917B (en) | 2013-04-03 |
Family
ID=42514267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010022813 Active CN101777917B (en) | 2010-01-14 | 2010-01-14 | Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101777917B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075189A (en) * | 2011-02-16 | 2011-05-25 | 东南大学 | Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration |
| US8405537B2 (en) | 2011-08-11 | 2013-03-26 | Pixart Imaging Inc. | Systems, devices and methods for capacitor mismatch error averaging in pipeline analog-to-digital converters |
| US8441378B2 (en) | 2011-08-11 | 2013-05-14 | Pixart Imaging, Inc. | Capacitor mismatch error correction in pipeline analog-to-digital converters |
| CN103905041A (en) * | 2012-12-25 | 2014-07-02 | 北京中电华大电子设计有限责任公司 | Direct-current offset calibration method and circuit for pipelined analog-to-digital converters |
| CN104038220A (en) * | 2013-03-06 | 2014-09-10 | 西安电子科技大学 | 16-bit pipelined analog-digital converter |
| CN104254975A (en) * | 2012-02-14 | 2014-12-31 | 赫梯特微波公司 | Methods for calibrating pipeline analog-to-digital converters having multiple channels |
| CN104702284A (en) * | 2013-12-09 | 2015-06-10 | 株式会社东芝 | Analog-to-digital converter and image sensor |
| CN106230438A (en) * | 2016-08-04 | 2016-12-14 | 成都博思微科技有限公司 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
| CN103762982B (en) * | 2014-01-16 | 2017-02-01 | 东南大学 | Capacitance mismatch fast calibrating circuit of analog-digital converter and calibrating method |
| CN107846223A (en) * | 2012-04-20 | 2018-03-27 | 凌力尔特有限公司 | Analog-to-digital converter and method |
| CN108988859A (en) * | 2018-08-28 | 2018-12-11 | 电子科技大学 | Comparator imbalance voltage calibration method based on redundant digit |
| CN110176930A (en) * | 2019-05-29 | 2019-08-27 | 中国电子科技集团公司第二十四研究所 | Measure the multidigit resolution level pipeline organization of transmission curve jump height |
| CN110504967A (en) * | 2019-08-30 | 2019-11-26 | 电子科技大学 | A kind of interstage gain mismatch repair method of pipeline ADC |
| CN111147077A (en) * | 2018-11-05 | 2020-05-12 | 瑞昱半导体股份有限公司 | Gain calibration device and method for residual amplifier of analog-digital converter |
| CN111682877A (en) * | 2020-05-29 | 2020-09-18 | 成都华微电子科技有限公司 | Analog-to-digital conversion method of pipeline analog-to-digital converter and pipeline analog-to-digital converter |
| CN112600559A (en) * | 2020-12-02 | 2021-04-02 | 深圳市国微电子有限公司 | Pipeline analog-to-digital converter and transceiving chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
| CN101005283A (en) * | 2006-01-18 | 2007-07-25 | 马维尔国际贸易有限公司 | Pipelined analog-to-digital converters |
| CN101040441A (en) * | 2004-10-12 | 2007-09-19 | 索尼株式会社 | Sample hold circuit, and pipeline ad converter using the circuit |
| CN101222230A (en) * | 2008-01-24 | 2008-07-16 | 上海萌芯电子科技有限公司 | Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error |
-
2010
- 2010-01-14 CN CN 201010022813 patent/CN101777917B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1499730A (en) * | 2002-11-08 | 2004-05-26 | 尹登庆 | Pipeline structured A/D converter with high speed and high precision |
| CN101040441A (en) * | 2004-10-12 | 2007-09-19 | 索尼株式会社 | Sample hold circuit, and pipeline ad converter using the circuit |
| CN101005283A (en) * | 2006-01-18 | 2007-07-25 | 马维尔国际贸易有限公司 | Pipelined analog-to-digital converters |
| CN101222230A (en) * | 2008-01-24 | 2008-07-16 | 上海萌芯电子科技有限公司 | Assembly line type D/A convertor capable of calibrating capacitance mismatch and finite gain error |
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075189B (en) * | 2011-02-16 | 2014-12-17 | 东南大学 | Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration |
| CN102075189A (en) * | 2011-02-16 | 2011-05-25 | 东南大学 | Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration |
| US8405537B2 (en) | 2011-08-11 | 2013-03-26 | Pixart Imaging Inc. | Systems, devices and methods for capacitor mismatch error averaging in pipeline analog-to-digital converters |
| US8441378B2 (en) | 2011-08-11 | 2013-05-14 | Pixart Imaging, Inc. | Capacitor mismatch error correction in pipeline analog-to-digital converters |
| CN104254975B (en) * | 2012-02-14 | 2017-11-03 | 赫梯特微波有限责任公司 | Method and apparatus for calibrating the production line analog-digital converter with multiple passages |
| CN104254975A (en) * | 2012-02-14 | 2014-12-31 | 赫梯特微波公司 | Methods for calibrating pipeline analog-to-digital converters having multiple channels |
| CN107846223B (en) * | 2012-04-20 | 2021-12-03 | 亚德诺半导体国际无限责任公司 | Analog-to-digital converter system and method |
| CN107846223A (en) * | 2012-04-20 | 2018-03-27 | 凌力尔特有限公司 | Analog-to-digital converter and method |
| CN103905041A (en) * | 2012-12-25 | 2014-07-02 | 北京中电华大电子设计有限责任公司 | Direct-current offset calibration method and circuit for pipelined analog-to-digital converters |
| CN103905041B (en) * | 2012-12-25 | 2016-12-28 | 北京中电华大电子设计有限责任公司 | A kind of DC maladjustment calibration steps for production line analog-digital converter and circuit |
| CN104038220B (en) * | 2013-03-06 | 2017-12-22 | 西安电子科技大学 | A kind of 16 flow-line modulus converters |
| CN104038220A (en) * | 2013-03-06 | 2014-09-10 | 西安电子科技大学 | 16-bit pipelined analog-digital converter |
| CN104702284A (en) * | 2013-12-09 | 2015-06-10 | 株式会社东芝 | Analog-to-digital converter and image sensor |
| CN103762982B (en) * | 2014-01-16 | 2017-02-01 | 东南大学 | Capacitance mismatch fast calibrating circuit of analog-digital converter and calibrating method |
| CN106230438A (en) * | 2016-08-04 | 2016-12-14 | 成都博思微科技有限公司 | A kind of capacitance mismatch for production line analog-digital converter tests System and method for |
| CN108988859B (en) * | 2018-08-28 | 2021-09-07 | 电子科技大学 | Comparator offset voltage calibration method based on redundant bits |
| CN108988859A (en) * | 2018-08-28 | 2018-12-11 | 电子科技大学 | Comparator imbalance voltage calibration method based on redundant digit |
| CN111147077B (en) * | 2018-11-05 | 2023-08-11 | 瑞昱半导体股份有限公司 | Gain calibration device and method for residual amplifier of analog-digital converter |
| CN111147077A (en) * | 2018-11-05 | 2020-05-12 | 瑞昱半导体股份有限公司 | Gain calibration device and method for residual amplifier of analog-digital converter |
| CN110176930A (en) * | 2019-05-29 | 2019-08-27 | 中国电子科技集团公司第二十四研究所 | Measure the multidigit resolution level pipeline organization of transmission curve jump height |
| CN110176930B (en) * | 2019-05-29 | 2021-08-31 | 中国电子科技集团公司第二十四研究所 | Multi-position resolution sub-pipeline structure for measuring jump height of transmission curve |
| CN110504967B (en) * | 2019-08-30 | 2022-04-22 | 电子科技大学 | Interstage gain mismatch correction method of pipeline ADC (analog to digital converter) |
| CN110504967A (en) * | 2019-08-30 | 2019-11-26 | 电子科技大学 | A kind of interstage gain mismatch repair method of pipeline ADC |
| CN111682877A (en) * | 2020-05-29 | 2020-09-18 | 成都华微电子科技有限公司 | Analog-to-digital conversion method of pipeline analog-to-digital converter and pipeline analog-to-digital converter |
| CN111682877B (en) * | 2020-05-29 | 2023-04-28 | 成都华微电子科技股份有限公司 | Analog-to-digital conversion method of pipeline analog-to-digital converter and pipeline analog-to-digital converter |
| CN112600559A (en) * | 2020-12-02 | 2021-04-02 | 深圳市国微电子有限公司 | Pipeline analog-to-digital converter and transceiving chip |
| CN112600559B (en) * | 2020-12-02 | 2024-03-19 | 深圳市国微电子有限公司 | Pipelined analog-to-digital converter and transceiver chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101777917B (en) | 2013-04-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101777917B (en) | Pipeline analog-to-digital converter and quick calibration method of capacitance mismatch thereof | |
| US9954549B2 (en) | Charge-sharing and charge-redistribution DAC and method for successive approximation analog-to-digital converters | |
| CN109120268B (en) | Dynamic comparator offset voltage calibration method | |
| CN102045067B (en) | Conversion and calibration algorithm for improving output signal-to-noise ratio of successive approximation (SAR) analog-to-digital converter (ADC) and ADC | |
| CN102075189B (en) | Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration | |
| US10135457B2 (en) | Successive approximation register analog-digital converter having a split-capacitor based digital-analog converter | |
| CN103580695B (en) | Predictive successive approximation type analog-digital conversion device and method thereof | |
| EP3567720B1 (en) | Mismatch and reference common-mode offset insensitive single-ended switched capacitor gain stage | |
| CN102751990A (en) | Pipelined analog-to-digital converter capable of improving dynamic performance | |
| CN107579740B (en) | Method for improving output precision of pipeline analog-to-digital converter and analog-to-digital converter | |
| CN109462402B (en) | Mixed type assembly line ADC structure | |
| CN102723951B (en) | Pipelined ADC (Analog-to-Digital Converter) digital background correcting circuit with translation technology | |
| CN111740742A (en) | High-speed and high-precision image signal analog-to-digital conversion circuit | |
| CN112290945B (en) | Digital background self-calibration circuit structure and method of single-channel high-speed high-precision SAR ADC | |
| US8576106B2 (en) | Analog-digital converter | |
| CN201590812U (en) | Cascade circuit device for pipeline analog-to-digital converter | |
| US10454491B1 (en) | Successive approximation register (SAR) analog to digital converter (ADC) with partial loop-unrolling | |
| US20220021396A1 (en) | Signal converting apparatus and related method | |
| CN107786206A (en) | Pipeline SAR-ADC system | |
| CN207410329U (en) | Pipeline SAR-ADC device | |
| US10541698B1 (en) | Switched capacitor multiplying digital-to-analog converter | |
| CN102790619B (en) | Switch capacitor circuit and pipeline system analog-to-digital converter | |
| CN102811060B (en) | Production line analog-digital converter, video system and wireless system | |
| Wu et al. | A Digital Background Calibration Algorithm of Pipelined ADC Based on Pesudo-Random Sequence | |
| CN114696834B (en) | Successive approximation type analog-to-digital converter, test equipment and capacitance weighted value calibration method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |