CN101040441A - Sample hold circuit, and pipeline ad converter using the circuit - Google Patents

Abstract

A switched capacitor sample hold circuit using a source-earthed input operation amplifier. This operation circuit is provided with a feed forward circuit or a feedback circuit, which is connected with a feedback capacitor of the operation amplifier through a switch. An input common voltage or the middle point voltage of an output is detected to precharge the feedback capacitor beforehand with the difference from a reference voltage thereby to suppress fluctuations in an output operation point at the time of amplifying the operation amplifier.

Description

Sampling hold circuit and the production line analog-digital converter that uses this circuit

Technical field

The present invention relates to streamline modulus (AD) transducer that uses the sampling hold circuit of switched capacitor (switched capacitor) and use it.

Background technology

Fig. 1 has shown the basic S/H that uses traditionally (sampling and maintenance) circuit 10.Constitute S/H circuit 10 by operational amplifier 11, switch SW 11, SW12, SW13, SW14, SW15, SW16, SW17, SW18, SW19 and SW20 and by the switched capacitor that capacitor C S10, CS11, Cf10 and Cf11 form.

Vag is connected to the side of capacitor CS10 via switch SW 13, and Vip is connected to the side of capacitor CS10 via SW11.And the other end is connected to the first input end of operational amplifier 11.

In addition, Vin is connected to the side of capacitor CS11 via SW12, and Vag is connected to the side of capacitor CS11 via SW14.The other end is connected to second input of operational amplifier 11.

First output of operational amplifier 11 is connected to first input end via SW16, and SW17 that is connected in series and capacitor Cf10 are parallel to first input end and output.

Second output of operational amplifier 11 is connected to second input via SW20, and SW19 that is connected in series and capacitor Cf11 are parallel to second input and output.

Here, control the on/off of SW11, SW12, SW15, SW16, SW18 and SW20, and control the on/off of SW13, SW14, SW17 and SW19 by clock signal 2 (CK2) by clock signal 1 (CK1).

Explain the operation of S/H circuit 10 by the operation timing waveform that uses Fig. 2.By 2 phase non-overlapping clock signals shown in Figure 2 (CK1, the CK2) on/off of control switch, and by (sampling) pattern and two these switches of stages operating of amplification (maintenance) pattern of resetting.

Shown in Fig. 2 A and Fig. 2 B, in the replacement pattern, when CK1 being arranged on " H " level, when CK2 being arranged on " L " level, SW11, SW12, SW15, SW16, SW18 and SW20 become connection (short circuit), and SW13, SW14, SW17 and SW19 become off-state (open circuit).

As a result, the first input end of operational amplifier 11 and output and second input and output be by short circuit, and operational amplifier 11 is biased to the operating point (Vag) with highest-gain.

In addition, (Vip Vin) is charged to sampling capacitor CS and is used for Vag with input voltage.Charge into sampling capacitor CS (CS10, CS11) and feedback condenser Cf (Cf10, quantity of electric charge Cf11) (only paying close attention to the variation of a side) becomes following equation:

Qcs＝CS(Vip-Vag) (1)

Qcf＝0 (2)

On the other hand, in amplification mode, in Fig. 2 A and Fig. 2 B, CK1 becomes " L " level, and CK2 becomes " H " level.As a result, SW11, SW12, SW15, SW16, SW18 and SW20 disconnect, and SW13, SW14, SW17 and SW19 connect (short circuit).As a result, operational amplifier 11 becomes capacitive feedback type amplifier.

At the input side of operational amplifier 11, SW13 and SW14 connect, and the switch of input is switched to Vag (terminal), and charge into sampling capacitor CS (CS10, CS11) and feedback condenser Cf (Cf10, quantity of electric charge Cf11) becomes following equation:

Qcs＝0 (3)

Qcf＝Cf(Von-Vag) (4)

Overall charge amount in replacement pattern and amplification mode is constant, and therefore, output voltage V on becomes:

Von＝(CS/Cf)*(Vip-Vag)+Vag (5)

And use Vag to multiply each other with the difference and the permittivity of output as a reference with input voltage.

In many cases, source-coupled is as shown in Figure 3 imported high gain operational amplifier (source-coupled pair transistors input high gain operational amplifier) to transistor and is used for such switching capacity type operational amplifier.Because it be desirable differential-type, therefore, general practice is the middle point voltage that detects output signal, and applies commonality schemata and feed back (CMFB) and obtain desirable output function point Vag.

On the other hand, along with the up-to-date reduction of voltage, be difficult to vertically pile up as shown in Figure 3 a plurality of transistors.

As shown in Figure 3, the source electrode of PMOS transistor Q51 is connected to voltage source V DD, and its drain electrode is connected to the source electrode of PMOS transistor Q52.In addition, the grid of PMOS transistor Q51 is connected to bias voltage (Bias3).The drain electrode of PMOS transistor Q52 is connected to the drain electrode of nmos pass transistor Q53, and its grid is connected to bias voltage (Bias2).The source electrode of nmos pass transistor Q53 is connected to the drain electrode of nmos pass transistor Q54, and its grid is connected to bias voltage (Biasl).The grid of nmos pass transistor Q54 is connected to Vin, and its source electrode is connected to the source electrode of nmos pass transistor Q58 publicly and is connected to the drain electrode of the nmos pass transistor Q59 that forms current source, and the source ground of nmos pass transistor Q59.

The source electrode of PMOS transistor Q55 is connected to voltage source V DD, and its drain electrode is connected to the source electrode of PMOS transistor Q56.In addition, the grid of PMOS transistor Q55 is connected to bias voltage (Bias3).The drain electrode of PMOS transistor Q56 is connected to the drain electrode of nmos pass transistor Q57, and its grid is connected to bias voltage (Bias2).The source electrode of nmos pass transistor Q57 is connected to the drain electrode of nmos pass transistor Q58, and its grid is connected to bias voltage (Biasl).The grid of nmos pass transistor Q58 is connected to Vip, and its source electrode is connected to the source electrode of nmos pass transistor Q54 publicly.

The drain electrode of nmos pass transistor Q53 and nmos pass transistor Q57 is connected to CMFB (commonality schemata feedback) circuit 51, and is connected to output Vop and Von.

In addition, the output of CMFB circuit 51 is connected to the grid of the current source of nmos pass transistor Q59, and the Control current amount.

As mentioned above, the source-coupled of operational amplifier 50 with the MOS transistor that contains vertical stacking disposes transistorized input.It has its output resistance can be done very big advantage, but but sacrificed the dynamic range of the output of operational amplifier 50.For this reason, have the situation that adopts folded configuration, but this has the inefficient defective of overall electric current.

In contrast, in Fig. 4, shown the example of circuit arrangement of sampling hold circuit 100 of suitable reduction voltage that has the operational amplifier of source ground type input stage by employing.

The side of current source I100 is connected to voltage source V DD, and opposite side is connected to the drain electrode of nmos pass transistor Q100.The source ground of nmos pass transistor Q100 connects SW106 between grid and drain electrode, and the SW107 and the capacitor Cf100 of series connection is in parallel with it.The points of common connection of these capacitors Cf100 and SW107 is connected to Vag via SW105.

In addition, the side of current source I101 is connected to voltage source V DD, and the drain electrode of nmos pass transistor Q101 is connected to opposite side.The source ground of nmos pass transistor Q101, SW108 are connected between grid and the drain electrode, and the SW109 and the capacitor Cf101 that are connected in series is in parallel with it.The points of common connection of these capacitors Cf101 and SW109 is connected to Vag via SW110.

The grid of nmos pass transistor Q100 is connected to capacitor CS100, also is connected to Vip via SW101, and is connected to Vag via SW103.

The grid of nmos pass transistor Q101 is connected to capacitor CS101, also is connected to Vin via SW102, and is connected to Vag via SW104.

As mentioned above, (Q100, Q101), they move with the pseudo-differential form to use two source ground amplifiers.The input stage of not setovering on current source is to transistor, it is hereby ensured a transistor output than great dynamic range.In addition, by (I100 I101) setovers to determine the output function point from load-side, does not therefore need the CMFB circuit in the conventional operational amplifier by current source.

Yet, in the above operational amplifier that uses the ground connection source electrode, determine gm (transistor conductivity) by frequency, therefore can not expect further to reduce power consumption.In addition, the electrical characteristics with operational amplifier of ground connection source electrode change with the fluctuation of common electric voltage of input.In addition, amplify the undulate quantity of common electric voltage in the mode identical with the differential signal component.For this reason, the defective that exists the operation on the output point to fluctuate from primitive operation point, and this has dwindled the dynamic range of output.

Patent file 1: the open HEI:No.5-14199 of Japan Patent

Patent file 2: the open No.2000-201054 of Japan Patent

Non-patent file 1:Daisuke Miyazaki et al., " A 10-b 30-MS/s LOW-POWERPipelined CMOS A/D Converter Using a Pseudo Differential Architecture ", IEEEJOURNAL OF SOLID-STATE CIRCUIT, VOL.38, No.2, pp.370-373, FEBUARY 2003.

Summary of the invention

The technical problem to be solved in the present invention

Consider that above problem makes the present invention, it can reduce the power consumption of ground connection source electrode operational amplifier, and the sampling hold circuit of the operational amplifier that adopts the source ground input transistors with the public fluctuation of opposing input and the AD converter of using this circuit are provided.

The device that is used to deal with problems

The present invention has: first switch is provided with first reference signal and operates on/off by first control signal; Second switch is provided with first input signal and operates on/off by second control signal; The 3rd switch is provided with second reference signal and operates on/off by described first control signal; The 4th switch is provided with second input signal and operates on/off by described second control signal; First capacitor alternately provides signal to it in response to described first and second control signals from described first and second switches; Second capacitor alternately provides signal to it in response to described first and second control signals from described third and fourth switch; First amplifier, it makes the output of described first and second capacitors be connected to first and second inputs, amplifies described output, and it is exported from first and second outputs; The 5th switch and the 3rd capacitor are connected between the described first input end and first output; The 6th switch and the 4th capacitor are connected between described second input and second output; Be connected first and second outputs of described first amplifier and first and second variable current sources between the reference power source; With the operation setting circuit, be provided with described second control signal and during second control signal is provided, fix the mode of operation of described amplifier.

Alternatively, the present invention has: the 5th and the 6th switch first, second, third, fourth,, it is equated by sample frequency and first and second clock signals of non-overlapping copies are controlled, and become on-state on the time point when described first clock is connected, seven, the 8 9th and the tenth switch becomes on-state when described second clock is connected; Operational amplifier; Be used for that negative feedback is applied to the capacitor of operational amplifier and be used for via the described the 3rd or the capacitor of the 4th switch sampled input signal, wherein said first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, when connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output, dispose described operational amplifier by 2 groups of source ground input stages and 2 groups of current sources, to be inserted in each level by the switch that described second clock becomes on-state, and with described second clock synchronously with the bias current value of input transistors and grid width size with (n+1) multiply each other [n＞0, integer].

Alternatively, the present invention has: first switch is provided with first reference signal and operates on/off by first control signal; Second switch is provided with first input signal and operates on/off by second control signal; The 3rd switch is provided with second reference signal and operates on/off by described first control signal; The 4th switch is provided with second reference signal and operates on/off by described second control signal; First capacitor of first output signal alternately is provided to it from described first and second switches in response to described first and second control signals; Second capacitor of described second output signal alternately is provided to it from described third and fourth switch in response to described first and second control signals; First amplifier, it makes the output of described first and second capacitors be connected to first and second inputs, amplifies described output, and it is exported from first and second outputs; The 5th switch and the 3rd capacitor are connected between the described first input end and first output; The 6th switch and the 4th capacitor are connected between described second input and second output; Correcting circuit provides described first and second input signals and the 3rd reference signal to it, and is used to proofread and correct the correction signal of the operation of described first amplifier to the output of described third and fourth capacitor in response to described second control signal; With the operation setting circuit, be provided with described second control signal and during second control signal is provided, fix the mode of operation of described amplifier.

Alternatively, the present invention has: the 5th and the 6th switch first, second, third, fourth,, equate also first and second clock signals control of non-overlapping copies by sample frequency, when connecting, described first clock becomes on-state, and the 7th, the 8 9th and the tenth switch becomes on-state when described second clock is connected; Operational amplifier has the source ground amplifier as input stage; Be used for negative feedback is applied to the electric capacity of operational amplifier; And sampling capacitor, be used for via the described the 3rd or the 4th switch sampled input signal, wherein said first and second switch in parallel are to the capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, when connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and, and provide according to described reference voltage described input signal and correction voltage are connected to the described the 5th and the feed forward circuit of the 6th switch its output.

Alternatively, the present invention has: first switch is provided with first reference signal and operates on/off by first control signal; Second switch is provided with first input signal and operates on/off by second control signal; The 3rd switch is provided with second reference signal and operates on/off by described first control signal; The 4th switch is provided with second reference signal and operates on/off by described second control signal; First capacitor alternately provides signal to it in response to described first and second control signals from described first and second switches; Second capacitor alternately provides signal to it in response to described first and second control signals from described third and fourth switch; Amplifier, it makes the output of described first and second capacitors be connected to first and second inputs, amplifies described output, and it is exported from first and second outputs; The 5th switch and the 3rd capacitor are connected between the described first input end and first output; The 6th switch and the 4th capacitor are connected between described second input and second output; Correcting circuit provides described first and second input signals and the 3rd reference signal to it, and is used to proofread and correct the correction signal of the operation of described first amplifier to the output of described third and fourth capacitor in response to described second control signal; With the operation setting circuit, be provided with described second control signal and during second control signal is provided, fix the mode of operation of described amplifier.

Alternatively, the present invention is a sampling hold circuit, comprise: the 5th and the 6th switch first, second, third, fourth,, equate also first and second clock signals control of non-overlapping copies by sample frequency, when connecting, described first clock becomes on-state, and the 7th, the 8 9th and the tenth switch becomes on-state when described second clock is connected; Operational amplifier has the source ground amplifier as input stage; Be used for negative feedback is applied to the electric capacity of operational amplifier; And sampling capacitor, be used for via the described the 3rd or the 4th switch sampled input signal, wherein said first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in described sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, when connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, and the difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and, and provide according to described reference voltage the public output of described sampling hold circuit and correction voltage are connected to the described the 5th and the feed forward circuit of the 6th switch its output.

The present invention is the assembly line A/D converter cascade, it connects a plurality of AD and changes sub-piece, each sub-piece by be used for analog signal conversion be digital code AD converter, be used for digital code with AD converter output and be converted to the DA transducer of the analogue value and be used for and will be applied to analog signal that described AD is converted to and multiply by 2 from the difference between the analog signal of described DA transducer output ^(a-1)[resolution of a:AD transducer] and with the sampling hold circuit of its output, wherein said sampling hold circuit has: the 5th and the 6th switch first, second, third, fourth,, it is equated by sample frequency and first and second clock signals of non-overlapping copies are controlled, and become on-state on the time point when described first clock is connected, seven, the 8 9th and the tenth switch becomes on-state when described second clock is connected; Operational amplifier; Be used for via the described the 3rd or the capacitor of the 4th switch sampled input signal, wherein said first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, when connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output, dispose described operational amplifier by 2 groups of source ground input stages and 2 groups of current sources, to be inserted in each level by the switch that described second clock becomes on-state, and with described second clock synchronously with the bias current value of input transistors and grid width size with (n+1) multiply each other [n＞0, integer].

The present invention is the assembly line A/D converter cascade, it connects a plurality of AD and changes sub-piece, each sub-piece by be used for analog signal conversion be digital code AD converter, be used for digital code with AD converter output and be converted to the DA transducer of the analogue value and be used for and will be applied to analog signal that described AD is converted to and multiply by 2 from the difference between the analog signal of described DA transducer output ^(a-1)[resolution of a:AD transducer] and with the sampling hold circuit of its output, wherein said sampling hold circuit has: the 5th and the 6th switch first, second, third, fourth,, equate also first and second clock signals control of non-overlapping copies by sample frequency, when connecting, described first clock becomes on-state, and the 7th, the 8 9th and the tenth switch becomes on-state when described second clock is connected; Operational amplifier has the source ground amplifier as input stage; Be used for negative feedback is applied to the electric capacity of operational amplifier; And sampling capacitor, be used for via the described the 3rd or the 4th switch sampled input signal, wherein said first and second switch in parallel are to the capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, when connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output, to be used to detect poor between the common electric voltage of described input signal and the described reference voltage, the output of circuit of simultaneously difference voltage being amplified so much times of the ratio of described sampling capacitance and feedback capacity is connected to the described the 5th and the 6th switch, and the polarity of this circuit is opposite with the polarity of described operational amplifier.

The present invention is the assembly line A/D converter cascade, it connects a plurality of AD and changes sub-piece, each sub-piece by be used for analog signal conversion be digital code AD converter, be used for digital code with AD converter output and be converted to the DA transducer of the analogue value and be used for and will be applied to analog signal that described AD is converted to and multiply by 2 from the difference between the analog signal of described DA transducer output ^(a-1)[resolution of a:AD transducer] and with the sampling hold circuit of its output, wherein said sampling hold circuit has: the 5th and the 6th switch first, second, third, fourth,, equate also first and second clock signals control of non-overlapping copies by sample frequency, when connecting, described first clock becomes on-state, and the 7th, the 8 9th and the tenth switch becomes on-state when described second clock is connected; Operational amplifier has the source ground amplifier as input stage; Be used for negative feedback is applied to the electric capacity of operational amplifier; And sampling capacitor, be used for via the described the 3rd or the 4th switch sampled input signal, wherein said first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in described sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, when connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, and the difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output, to be used to detect poor between the common electric voltage of described input signal and the described reference voltage, the output of circuit of simultaneously difference voltage being amplified so much times of the ratio of described sampling capacitance and feedback capacity is connected to the described the 5th and the 6th switch, and the polarity of this circuit is opposite with the polarity of described operational amplifier.

Effect of the present invention

Sampling hold circuit of the present invention uses transistorized size by using switch according to the current source and the amplification of operator scheme switched amplifier, and makes operating current variable, makes and can reduce the operation average current.

In addition, by in assembly line A/D converter, using this sampling hold circuit, can reduce power consumption.

Sampling of the present invention and holding current increase out-put dynamic range, can suppress to import the commonality schemata fluctuation by feed forward circuit is provided in addition in amplifier.

In addition, by in assembly line A/D converter, using this sampling hold circuit, can implement to resist the stable conversion operations of commonality schemata fluctuation.

The present invention gets sampling hold circuit can suppress to import the commonality schemata fluctuation by feedback circuit is provided in amplifier.

In addition, by amplifier being configured to the source ground type, can increase out-put dynamic range.

In addition, by in assembly line A/D converter, using this sampling hold circuit, can implement to resist the stable conversion operations of commonality schemata fluctuation.

Description of drawings

Fig. 1 is the circuit diagram that shows the sampling hold circuit of conventional example.

Fig. 2 is the operation timing figure that is used to explain the operation of sampling hold circuit shown in Figure 1.

Fig. 3 is the circuit diagram that is presented at the circuit arrangement of the amplifier that uses in the sampling hold circuit shown in Figure 1.

Fig. 4 is the circuit diagram of configuration that shows another sampling hold circuit of conventional example.

Fig. 5 is the overall block-diagram that shows the configuration of sampling hold circuit of the present invention.

Fig. 6 is the operation timing figure that is used for key-drawing 5 described sampling hold circuits.

Fig. 7 is the overall block-diagram that shows the configuration of sampling hold circuit of the present invention.

Fig. 8 is the circuit diagram that shows the feed forward circuit configuration that forms in commonality schemata and/or the sampling hold circuit shown in Figure 7.

Fig. 9 is the operation timing figure that is used to explain the operation of sampling hold circuit shown in Figure 8.

Figure 10 is the overall block-diagram that shows the configuration of sampling hold circuit of the present invention.

Figure 11 is the circuit diagram that shows the feed forward circuit configuration that forms in commonality schemata and/or the sampling hold circuit shown in Figure 10.

Figure 12 is the overall block-diagram of the configuration of display pipeline AD converter.

Figure 13 is the circuit diagram that is presented at the configuration of the MDAC circuit that uses in the assembly line A/D converter shown in Figure 12.

Figure 14 is the circuit diagram that is presented at the configuration of another MDAC circuit that uses in the assembly line A/D converter shown in Figure 12.

Figure 15 is the circuit diagram that is presented at the configuration of another MDAC circuit that uses in the assembly line A/D converter shown in Figure 12.

Description of reference numerals

10,100,150,200,300,414,421 ... S/H (sampling and maintenance) circuit, 11 ... amplifier, 50,251,351 ... operational amplifier (amplifier), 51,302,350 ... CMFB (commonality schemata feedback) circuit, 202,250 ... CMFF (commonality schemata feedforward) circuit, 400 ... assembly line A/D converter, 402A to 402N, 403A to 403N ... input circuit, 410,422A is to 422D ... MDAC (multiplication DAC), 411 ... AD converter (ADC), 412 ... DA transducer (DAC), 413 ... subtracter and 423 ... error correction/clock generation circuit.

Embodiment

(embodiment 1)

In Fig. 5, show according to sampling hold circuit 50 of the present invention.

The side of current source I151 is connected to voltage source V DD, and opposite side is connected to the drain electrode of nmos pass transistor Q151, and current source I153 and the switch SW 163 that is connected in series is parallel to current source I151.Current source I153 is the current source that is used to flow through the n times of electric current of current source I151.The source ground of nmos pass transistor Q151 connects SW156 between grid and drain electrode.The SW157 and the capacitor Cf151 that are connected in series are parallel to it.Via SW155 the points of common connection of these capacitors Cf151 and SW157 is connected to Vag.

Provide source ground type nmos pass transistor Q153 in parallel with the nmos pass transistor Q151 of configuration pseudo-differential circuit, its grid is connected to the grid of Q151 publicly, and drain electrode is connected to the drain electrode of Q151 via SW161.

In addition, the side of current source I152 is connected to voltage source V DD, and opposite side is connected to the drain electrode of nmos pass transistor Q152.In addition, I152 is arranged side by side with current source, and current source I154 and SW164 are connected in series.Current source I154 is the current source that is used for by the n times of electric current of current source I152.

The source ground of nmos pass transistor Q152, SW158 are connected between grid and the drain electrode, and the SW159 and the capacitor Cf152 that are connected in series is in parallel with it.The points of common connection of these capacitors Cf152 and SW159 is connected to Vag via SW160.

In addition, dispose nmos pass transistor Q154 in the mode identical with nmos pass transistor Q153.Just, provide source ground type nmos pass transistor Q154 in parallel with nmos pass transistor Q152, its grid is commonly connected to the grid of Q152, and drain electrode is connected to the drain electrode of Q152 via SW162.

Here, be set at the grid width of nmos pass transistor Q153 and Q154 nmos pass transistor Q151 and Q152 grid width n doubly, and the drain current that flows through in nmos pass transistor Q151 and Q152 is under the situation of I0, drain current n*I0 flows through.

The grid of nmos pass transistor Q151 and Q153 is connected to capacitor CS151, further is connected to Vip via SW151, and is connected to Vag via SW153.

The grid of nmos pass transistor Q152 and Q154 is connected to capacitor CS152, further is connected to Vin via SW152, and is connected to Vag via SW154.

Then, the drain electrode of nmos pass transistor Q151 and Q152 is connected to output Von and Vop.

Next, by using timing waveform shown in Figure 6 to explain the basic operation of sampling hold circuit of the present invention 150 shown in Figure 5.

In Fig. 6 A, at the replacement mode time, CK1 becomes " H " level, and the CK2 of Fig. 6 B becomes " L " level.About the switch of this moment, SW151, SW152, SW155, SW156, SW158 and SW160 are in on-state, and SW153, SW154, SW157, SW159, SW161, SW162, SW163 and SW164 are in off-state.

SW163 and SW164 become disconnection, so the current source of nmos pass transistor Q151 and Q152 is I151 and the I152 with current value I 0.These flow to ground as drain current via source electrode.

In addition, SW161 and SW162 become disconnection, therefore, as mentioned above, nmos pass transistor Q151 and Q152 operation are only arranged.

The grid and the drain electrode of short circuit nmos pass transistor Q151 and 152 I/O end are so this transistor is as the MOS diode operation.

SW157 and SW159 become disconnection, therefore Vag voltage are provided to feedback condenser Cf151 and Cf152 and these capacitors of precharge.

At the input side of operational amplifier, SW151 and SW152 are in on-state, and by short circuit, therefore, Vip are provided to input capacitor CS151, and charge about the Vgs of nmos pass transistor Q151 (MOS diode).

On the other hand, Vin is provided to input capacitance CS152, and charges into nmos pass transistor Q152 (MOS diode) via SW152.

By this way, this circuit diverter switch when being in the replacement pattern at sampling hold circuit reduces the magnitude of current, simultaneously transistorized size (grid width) be multiply by 1/ (n+1) current density is always equated.

This is because ought only change current value, but when not changing transistorized size, the amplitude of the voltage Vgs between grid and the source electrode changes, and is equivalent to the variation of the common electric voltage of input thereupon.As a result, owing to amplify this change amount in the input stage of source ground type amplifier, therefore the problem of output function point drift appears.

In order to prevent this problem, in configuration of the present invention, provide switch, and make transistorized variable size, make constant current density when switchable current source.

Next, the timing of amplification mode will be explained.In Fig. 6 A, CK1 is in " L " level, and in Fig. 6 B, CK2 is in " H " level.

At this moment, SW151, SW152, SW155, SW156, SW158 and SW160 disconnect, and SW153, SW154, SW157, SW159, SW161, SW162, SW163 and SW164 connect.

SW163 becomes connection, so current source becomes overall (1+n) * I0 of Q151 and I153.This electric current stream is in source ground nmos pass transistor Q151 and Q153.In addition, SW164 also becomes connection, so the drain current of current source (overall (1+n) * I0 of I152 and I154) stream is in nmos pass transistor Q152 and Q154.

About DC, the grid of the I/O end of nmos pass transistor Q151 and Q153 and Q152 and Q154 and drain electrode become open circuit (open), and transistor becomes amplifier from diode thus.

Provide Vag via SW153 to input capacitor CS151.Then, feedback condenser Cf151 storage with by will gain (CS151/Cf151) and input voltage vin to the voltage difference of Vag the multiply each other voltage of acquisition and the corresponding electric charge of electric charge that in Cf151, charges in advance.

In an identical manner, via SW154 Vag is provided to input capacitor CS152.Feedback condenser Cf152 storage with by will gain (CS152/Cf152) and input voltage vin to the voltage difference of Vag the multiply each other voltage of acquisition and the corresponding electric charge of electric charge that in Cf152, charges in advance.

As mentioned above, when amplification mode, compare during with the replacement pattern, the operating current of current source be multiply by (1+n), transistorized then size multiply by (1+n) thereupon, therefore can realize high speed operation, and this moment grid and source electrode between Vgs can keep constant, so can prevent the fluctuation of the same phase voltage corresponding with the commonality schemata of input side.

In addition, by in the replacement pattern, producing operating current I0, in amplification mode, I0 be multiply by (1+n), and obtain efficient operation, can reduce the average operation electric current according to operator scheme switch current value.

The example that has shown the sampling hold circuit 150 of the foregoing description that uses nmos pass transistor.Except this example, can also be by this circuit of PMOS transistor arrangement, and can be configured by the FET that uses insulated gate electrode.

(embodiment 2)

Next, in Fig. 7, show sampling hold circuit 200 as another embodiment of the present invention.Here with the element of identical comment token indication with the identical configuration of element of Fig. 5.In addition, this sampling hold circuit 200 has the configuration that the circuit that forms by a part of commonality schemata feedforward (CNFF) circuit being added to by deletion Fig. 5 obtains.

Below, in order to simplify circuit arrangement and explanation thereof, only show a MOS transistor as the source ground transistor, but can be by using switch other MOS transistor in parallel, and can in corresponding with it constant current source, provide switch (SW) and current source in parallel.

The input of CMFF circuit 202 is connected to Vip and Vin, and is connected to Vag.The output of CMFF circuit 202 is connected to the points of common connection of capacitor Cf151 and SW157 and the points of common connection of capacitor Cf152 and SW159 via SW155 and SW160.Other circuit arrangement is identical with the sampling hold circuit 150 of Fig. 5, so the descriptions thereof are omitted here.

Next by using timing waveform shown in Figure 6 to explain the basic operation of sampling hold circuit shown in Figure 7 200.

In Fig. 6 A, in the replacement pattern, CK1 becomes " H " level, and the CK2 of Fig. 6 B becomes " L " level.About the switch of this moment, SW151, SW152, SW155, SW156, SW158 and SW160 are in on-state, and SW153, SW154, SW157 and SW159 are in off-state.

The grid of the I/O end of nmos pass transistor Q151 and Q152 and drain electrode are by short circuit as a result.

SW151 and SW152 connect and by short circuit, therefore Vip and Vin are provided to input capacitor CS151 and CS152 and are recharged.On the other hand, also these Vin and Vip are provided to CMFF circuit 202.CMFF circuit 202 has the difference that detects between voltage Vag and the input common electric voltage (Vcmn=(Vin+Vip)/2), and this difference voltage is amplified to the gain (function of multiple CS151/Cf151), of sampling hold circuit here.The VCMMD of the correction signal that will produce in CMFF circuit 202 is applied to the points of common connection of Cf151 and SW157 and the points of common connection of Cf152 and SW159 via SW155 and SW160.

Under the situation of replacement pattern, SW157 and SW159 become and end, and therefore, in feedback condenser Cf151, VCMMD is filled into the Vgs of nmos pass transistor Q151.In feedback condenser Cf152, VCMMD is filled into the Vgs of nmos pass transistor Q152.

In addition, Vip is provided to input capacitor CS151 via SW151, and about the Vgs of nmos pass transistor Q151 charging input capacitor CS151.

On the other hand, Vin is provided to input transistors CS152 via SW152, and in the Vgs of MOS transistor Q152 charging input capacitor CS152.

By this way, when sampling hold circuit was in the replacement pattern, this circuit filled into feedback condenser Cf151 and Cf152 via switch (SW) 155 and switch (SW) 160 in advance in advance with its correction voltage VCMMD.

Next, will explain amplification mode.In Fig. 6 A, CK1 is in " L " level, and in Fig. 6 B, CK2 is in " H " level.

At this moment, SW shows the mode of operation opposite with the mode time of resetting.As a result, the I/O end of nmos pass transistor Q151 and Q152 and grid and drain electrode become disconnection about DC, and operation becomes magnifying state.

By switching the switch of input, the variable quantity from Vip and Vin to Vag is sent to nmos pass transistor Q151 and Q152 via input capacitor CS151 and CS152.Variable quantity be multiply by CS151/Cf151 (or CS152/Cf152) and output Vop and Von.At this moment, as previously mentioned, in Cf151 and Cf152, therefore precharge VCMMD adds this calibration power supply to output voltage source in advance.

For example, suppose in the input common point, to occur fluctuation Δ V, the output function point fluctuation-Δ V (Cs/Cf) of sampling hold circuit in amplification mode.In contrast, by producing in Δ V (Cs/Cf) and the replacement pattern at sampling hold circuit at CMFF circuit 202 it is pre-charged to feedback condenser in advance, undulate quantity is cancelled out each other in amplification mode, and therefore, the operating point of operational amplifier will not change.

As the sampling hold circuit 200 of above embodiment, shown the example that uses nmos pass transistor, but except these, can be by this circuit of PMOS transistor arrangement, and can be configured by other insulated gate field-effect pipe.

(embodiment 3)

Fig. 8 shows the CMFF circuit 250 of present embodiment.CMFF circuit 250 is corresponding to the CMFF circuit 202 of configuration in the sampling hold circuit of explaining before 200.In Fig. 9, show the timing that is used to explain its operation.Be provided to of the inversion clock operation of the clock signal (CK3, CK4) of CMFF circuit 250 (202) as the control clock signal (CK1, CK2) of sampling hold circuit 200.

In Fig. 8, the input that is provided with Vin is connected to the end of SW251, and the other end of SW251 is connected to capacitor CS250.In addition, the points of common connection of this SW251 and capacitor CS250 is connected to Vag via SW253.

The input that is provided with Vip is connected to the end of SW252, and the other end of SW252 is connected to capacitor CS251.In addition, the points of common connection of this SW252 and capacitor CS251 is connected to Vag via SW254.

The other end of capacitor CS250 and CS251 is connected publicly, and is connected to an input of operational amplifier 251.Another input of this operational amplifier 251 is connected to Vag.SW256 is connected between the output and input of operational amplifier 251, and further that capacitor connected in series Cf250 and SW255 is in parallel with SW256.The points of common connection of capacitor Cf250 and SW255 is connected to Vag via SW257.

When the CMFF circuit was in the replacement pattern, sampling hold circuit 200 shown in Figure 7 was in amplification mode, and the CK2 of Fig. 9 is in " H " level.In Fig. 9 D, show its relation at Fig. 9 A.In Fig. 9 C and Fig. 9 D, when CK3 was in " H " level, CK4 became " L " level, so SW253, SW254, SW256 and SW257 become connection, and SW251, SW252 and SW255 become disconnection.

Therefore, SW253 and SW254 connect and also are connected to Vag, and Vag is input to the sampling capacitor CS250 and the CS251 of CMFF circuit 250, but the I/O end of operational amplifier 251 is Vag, therefore stored charge not.

Next, when CMFF circuit 250 was in amplification mode, CK3 became " L " level, and CK4 becomes " H " level (Fig. 9 C, Fig. 9 D).As a result, SW253, SW254, SW256 and SW257 become disconnection, and SW251, SW252 and SW255 become connection.

SW251 and SW252 become connection, Vin and Vip are provided to CS250 and CS251, and will output to the points of common connection of capacitor CS250 and CS251 by these average voltages that obtain (Vin+Vip)/2 by addition, and be provided to an input of operational amplifier 251.Another in-connector Vag of operational amplifier 251, thus the difference between this common electric voltage (=(Vin+Vip)/2) and the Vag with (CS250+CS251)/Cf250 multiplies each other, and its output Vo from operational amplifier 251 exported as VCMMD voltage.In CMFF circuit 250, the Vag that samples in advance carries out the switching of input voltage then, so the variable quantity of common electric voltage has and the identical amplitude of public variable quantity that takes place in sampling hold circuit, but has different polarity.

Notice that sampling capacitance CS250 and CS251 for the gain of determining CMFF circuit 250 do not need the electric capacity that uses identical value to be used as using in sampling hold circuit.These CS250, CD251 and Cf250 can have with sampling hold circuit 200 in those capacitance ratios much at one of using.Compare with CS152 with the input capacitor CS151 of sampling hold circuit, can select to have the CS250 and the CS251 of smaller value, and compare with Cf152, can select to have the Cf152 of smaller value with feedback condenser Cf151.

In addition, in an identical manner, the gain of operational amplifier 251 needs not to be high-gain.As the overall gain of CMFF circuit 202, consistent with the gain of sampling hold circuit 200 just enough.

(embodiment 4)

Next, the sampling hold circuit 300 that in Figure 10, shows another embodiment of the present invention.In the circuit of Figure 10, give identical note to the part identical with Fig. 5.

Sampling hold circuit 300 has sampling hold circuit shown in Figure 7 200, and come replaced C MFF circuit 202 with the CMFB circuit 302 between the output that is connected MOS transistor Q151 and Q152 and SW155 and the SW160, so this CMFB circuit 302 also receives Vag as input.

Next, will explain shown in Figure 10 to have source ground to transistorized operational amplifier by the timing waveform that uses Fig. 6 according to the embodiment of the invention.

With the operation of explaining under the replacement pattern situation.In Fig. 6 A, CK1 becomes " H " level, and the CK2 of Fig. 6 B becomes " L " level.Switching manipulation at this moment is identical with the switching manipulation of above-mentioned Fig. 7.

As a result, the grid of the I/O end of nmos pass transistor Q151 and Q152 and drain electrode are by short circuit, and transistor moves as the MOS diode.In addition, at this moment, the voltage of the tie point of input capacitor CS151 and CS152 and MOS transistor (diode) Q151 and Q152 is fixed on Vgs, and the impedance of these tie points becomes low.

SW151 and SW152 connect by short circuit, therefore Vip and Vin are provided to input capacitor CS151 and CS152, and about MOS diode Q151 and Q152 charging.On the other hand, CMFB circuit 302 outputs to Cf151 via SW155 and SW160 and Cf152 is used as VCMMD voltage from the difference between the common electric voltage (Vcmn=(Von+Vop)/2) of the output voltage of sampling hold circuit output during the amplification mode of half period (circulation) before with voltage Vag and at current period (circulation).

In addition, via SW151 Vip is provided to input capacitor CS151 and in CS151 about the Vgs of MOS diode (Q151) charging.In an identical manner, also in input capacitor CS152, about the Vgs charging Vin of MOS diode (Q152).

Next, the time of amplification mode will be explained.In Fig. 6 A, CK1 becomes " L " level, and the CK2 of Fig. 6 B becomes " H " level.Operation when switching manipulation at this moment becomes with the replacement pattern is opposite.

As a result, the grid of the I/O end of nmos pass transistor Q151 and Q152 and drain electrode disconnect about DC, and become the amplifieroperation state.

Vag is provided to input capacitor CS151 and CS152 from SW153 and SW154.Will (Vip, Vin) relevant variable quantity be sent to operational amplifier with the voltage that charges into when resetting.On the other hand, because SW155 and SW160 disconnect, therefore will not be provided to the points of common connection of SW157 and Cf151 and the points of common connection of SW159 and Cf152 from the output voltage of CMFB circuit 302.

Yet feedback condenser Cf151 and Cf152 have stored and the differential voltage (Von+Vop)/2 and the corresponding commonality schemata correction voltage VCMMD of Vag that export from CMFB circuit 302 in the replacement pattern.This VCMMD voltage is used for proofreading and correct the output function point at amplification mode.

As a result, VCMMD is added to by the difference between Vip and the Vag being multiply by the value that obtains of gain CS151/Cf151, and the result is exported.In addition, also corresponding nmos pass transistor Q152 as the voltage of the outlet side of Cf152, is added to VCMMD by the difference between Vin and the Vag being multiply by the value that gain CS152/Cf152 obtains, and the result is exported.

By this way, when hypothesis the fluctuation of Δ V occurs in the output common point in amplification mode (for example n amplification mode), CMFB circuit 302 generation-Δ V.When next replacement pattern (for example n+1 replacement pattern), by the precharge feedback condenser, when next amplification mode (for example n+1 amplification mode), undulate quantity is cancelled out each other, and the operating point of operational amplifier will not change.

It should be noted that as mentioned above, (therefore Von, the Von) deviation of detection common electric voltage, carry out the correction of variable quantity in the amplification mode of current period (circulation) back one-period (circulation) from voltage when the amplification mode of sampling hold circuit 300.

Below, in an identical manner, alternately repeat reset operation and amplifieroperation.

By this way, when sampling hold circuit was in the replacement mode state, CMFB circuit 302 charged in the capacitor Cf151 of feedback capacity and Cf152 in advance as commonality schemata via switch (SW) 155 and switch (SW) 160 and proofreaies and correct difference voltage with VCMMD voltage.

As the sampling hold circuit 300 of above embodiment, shown the example that uses nmos pass transistor, but except them, can be by this circuit of PMOS transistor arrangement, and can be configured by other insulated gate field-effect pipe.

(embodiment 5)

Figure 11 shows the CMFB circuit 350 (302) of embodiment.(CK1, (CK3 CK4) operates this CFMB circuit 350 to inversion clock CK2) by the control clock signal with sampling hold circuit.

In Figure 11, the input (Vin) that is provided with the negative output voltage Von of sampling hold circuit (300) is connected to the end of SW351, and the other end of SW351 is connected to capacitor CS350.In addition, the points of common connection of these SW351 and capacitor CS350 is connected to Vag via SW353.

The input (Vin) that is provided with the positive output voltage Vop of sampling hold circuit (300) is connected to the end of SW352, and the other end of SW352 is connected to capacitor CS351.In addition, the points of common connection of these SW352 and capacitor CS351 is connected to Vag via SW354.

The other end of capacitor CS350 and CS351 is connected publicly, and is connected to an input of operational amplifier 351, and this points of common connection is connected to Vag via SW355.The output of operational amplifier 351 is connected to other input, and this circuit arrangement forms voltage follower circuit.

To explain the operation of CFMB circuit 350 by using Fig. 9 and Figure 11.When sampling hold circuit 300 was in amplification mode, CMFB circuit 350 was in the replacement pattern, and CK3 becomes " H " level, and CK4 becomes " L " level (Fig. 9 C, Fig. 9 D).As a result, SW351, SW352 and SW355 become connection, and SW353 and SW354 become disconnection.

SW351 and SW352 and SW355 become connection, and the output voltage V on and the Vop of sampling hold circuit is provided to CS350 and CS351, and charge about Vag.

Next, when sampling hold circuit 300 is in the replacement pattern, and when CFMB circuit 350 was in amplification mode, CK3 became " L " level, and CK4 becomes " H " level (Fig. 9 C, Fig. 9 D).As a result, SW351, SW352 and SW355 become disconnection, and SW353 and SW354 become connection.

SW353 and SW354 become connection, therefore Vag are provided to input capacitor CS350 and CS351, and will be sent to the input of voltage follower circuit from the variable quantity of the output voltage of charging before the sampling hold circuit.As a result, because input capacitor CS350 is connected with CS351 is public, therefore export the average (Von+Vop)/2 of these change amounts from voltage follower circuit.

Current C MFB circuit 350 is sampled to the Von of sampling hold circuit 300 and the output voltage of Vop in advance, switch to Vag then, therefore, though its amplitude is identical with the public variable quantity that takes place in the output of sampling hold circuit 10, their polarity difference.

When sampling hold circuit 300 is in the replacement pattern, this CMFB circuit 350 via SW155 and SW160 to feedback condenser Cf151 and Cf152 precharge current period (circulation) the output common mode voltage the during fixed mode of half period (circulation) and the difference between the Vag before.

By this way, by charging feedback condenser when sampling and the replacement that keeps in advance, undulate quantity is cancelled out each other when next amplification mode, prevents that thus the operating point of operational amplifier from changing.

Note,, proofread and correct variable quantity in the amplification mode of the one-period (circulation) behind current period (circulation) in order to detect when the amplification mode of sampling hold circuit 300 deviation from the common electric voltage of output voltage.

(embodiment 6)

The example of Figure 12 display pipeline AD converter 400.In initial level, arrange sampling and keep (S/H) circuit 421, afterwards according to resolution (resolution) cascade n position/level piece (stage bit block) (422A, 422B, 422C, 422D ...).Will be at error correction/clock generation circuit 423 places from the numerical data addition each other of position piece AD conversion, and after error correction, export.

N position/level piece (422A, 422B, 422C, 422D ...) have n position ADC 411 and DAC412 and the output voltage that is used for reproducing with input analog voltage with from DAC 412 between difference amplify 2 ^(n-1)Sampling hold circuit 414 doubly.Can realize DAC, subtracter, amplifier and holding circuit by a frequent circuit that is called MDAC (multiplication DAC) 410 that uses in pipeline ADC (transducer).In this MDAC 410, can use three kinds of S/H circuit (150,200,300) of embodiments of the invention.

Next, the basic operation of this assembly line A/D converter 400 will be explained.When with analog input signal (simulation in) input sampling and maintenance (S/H) circuit 421, in the sampling period, with sampling clock synchronized sampling analog signal.In the analog signal of next timing (clock) maintenance through sampling.

The signal that will keep in S/H circuit 421 input puts in place among the piece 422A, uses predetermined precision (position) that analog signal conversion is digital signal.As the position precision of AD converter 411, have 1.5 or 2,3 or 4 etc., and in each piece the selectivity service precision.

The flash-type configuration is used for the configuration of AD converter 411.It carries out high speed operation, makes it possible to achieve pile line operation.For this reason, 2 of the quantity of comparator and figure place powers are proportional.Therefore, reduce figure place as far as possible.The quantity of comparator becomes 2 in the time of 1.5, become 3 in the time of 2, becomes 7 in the time of 3 ...The quantity of comparator is big more, and chip area is big more.Therefore the quantity of consideration position piece level and a position precision are determined it.

To be provided to error correction/clock generation circuit shown in Figure 12 423 in the data that AD converter 411 is converted into digital signal, and it will be provided to the DA transducer 412 of configuration MDAC 410.

At the DA transducer digital signal is converted to analog signal, and is provided to subtracter 413, wherein it is deducted the input analog signal that is kept.That is, output is by deducting the signal of the signal conduct of high significance bit (422A) acquisition from these subtracter 413 outputs from the input analog signal.This difference signal is provided to S/H circuit 414, (n-1) the inferior power that gains with 2 is multiplied each other, keep through amplifying signal then.

Next, the position piece 422B that the analog signal that S/H circuit 414 places of on the throne 422A are kept is provided to next stage carries out the same operation of explaining, and further carries out fine quantization in 422A.Below, regularly synchronously repeat this operation with the clock of exporting from error correction/clock generation circuit.

Above-mentioned each piece has sampling and keeps function, and therefore the position piece is about sequentially carrying out conversion according to continuous input signal of time, and the high-speed transitions operation is possible.That is, for example when a piece 422A carried out the AD conversion operations, once the AD of the analog signal of sampling changed before next conversion operations meta piece 422B execution being undertaken by position piece 422A signal AD conversion.

By this way, the analog signal that AD conversion is side by side sampled with the time sequencing of the accurate progression of position piece, and can regularly from error correction/clock generation circuit 423, extract through the AD data converted as follow-up numerical data synchronously with clock.

(embodiment 7)

Figure 13 shows another embodiment of MDAC450.As shown in figure 12, in MDAC 450, realize the function of DA transducer 412, subtracter 413 and S/H circuit 414 by a circuit.In Figure 13, have with the element of the MDAC 450 of the S/H circuit 150 identical configurations of Fig. 5 and give identical note.

In addition, the S/H circuit has the circuit arrangement identical with Fig. 5, therefore omits its explanation, and the explanation of the DA transducer (412) that is connected to its input will mainly be provided.

The grid of nmos pass transistor Q151 of configuration source ground be connected to input circuit 402A, 402B ... 402N.For example, this grid is connected to the capacitor CS402A of this input circuit 402A, and is connected to input signal Vip, and be connected to reference voltage VT and VB via SW402AB and SW402AC via SW402AA.Connect in an identical manner 402B ..., 402N.

The grid of nmos pass transistor Q152 be connected to input circuit 403A, 403B ..., 403N.For example, this grid is connected to the capacitor CS403A that disposes this input circuit 403A, and is connected to input signal Vin, and be connected to reference voltage VT and VB via SW403AB and SW403AC via SW403AA.In addition, connect in an identical manner input circuit 403B ..., 403N.

The drain electrode of nmos pass transistor Q151 and Q153 and Q152 and Q154 is connected to output Von and Vop.

According to the resolution of the AD of position piece conversion be provided at input circuit 402A, 402B ..., 402N and 403A, 403B ..., the capacitor CS402A that provides among the 403N to 403N, and is connected to reference voltage VT or VB in response to the thermometer-code output (thermometer code output) of the AD of position piece to 402N and CS403A.

Next, the operation of MDAC 450 will be explained.Hypothesis is selected input circuit 402A and 403A in AD converter 411 now.

When the replacement pattern, with reference to Fig. 6 A and Fig. 6 B, CK1 becomes " H " level, and CK2 becomes " L " level.Switching manipulation at this moment is identical with the S/H circuit 150 of Fig. 5.In addition, SW402AA and SW403AA connect, and SW402AB, SW402AC, SW403AB and SW403AC disconnect.Note, by ADC 411 control SW402AB, SW402AC, SW403AB and SW403AC.They carry out switching manipulation, feasible any one that select among VT or the VB.

Then, nmos pass transistor Q151 and Q152 operation is only arranged, their operating current is set at I151 and I152 then, so they are as the MOS diode operation.

Via SW155 and SW160 Vag is provided to Cf151 and Cf152, and about the Vgs of nmos pass transistor Q151 and Q152 (MOS diode) charging Vag.

For example, suppose to select input circuit 402A, then switch SW 402AA connects, and therefore provides output voltage from the MDAC (410) of the position piece in the previous stage as input voltage now, for example Vip.It is provided to sampling capacitor CS402A and about the Vgs of nmos pass transistor Q151 (MOS diode) charging via this switch.

Yet two other SW (SW402AB and SW402AC) disconnects, therefore, do not provide thermal voltage in response to the thermometer-code output of AD converter (reference voltage source VB, VT).In addition, also carry out identical operations at the input circuit 403A that Vin is provided to it (to 403N).

Next, when amplification mode, the operation of each SW becomes the operated in anti-phase state when resetting.As a result, nmos pass transistor Q151, Q153 and Q152 and Q154 become the amplifieroperation state.In addition, by on/off, and be connected among VT or the VB any one from the operation of the control signal of ADC 411 SW402AB, SW402AC, SW403AB, SW403AC.As a result, sampled input signal when resetting via input transistors, and will be sent to operational amplifier from the variable quantity of VT or VB.These variable quantities be multiply each other at MDAC 410 (=CS402/Cf151, here, CS402=CS402A+CS402B+ ... + CS402N) gain.

By this way, when amplification mode, provide I151 and I153 and the I152 and the I54 of current source simultaneously, the operating current of each amplifier is set to (1+n) * I0, and compares the execution high speed operation with the operation of reset cycle.

On the other hand, Q151 in parallel and Q153 and Q152 and Q154 are as the nmos pass transistor of configuration amplifier.Current density is kept constant, and make Vgs constant, simultaneously, can carry out high speed operation by using from the increase electric current of above current source.

Below, in an identical manner, interblock on the throne repeats identical operations, and regularly synchronously carries out the operation that AD changes with clock.

By this way, when the replacement pattern, the operating current value of amplifier is suppressed to 1/ (1+n) doubly, and the average current source that reduces sampling hold circuit.At this moment, also in the same manner the transistor size of the input stage of amplifier be multiply by 1/ (1+n), and transistorized current density always equates.Therefore, when only changing current value, the amplitude of the gate/source voltage Vgs of input transistors changes, and is equivalent to the input common electric voltage.The amplifier of source ground input stage is carried out the amplifieroperation of this variable quantity, therefore has the problem that moves of output function point, but can prevent this problem according to the present invention.

(embodiment 8)

Next, in Figure 14, show another embodiment MDAC500.This MDAC 500 has the configuration that obtains by the S/H circuit 200 that uses among the MDAC shown in Figure 12 400.

In the circuit arrangement of MDAC 500, DAC is connected to S/H circuit 200 shown in Figure 7, and DAC further is connected to the grid of nmos pass transistor Q151 and Q152.As shown in figure 13, each DAC has identical circuit arrangement, therefore, omits the explanation of circuit arrangement here, and only rendering circuit operation.

The operation of MDAC 500 will be explained.Hypothesis is selected input circuit 402A and 403A in AD converter 411 now.

With reference to Fig. 6 A and Fig. 6 B, when operational amplifier was in the replacement pattern, CK1 became " H " level, and CK2 becomes " L " level.This moment, switch was carried out the identical switching manipulation of operation with MDAC 450 shown in Figure 13.As a result, nmos pass transistor Q151 and Q152 are as the MOS diode.In addition, via SW155 and SW160 VCMMD voltage is provided to Cf151 and CF152 from CMFF circuit 202.To be provided to sampling capacitor as input voltage (for example Vip and Vin) from the output voltage of MDAC (500) of the position piece in the previous stage, and about the Vgs charging of MOS transistor Q151 and Q152.

Next, when amplification mode, the operated in anti-phase state when each SW becomes the replacement pattern, the result, nmos pass transistor Q151 and Q152 become the amplifieroperation state.In addition, in response to from the switch of the control signal of ADC411 operation input circuit and be connected to VT or VB in any one.Be sent to operational amplifier via the signal of input capacitor sampling when resetting with from the variable quantity of VT or VB via each input capacitor.These variable quantities be multiply by the gain of MDAC 500 and it is provided to the position piece of next stage.

Below, in an identical manner, repeat identical operations between on the throne, and regularly synchronously carry out the AD conversion operations with clock.

(embodiment 9)

Next, the MDAC 550 that shows another embodiment at Figure 15.The S/H circuit 300 of the Figure 10 that uses among the MDAC 400 that use shows in Figure 12 disposes this MDAC 550.

In the circuit arrangement of MDAC 550, each DAC further is connected to the nmos pass transistor Q151 of S/H circuit 300 shown in Figure 10 and the grid of Q152.Each DAC is identical with DAC circuit shown in Figure 13, therefore, omits the explanation of this circuit arrangement here, and only rendering circuit operation.

The operation of MDAC 550 will be explained.Hypothesis is selected input circuit 402A and 403A in AD converter 411 now.

When MDAC 550 was in the replacement pattern, its operation was identical with the operation of the MDAC 500 of Figure 14, the result, and nmos pass transistor Q151 and Q152 are as the MOS diode.In addition, VCMMD (voltage) is provided to Cf151 and Cf152 from CMFB circuit 302.

Produce VCMMD voltage from output voltage during the amplification mode of half period (circulation) before at current period (circulation), detect poor between Vag and the outputting common voltage, this potential difference is provided to each Cf151 and Cf152 as VCMMD voltage, and about the Vgs of nmos pass transistor Q151 and Q152 this VCMMD voltage that charges.

Provide output voltage to be used as (for example) Vip and Vin from the MDAC (550) of last position piece, and about the Vgs of MOS transistor Q151 and Q152 this output voltage that charges.

Next, when MDAC 550 is in amplification mode, the operated in anti-phase state when each SW becomes the replacement pattern.In addition, in response to the control signal from ADC 411, it is connected to VT or VB, and via input capacitor this signal of sampling when resetting, the variable quantity relevant with VT or VB is sent to operational amplifier.The gain that these variable quantities be multiply by MDAC 550, and output and be provided to the next bit piece.

At this example, as mentioned above, for example, by amplification undulate quantity when resetting for the n time, and the feedback condenser that when resetting for the n+1 time, charges, when amplifying for the n+1 time, will offset undulate quantity.

Below, in an identical manner, repeat identical operations between on the throne, and regularly carry out the AD conversion operations synchronously with clock.

In MDAC, thermometer code output in response to the AD converter of position piece is provided to above input circuit with reference voltage VT and VB, but in this case, when the intermediate voltage between input common electric voltage and VT and the VB is inconsistent, its difference becomes the fluctuation of common electric voltage, and this undulate quantity be multiply by the gain of MDAC and with its output.For this reason, the fluctuation of the output function point of operational amplifier, and out-put dynamic range narrows down.

By in feedback condenser, charge into the variable quantity of common electric voltage in advance by CMFF circuit and CMFB circuit, can offset the variable quantity of the common electric voltage that in operational amplifier, takes place, and can carry out stable operation, and not cause the variation of output function point.

Industrial usability

The present invention can be used for using the sampling hold circuit of switched capacitor and the stream that uses this circuit The waterline AD converter.

Claims (32)

1. sampling hold circuit comprises:

First switch is provided with first reference signal and operates on/off by first control signal;

Second switch is provided with first input signal and operates on/off by second control signal;

The 3rd switch is provided with second reference signal and operates on/off by described first control signal;

The 4th switch is provided with second input signal and operates on/off by described second control signal;

First capacitor alternately provides signal to it in response to described first and second control signals from described first and second switches;

Second capacitor alternately provides signal to it in response to described first and second control signals from described third and fourth switch;

Amplifier, it makes the output of described first and second capacitors be connected to first and second inputs, amplifies described output, and it is exported from first and second outputs;

The 5th switch and the 3rd capacitor are connected between the described first input end and first output;

The 6th switch and the 4th capacitor are connected between described second input and second output;

Be connected first and second outputs of described amplifier and first and second variable current sources between the reference power source; With

The operation setting circuit is provided with described second control signal and fixes the mode of operation of described amplifier during second control signal is provided.

2. sampling hold circuit as claimed in claim 1, wherein:

Described the 5th switch and described the 3rd capacitors in series, and described the 6th switch and described the 4th capacitors in series.

3. sampling hold circuit as claimed in claim 1, wherein:

Described first and second variable current sources have and are used for by using the 7th and the 8th diverter switch to come a plurality of current sources of switch current value.

4. sampling hold circuit as claimed in claim 1, wherein:

Described amplifier has the first transistor, and transistor seconds is in parallel with the first transistor via the 9th diverter switch.

5. sampling hold circuit as claimed in claim 4, wherein:

Dispose described first and second transistors by source ground insulated gate field-effect pipe.

6. sampling hold circuit as claimed in claim 5, wherein:

When switching described the 9th diverter switch, described first and second transistors make constant current density.

7. sampling hold circuit comprises:

First, second, third, fourth, the 5th and the 6th switch, it is equated by sample frequency and first and second clock signals of non-overlapping copies are controlled, and become on-state on the time point when described first clock is connected, seven, the 8 9th and the tenth switch becomes on-state when described second clock is connected;

Operational amplifier, be used for that negative feedback is applied to the capacitor of operational amplifier and be used for via the described the 3rd or the capacitor of the 4th switch sampled input signal,

Described first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit charge into poor between the electromotive force of addition node and the input voltage in sampling capacitor

When connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch,

Difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output,

Dispose described operational amplifier by 2 groups of source ground input stages and 2 groups of current sources, to be inserted in each group by the switch that described second clock becomes on-state, and with described second clock synchronously with the bias current value of input transistors and grid width size with (n+1) multiply each other [n＞0, integer].

8. sampling hold circuit as claimed in claim 7, wherein:

In described operational amplifier, the switch of source ground input stage is inserted into drain node.

9. sampling hold circuit comprises:

First switch is provided with first reference signal and operates on/off by first control signal;

Second switch is provided with first input signal and operates on/off by second control signal;

The 3rd switch is provided with second reference signal and operates on/off by described first control signal;

The 4th switch is provided with second reference signal and operates on/off by described second control signal;

First capacitor hands over device to provide first output signal for ground to it in response to described first and second control signals from described first and second switches;

Second capacitor alternately provides second output signal to it in response to described first and second control signals from described third and fourth switching device;

First amplifier, it makes the output of described first and second capacitors be connected to first and second inputs, amplifies described output, and it is exported from first and second outputs;

The 5th switch and the 3rd capacitor are connected between the described first input end and first output;

The 6th switch and the 4th capacitor are connected between described second input and second output;

Correcting circuit provides described first and second input signals and the 3rd reference signal to it, and it is used to proofread and correct the correction signal of the operation of described first amplifier to the output of described third and fourth capacitor in response to described second control signal; With

The operation setting circuit is provided with described second control signal and fixes the mode of operation of described amplifier during second control signal is provided.

10. sampling hold circuit as claimed in claim 9, wherein:

Described the 5th switch and described the 3rd capacitors in series, and described the 6th switch and described the 4th capacitors in series.

11. sampling hold circuit as claimed in claim 9, wherein:

The correction signal that will be used to proofread and correct the operation of described first amplifier is provided to the 5th switch of series connection and points of common connection and the 6th switch of series connection and the points of common connection of the 4th capacitor of the 3rd capacitor.

12. sampling hold circuit as claimed in claim 9, wherein:

Described correcting circuit in response to the 3rd control signal via the 7th and octavo close described correction signal be provided to described third and fourth capacitor.

13. sampling hold circuit as claimed in claim 9, wherein:

The operation setting circuit that is used for fixing the mode of operation of described first amplifier the 9th switch that charges.

14. sampling hold circuit as claimed in claim 13, wherein:

Described the 9th switch has between the described first input end that is connected described first amplifier and described first output and by the tenth switch of described second control signal control, and is connected between described second input of described amplifier and described second output and by the 11 switch of described second control signal control.

15. sampling hold circuit as claimed in claim 9, wherein:

Described amplifier has the insulated gate field-effect pipe of source ground.

16. sampling hold circuit as claimed in claim 9, wherein:

Described correcting circuit has

The 5th capacitor provides described first input signal via the twelvemo pass to it;

The 6th capacitor provides described second input signal via the 13 switch to it;

The described the 11 and second amplifier that is commonly connected to of the output of the 12 capacitor, it is connected to first input end;

The 14 switch is used to control the on/off of the I/O of described second amplifier;

Be connected on the 7th and the 15 switch between the input and output of described second amplifier; With

Sixteenmo closes device, wherein in response to the 3rd control signal described first reference signal is provided to the points of common connection of described the 7th capacitor and the 15 switch.

17. a sampling hold circuit comprises:

First, second, third, fourth, the 5th and the 6th switch equates also first and second clock signals control of non-overlapping copies by sample frequency, becomes on-state when described first clock is connected,

Seven, the 8 9th and the tenth switch becomes on-state when described second clock is connected;

Operational amplifier has as the source ground amplifier of input stage and is used for negative feedback is applied to the electric capacity of operational amplifier; With

Sampling capacitor is used for via the described the 3rd or the 4th switch sampled input signal, wherein

Described first and second switch in parallel are to the capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit charge into poor between the electromotive force of addition node and the input voltage in described sampling capacitor

When connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch,

Difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output, and

Also provide according to described reference voltage described input signal and correction voltage are connected to the described the 5th and the feed forward circuit of the 6th switch.

18. a sampling hold circuit comprises:

First, second, third, fourth, the 5th and the 6th switch equates also first and second clock signals control of non-overlapping copies by sample frequency, becomes on-state when described first clock is connected;

Seven, the 8 9th and the tenth switch becomes on-state when described second clock is connected;

Operational amplifier has as the source ground amplifier of input stage and is used for negative feedback is applied to the electric capacity of operational amplifier; With

Sampling capacitor is used for via the described the 3rd or the 4th switch sampled input signal, wherein

Described first and second switch in parallel are to the capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit charge into poor between the electromotive force of addition node and the input voltage in described sampling capacitor

When described second clock is connected, to be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, difference between the voltage that charges in the described sampling capacitor and the described reference voltage amplified so much times of the ratio of described sampling capacitance and described feedback capacity and with its output, and

Be used to detect poor between the common electric voltage of described input signal and the described reference voltage, the output of circuit of simultaneously this difference voltage being amplified so much times of the ratio of described sampling capacitance and feedback capacity is connected to the described the 5th and the 6th switch, and the polarity of this circuit is opposite with the polarity of described operational amplifier.

19. sampling hold circuit as claimed in claim 18, wherein:

The detection of the difference between the common electric voltage of described input signal and the described reference voltage and amplification have with the anti-phase switched-capacitor circuit of described control clock of described sampling hold circuit.

20. a sampling hold circuit has:

First switch is provided with first reference signal and operates on/off by first control signal;

Second switch is provided with first input signal and operates on/off by second control signal;

The 3rd switch is provided with second reference signal and operates on/off by described first control signal;

The 4th switch is provided with second input signal and operates on/off by described second control signal;

First capacitor alternately provides signal to it in response to described first and second control signals from described first and second switches;

Second capacitor alternately provides signal to it in response to described first and second control signals from described third and fourth switch;

Amplifier, it makes the output of described first and second capacitors be connected to first and second inputs, amplifies described output, and it is exported from first and second outputs;

The 5th switch and the 3rd capacitor are connected between the described first input end and first output;

The 6th switch and the 4th capacitor are connected between described second input and second output;

Correcting circuit provides described first and second input signals and the 3rd reference signal to it, and it is used to proofread and correct the correction signal of the operation of described amplifier to the output of described third and fourth capacitor in response to described second control signal; With

The operation setting device is provided with described second control signal, and it fixes the mode of operation of described amplifier during second control signal is provided.

21. sampling hold circuit as claimed in claim 20, wherein:

Described the 5th switch and described the 3rd capacitors in series, and described the 6th switch and described the 4th capacitors in series.

22. sampling hold circuit as claimed in claim 21, wherein:

The correction signal that will be used to proofread and correct the operation of described amplifier is provided to the 5th switch of series connection and points of common connection and the 6th switch of series connection and the points of common connection of the 4th capacitor of the 3rd capacitor.

23. sampling hold circuit as claimed in claim 21, wherein said sampling hold circuit also comprises:

Provide the minion of correction signal to close from described correcting circuit to it, it is provided to described the 3rd capacitor in response to the 3rd control signal with described correction signal; With

Provide the octavo of correction signal to close from described correcting circuit to it, it is provided to described the 4th capacitor in response to described the 3rd control signal with described correction signal.

24. sampling hold circuit as claimed in claim 20, wherein:

The operation setting circuit that is used for fixing the mode of operation of described amplifier the 9th switch that charges.

25. sampling hold circuit as claimed in claim 24, wherein:

Described the 9th switch has: be connected between the described first input end of described amplifier and described first output and by the tenth switch of described second control signal control, and be connected between described second input of described amplifier and described second output and by the 11 switch of described second control signal control.

26. sampling hold circuit as claimed in claim 20, wherein:

Described amplifier has source ground insulated gate field-effect pipe.

27. a sampling hold circuit, by following arrangement of components:

First, second, third, fourth, the 5th and the 6th switch, equate also first and second clock signals control of non-overlapping copies by sample frequency, when connecting, described first clock becomes on-state, and the 7th, the 8 9th and the tenth switch, when connecting, described second clock becomes on-state;

Operational amplifier has the source ground amplifier as input stage;

Be used for negative feedback is applied to the electric capacity of operational amplifier; With

Sampling capacitor is used for via the described the 3rd or the 4th switch sampled input signal, wherein

Described first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in described sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, the the described the 9th and the tenth switch is connected to the reference voltage that is used for determining operating point when described second clock is connected, and the difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output

Also comprise feedback circuit, it is connected to the described the 5th and the 6th switch according to described reference voltage with the public output and the correction voltage of described sampling hold circuit.

28. a sampling hold circuit comprises:

First, second, third, fourth, the 5th and the 6th switch, equate also first and second clock signals control of non-overlapping copies by sample frequency, when connecting, described first clock becomes on-state, and the 7th, the 8 9th and the tenth switch, when connecting, described second clock becomes on-state;

Operational amplifier has the source ground amplifier as input stage;

Be used for negative feedback is applied to the electric capacity of operational amplifier; With

Sampling capacitor is used for via the described the 3rd or the 4th switch sampled input signal, wherein

Described first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in described sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, the the described the 9th and the tenth switch is connected to the reference voltage that is used for determining operating point when described second clock is connected, and the difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and, be characterised in that its output

Be used to detect the outputting common voltage and the difference between the described reference voltage of described sampling hold circuit and export them be connected to the described the 5th and the 6th switch, and the polarity of circuit is opposite with the polarity of described operational amplifier as the output of the circuit of correction signal.

29. sampling hold circuit as claimed in claim 28, wherein:

The detection of the difference between the common electric voltage of described input signal and the described reference voltage and amplification have with the switched-capacitor circuit of the anti-phase operation of the described control clock of described sampling hold circuit.

30. assembly line A/D converter cascade, it connects a plurality of AD and changes sub-piece, each sub-piece have be used for analog signal conversion be digital code AD converter, be used for digital code with AD converter output and be converted to the DA transducer of the analogue value and be used for and will be applied to analog signal that described AD is converted to and multiply by 2 from the difference between the analog signal of described DA transducer output ^(a-1)[resolution of a:AD transducer] and with the sampling hold circuit of its output, wherein said sampling hold circuit has:

First, second, third, fourth, the 5th and the 6th switch, it is equated by sample frequency and first and second clock signals of non-overlapping copies are controlled, and becomes on-state on the time point when described first clock is connected,

Seven, the 8 9th and the tenth switch becomes on-state when described second clock is connected;

Operational amplifier;

Be used for negative feedback is applied to the capacitor of operational amplifier; With

Be used for via the described the 3rd or the capacitor of the 4th switch sampled input signal,

Described first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit charge into poor between the electromotive force of addition node and the input voltage in sampling capacitor

When connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch,

Difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output,

Dispose described operational amplifier by 2 groups of source ground input stages and 2 groups of current sources, to be inserted in each group by the switch that described second clock becomes on-state, and with described second clock synchronously with the bias current value of input transistors and grid width size with (n+1) multiply each other [n＞0, integer].

31. assembly line A/D converter cascade, it connects a plurality of AD and changes sub-piece, each sub-piece have be used for analog signal conversion be digital code AD converter, be used for digital code with AD converter output and be converted to the DA transducer of the analogue value and be used for being applied to the analog signal of described AD converter and multiply by 2 from the difference between the analog signal of described DA transducer output ^(a-1)[resolution of a:AD transducer] and with the sampling hold circuit of its output, wherein

Described sampling hold circuit has:

First, second, third, fourth, the 5th and the 6th switch equates also first and second clock signals control of non-overlapping copies by sample frequency, becomes on-state when described first clock is connected,

Seven, the 8 9th and the tenth switch becomes on-state when described second clock is connected;

Operational amplifier has source ground amplifier as input stage, is used for negative feedback is applied to the electric capacity and the sampling capacitor of operational amplifier, is used for via the described the 3rd or the 4th switch sampled input signal,

Described first and second switch in parallel are to the capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit charge into poor between the electromotive force of addition node and the input voltage in sampling capacitor

When connecting, described second clock will be used for determining that the reference voltage of operating point is provided to the described the 9th and the tenth switch, difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output

To be used to detect poor between the common electric voltage of described input signal and the described reference voltage, the output of circuit of simultaneously difference voltage being amplified so much times of the ratio of described sampling capacitance and feedback capacity is connected to the described the 5th and the 6th switch, and the polarity of this circuit is opposite with the polarity of described operational amplifier.

32. assembly line A/D converter cascade, it connects a plurality of AD and changes sub-piece, and each sub-piece has that to be used for analog signal conversion be that the AD converter, Zhou Yu of digital code is converted to the DA transducer of the analogue value with the digital code of AD converter output and is used for and will is applied to analog signal that described AD is converted to and multiply by 2 from the difference between the analog signal of described DA transducer output ^(a-1)[resolution of a:AD transducer] and with the sampling hold circuit of its output, wherein

Described sampling hold circuit is by following arrangement of components:

First, second, third, fourth, the 5th and the 6th switch, equate also first and second clock signals control of non-overlapping copies by sample frequency, when connecting, described first clock becomes on-state, and the 7th, the 8 9th and the tenth switch, when connecting, described second clock becomes on-state;

Operational amplifier has the source ground amplifier as input stage;

Be used for negative feedback is applied to the electric capacity of operational amplifier; With

Sampling capacitor is used for via the described the 3rd or the 4th switch sampled input signal, wherein

Described first and second switch in parallel are to the described capacitor that is used for negative feedback is applied to described operational amplifier, when described first clock is connection, the input and output of the described operational amplifier of short circuit, in described sampling capacitor, charge into poor between the electromotive force of addition node and the input voltage, the the described the 9th and the tenth switch is connected to the reference voltage that is used for determining operating point when described second clock is connected, difference between voltage that charges in described sampling capacitor and the described reference voltage is exaggerated so much times of the ratio of described sampling capacitance and feedback capacity, and with its output

To be used to detect poor between the common electric voltage of described input signal and the described reference voltage, the output of circuit of simultaneously difference voltage being amplified so much times of the ratio of described sampling capacitance and feedback capacity is connected to the described the 5th and the 6th switch, and the polarity of this circuit is opposite with the polarity of described operational amplifier.

Images