JP2006121480A - Sample and hold circuit, and pipeline ad converter using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sample and hold circuit for switching a current depending on operation modes to reduce an average operation current, and a pipeline AD converter using the same. <P>SOLUTION: In the sample and hold circuit, a plurality of switches are controlled in first and second clocks, the switches each change over a capacity for applying negative feedback to an operational amplifier and a sampling capacity for sampling an input signal, input/output of the operational amplifier is short-circuited when the first clock is in an on-state, the difference between the potential of a summing node and an input voltage is charged into the sampling capacity, the switches are connected to a reference voltage for deciding an operation point when the second clock is in an on-state, and the difference is amplified based on a ratio of the sampling capacity and the feedback capacity and the amplified difference is outputted. The operation current of the amplifier is switched depending on the modes to reduce the average operation current source. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a sample hold circuit using a switched capacitor and a pipeline AD converter using the sample hold circuit.

FIG. 5 shows a basic S / H (sample hold) circuit 100 conventionally used. The configuration of the S / H circuit 100 is a switched capacitor configuration including an operational amplifier 101, switches SW101, SW102, SW103, SW104, SW105, SW106, SW107, SW108, SW109, SW110 and capacitors CS100, CS101, Cf100, Cf101.
Vag is connected to switch SW103, Vip is connected to one side of capacitor CS100 via SW101, and the other terminal is connected to the first input of operational amplifier 101.
Further, Vin is connected to SW102 and Vag is connected to one terminal of capacitor CS101 via SW104, and the other is connected to the second input of operational amplifier 101. The first output of the operational amplifier 101 is connected to the first input via the SW 106, and the SW 107 and the capacitor Cf100 connected in series are connected in parallel with the first output. The second output of the operational amplifier 101 is connected to the second input via the SW 110, and the SW 109 and the capacitor Cf101 connected in series are connected in parallel with the second output.
Here, SW101, SW102, SW105, SW106, SW108, and SW110 are ON / OFF controlled with clock 1 (CK1), and SW103, SW104, SW107, and SW109 are ON / OFF controlled with clock 2 (CK2).

The operation of the S / H circuit 100 will be described using the operation timing waveform of FIG. Each switch is ON / OFF controlled by the two-phase non-overlapping clocks (CK1, CK2) shown in FIG. 6, and operates in two phases of a reset (sample) mode and an amplifier (hold) mode.
As shown in FIGS. 6A and 6B, in the reset mode, when CK1 is at “H” level, CK2 is at “L” level, and SW101, SW102, SW105, SW106, SW108, and SW110 are ON (short). Thus, SW103, SW104, SW107, and SW109 are turned off (open).
As a result, the first input / output and the second input / output of the operational amplifier 101 are short-circuited.
In the reset mode, the input / output of the operational amplifier 101 is short-circuited, and the operational amplifier 101 is biased to the operating point (Vag) having the highest gain. The input voltage (Vip, Vin) is charged in the sample capacitor CS with respect to this Vag, and the amount of charge charged in each of the capacitors CS (CS100, CS101) and Cf (Cf100, Cf101) (noting the change on one side only) For each, the following equation is obtained.

Qcs = CS (Vip−Vag) (1)
Qcf = 0 (2)

On the other hand, in the amplifier mode, the switches SW106 and SW110 between the input and output of the operational amplifier 101 are turned off, and the operational amplifier 101 becomes a capacitive feedback amplifier.
6A and 6B, CK1 is at "L" level and CK2 is at "H" level. As a result, SW101, SW102, SW105, SW106, SW108, and SW110 are turned off, and SW103, SW104, SW107, and SW109 are turned on (shorted).
The input switch is switched to Vag (terminal), and the amount of charge charged in each of the capacitors CS (CS100, CS101) and Cf (Cf100, Cf101) is as follows.

Qcs = 0 (3)
Qcf = Cf (Von−Vag) (4)

Since the total charge amount is constant in the reset mode and the amplifier mode, the output voltage Von is

Von = (CS / Cf) * (Vip−Vag) + Vag (5)

Thus, the difference between the input voltages with respect to Vag is output after being multiplied by the capacitance ratio.

Such a switched capacitor type operational amplifier is often a high-gain operational amplifier with a source-coupled pair input as shown in FIG. 9. Since it is a fully differential type, the midpoint voltage of the output signal is detected, and a desired operational amplifier is obtained. In general, common mode feedback (CMFB) is applied so that the output operating point Vag is obtained.
On the other hand, with the recent low voltage, it has become very difficult to vertically stack a plurality of transistors as shown in FIG.
As shown in FIG. 7, the source of the PMOS transistor Q201 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor Q202. The gate of the PMOS transistor Q201 is connected to a bias (Bias3). The drain of the PMOS transistor Q202 is connected to the drain of the NMOS transistor Q203, and the gate is connected to the bias (Bias2). The source of the NMOS transistor Q203 is connected to the drain of the NMOS transistor Q204, and the gate is connected to the bias (Bias1). The gate of the NMOS transistor Q204 is connected to Vin, the source is commonly connected to the source of the NMOS transistor Q208, and is connected to the drain of the NMOS transistor Q209 constituting the current source, and the source of the NMOS transistor Q209 is connected to the ground. .

  The source of the PMOS transistor Q205 is connected to the power supply VDD, and the drain is connected to the source of the PMOS transistor Q206. The gate of the PMOS transistor Q205 is connected to a bias (Bias3). The drain of the PMOS transistor Q206 is connected to the drain of the NMOS transistor Q207, and the gate is connected to the bias (Bias2). The source of the NMOS transistor Q207 is connected to the drain of the NMOS transistor Q208, and the gate is connected to the bias (Bias1). The gate of the NMOS transistor Q208 is connected to Vip, and the source is commonly connected to the source of the NMOS transistor Q204.

The drains of the NMOS transistor Q203 and the NMOS transistor Q207 are connected to a CMFB (common mode feedback) circuit 201 and also to outputs Vop and Von.
The output of the CMFB circuit 201 is connected to the gate of the NMOS transistor Q209 for current source, and controls the amount of current. As a result, the voltages at the output terminals Vop and Von are constant.

  As described above, the source-coupled pair input operational amplifier 200 has MOS transistors vertically stacked and has an advantage of increasing the output resistance, but tends to sacrifice the output linear range of the operational amplifier 200. For this reason, there is a case where a folded configuration is adopted, but there is a drawback that the total current efficiency is deteriorated.

On the other hand, FIG. 8 shows a circuit configuration example of the sample hold circuit 300 suitable for lowering the voltage by adopting an operational amplifier having a common source type input stage.
One of the current sources I300 is connected to the voltage source VDD, and the other is connected to the drain of the NMOS transistor Q300. The source of the NMOS transistor Q300 is connected to the ground, the SW306 is connected between the gate and the drain, and the SW307 and the capacitor Cf300 connected in series with this are connected in parallel. A common connection point of the capacitors Cf300 and SW307 is connected to Vag via SW305.
Further, one of the current sources I301 is connected to the voltage source VDD, and the other is connected to the drain of the NMOS transistor Q301. The source of the NMOS transistor Q301 is connected to the ground, the SW308 is connected between the gate and the drain, and the SW309 and the capacitor Cf301 connected in series in parallel with this are connected. The common connection point of the capacitors Cf301 and SW309 is connected to Vag via SW310.
The gate of the NMOS transistor Q300 is connected to the capacitor CS300, and is further connected to Vip via SW301 and to Vag via SW303.
The gate of the NMOS transistor Q301 is connected to the capacitor CS301, and is further connected to Vin via SW302 and to Vag via SW304.

As described above, two source-grounded amplifiers (Q300, Q301) are used and operate in a pseudo differential format. Since the input stage pair is not biased by the current source, a wide output linear range can be secured for one transistor. Further, since the output operating point is determined by being biased by the current source (I300, I301) from the load side, a CMFB circuit like a conventional operational amplifier is not required.
However, the above-mentioned operational amplifier using the grounded source determines gm (transformer conductance) from the balance of frequency characteristics, and therefore cannot expect further reduction in power.
JP-A-9-306193 JP 2001-196909 A Daisuke Miyazaki et all, “A 10-b 30-MS / s LOW-POWER Pipelined CMOS A / D Converter Using a Pseudo differential Architecture” IEEE JOURNAL OF SOLID-STATE CIRCUIT, VOL.38, NO2, p370-373, FEBRUARY 2003

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a sample-and-hold circuit in which an operational amplifier having a common-source input has reduced power consumption and an AD converter using the same.

  The present invention provides a first switching means that is supplied with a first reference signal and is turned on / off by a first control signal, and a first switching means that is supplied with a first input signal and is turned on / off by a second control signal. 2 switching means, a third switching means which is supplied with a second reference signal and is turned on / off by a first control signal, and an on / off action which is supplied with a second input signal and is supplied with a second control signal A fourth switching means, a first capacitor to which a signal from the first and second switching means is alternatively supplied by the first and second control signals, and the third and fourth A second capacitor to which a signal from the switching means is supplied alternatively by the first and second control signals, and outputs of the first and second capacitors to the first and second input terminals. A first amplifier connected, amplified and output from the first and second output terminals; A fifth switching means and a third capacitor connected between the first input terminal and the first output terminal, and a sixth switching connected between the second input terminal and the second output terminal. Means, a fourth capacitor, first and second variable current sources connected between first and second output terminals of the first amplifier and a reference power source, and the second control signal. And an operation setting means for fixing an operation state of the first amplifier during a period in which the second control signal is supplied.

  The present invention provides a first switching means that is supplied with a first reference signal and is turned on / off by a first control signal, and a first switching means that is supplied with a first input signal and is turned on / off by a second control signal. 2 switching means, a third switching means which is supplied with a second reference signal and is turned on / off by a first control signal, and an on / off action which is supplied with a second input signal and is supplied with a second control signal A fourth switching means, a first capacitor to which a signal from the first and second switching means is alternatively supplied by the first and second control signals, and the third and fourth A second capacitor to which a signal from the switching means is supplied alternatively by the first and second control signals, and outputs of the first and second capacitors to the first and second input terminals. Grounded source amplification that is connected, amplified, and output from the first and second output terminals And a fifth switching means and a third capacitor connected between the first input terminal and the first output terminal, and a sixth switch connected between the second input terminal and the second output terminal. Switching means, a fourth capacitor, first and second variable current sources connected between the first and second output terminals of the first amplifier and a reference power supply, and the second control signal And an operation setting means for fixing an operation state of the common-source amplifier during a period in which the second control signal is supplied.

  The present invention is controlled by first and second clocks that are equal to the sampling frequency and do not overlap each other, and the first, second, third, fourth, and second states that become conductive when the first clock is on. The fifth and sixth switches, the seventh, eighth, ninth, and tenth switches that are turned on when the second clock is on, the operational amplifier, the capacitance that applies negative feedback to the operational amplifier, and the third Or a capacitor for sampling an input signal through a fourth switch, wherein the first and second switches are connected in parallel with the capacitor for applying negative feedback to the operational amplifier, and the first clock is turned on. The input / output of the operational amplifier is short-circuited at the time, the difference between the potential of the summing node and the input voltage is charged to the sample capacitor, and the ninth and tenth switches operate when the second clock is on. And a difference between the voltage charged in the sample capacitor and the reference voltage is amplified by a ratio of the sample capacitor and the feedback capacitor, and the operational amplifier has two sets of common source input stages. And a pair of current sources, and a switch that is turned on by the second clock is inserted in each of the sets, and the bias current value and the gate of the input transistor are synchronized with the second clock. The width size is (n + 1) times [n> 0, integer].

The present invention includes an AD converter that converts an analog signal into a digital code, a DA converter that converts the digital code output from the AD converter into an analog value, and an analog signal applied to the AD converter. A plurality of AD conversion sub-blocks composed of a sample-and-hold circuit that outputs the difference from the analog signal output from the DA converter multiplied by 2 ^(a-1) [a: resolution of the AD converter]. A connected pipeline type AD converter, wherein the sample and hold circuit is controlled by first and second clocks that are equal to a sampling frequency and do not overlap each other, and is in a conductive state when the first clock is turned on. First, second, third, fourth, fifth and sixth switches, and seventh, eighth, ninth and tenth switches which become conductive when the second clock is on, Oh A capacitor for applying negative feedback to the amplifier and the operational amplifier, a capacitor for sampling an input signal through the third or fourth switch, and the first and second switches in parallel with the capacitor for applying negative feedback to the operational amplifier. When the first clock is on, the input / output of the operational amplifier is short-circuited, the difference between the potential of the summing node and the input voltage is charged to the sample capacitor, and when the second clock is on, the first The reference voltage for determining the operating point is supplied to the ninth and tenth switches, and the difference between the voltage charged in the sample capacitor and the reference voltage is amplified by the ratio of the sample capacitor and the feedback capacitor and output, The operational amplifier is composed of two sets of a common source input stage and two sets of current sources, and a switch that is turned on by the second clock is inserted in each set. Are the in the synchronization with the second clock gate width size of the bias current value and the input transistor (n + 1) times [n> 0, integer, characterized in that it is a.

The sample and hold circuit of the present invention can reduce the average operating current by changing the operating current by switching the size of the current source of the amplifier and the size of the amplifying transistor using a switch according to the operating mode.
Furthermore, the current consumption can be reduced by using this sample and hold circuit in a pipeline AD converter.

A sample and hold circuit 10 of the present invention will be described with reference to FIGS.
One of the current sources I1 is connected to the voltage source VDD, the other is connected to the drain of the NMOS transistor Q1, and the current source I2 and the switch SW13 are connected in series in parallel with the current source I1. The current source I2 is a current source that supplies a current n times that of the current source I1. The source of the NMOS transistor Q1 is connected to the ground, SW6 is connected between the gate and drain, and SW7 and capacitor Cf1 connected in series are connected in parallel with this. The common connection point of the capacitors Cf1 and SW7 is connected to Vag via SW5.
A common source NMOS transistor Q3 is provided in parallel with the NMOS transistor Q1 constituting the pseudo-differential circuit, the gate is connected in common with the gate of Q1, and the drain is connected to the drain of Q1 via SW11.
One of the current sources I3 is connected to the voltage source VDD, and the other is connected to the drain of the NMOS transistor Q2. A current source I4 and SW14 are connected in series in parallel with the current source I3. The current I4 is a current source that supplies a current n times that of the current source I3.
The source of the NMOS transistor Q2 is connected to the ground, the SW8 is connected between the gate and the drain, and the SW9 and the capacitor Cf2 connected in series are connected in parallel thereto. The common connection point of the capacitors Cf2 and SW9 is connected to Vag via SW10.
The NMOS transistor Q4 is configured similarly to the NMOS transistor Q3. That is, a common source NMOS transistor Q4 is provided in parallel with the NMOS transistor Q2, and its gate is commonly connected to the gate of Q2, and its drain is connected to the drain of Q2 via SW12.
Here, the gate widths of the NMOS transistors Q3 and Q4 are set to n times the gate width of the NMOS transistors Q1 and Q2, and if the drain current flowing through the NMOS transistors Q1 and Q2 is I0, the drain current of n * I0 flows. .
The gates of the NMOS transistors Q1 and Q3 are connected to the capacitor CS1, and further connected to Vip via SW1 and to Vag via SW3.
The gates of the NMOS transistors Q2 and Q4 are connected to the capacitor CS2, and are further connected to Vin via SW2 and to Vag via SW4.
The drains of the NMOS transistors Q1 and Q2 are connected to the outputs Von and Vop, respectively.

Next, the basic operation of the sample-and-hold circuit 10 using the operational amplifier having the common source pair shown in FIG. 1 according to the embodiment of the present invention will be described with reference to the timing waveform shown in FIG.
In the reset mode, in FIG. 2A, CK1 is at “H” level and CK2 in FIG. 2B is at “L” level, and the switches at that time are SW1, SW2, SW5, SW6, SW8, respectively. , SW10 is ON, and SW3, SW4, SW7, SW9, SW11, SW12, SW13, SW14 are OFF.
Since SW13 and SW14 are OFF, the current sources of the NMOS transistors Q1 and Q2 are I1 and I3 having a current value of I0, and this flows as a drain current to the ground through the source.
Since SW11 and SW12 are also OFF, only the NMOS transistors Q1 and Q2 operate as described above.
The gates and drains of the input / output terminals of the NMOS transistors Q1 and Q2 are short-circuited to operate as MOS diodes.
Since SW7 and SW9 are OFF, the Vag voltage is supplied to the feedback capacitors Cf1 and Cf2, and these capacitors are precharged.
Since SW1 and SW2 are ON and short-circuited on the input side of the operational amplifier, Vip is supplied to the input capacitor CS1 to charge Vgs of the NMOS transistor Q1 (MOS diode).
On the other hand, Vin is supplied to the input capacitor CS2 via SW2, and charged to Vgs of the NMOS transistor Q2 (MOS diode).

In this way, when the sample and hold is in the reset mode, this circuit switches the switch to reduce the amount of current, and the transistor size (gate width) is also 1 / (n + 1) times so that the current density is always equal.
If only the current value is changed and the size of the transistor is not changed accordingly, the magnitude of the gate-source voltage Vgs changes, which is equivalent to the change of the input common voltage. As a result, this change is amplified at the input stage of the common-source amplifier, so that the output operating point shifts.
In order to prevent such a problem, in the configuration of the present invention, when the current source is switched, a switch is provided to change the size of the transistor so that the current density becomes constant.

Next, the amplifier mode in which CK1 is “L” level in FIG. 2A and CK2 is “H” level in FIG. 2B will be described.
At this time, SW1, SW2, SW5, SW6, SW8, and SW10 are OFF, and SW3, SW4, SW7, SW9, SW11, SW12, SW13, and SW14 are ON.
Since SW13 is ON, the current source becomes (1 + n) * I0 obtained by adding I1 and I2, and this flows to the common source NMOS transistors Q1 and Q3. Since SW14 is also ON, the drain current of the current source (1 + n) * I0 obtained by adding I3 and I4 flows to the NMOS transistors Q2 and Q4.
The gates and drains of the input / output terminals of the NMOS transistors Q1, Q3, Q2, and Q4 are DC open, and change from diodes to amplifiers.
Vag is supplied to the input capacitor CS1 via SW3. The voltage difference between the input voltage Vin and Vag is multiplied by a gain (Cf1 / CS1) in the feedback capacitor Cf1, and the charge amount corresponding to the voltage and the charge precharged in Cf1 are accumulated.
Similarly, Vag is supplied to the input capacitor CS2 via SW4. The feedback capacitor Cf2 stores a charge corresponding to a voltage obtained by multiplying the voltage difference between Vin and Vag by a gain (Cf2 / CS2) and a charge precharged in Cf2.
As described above, in the amplifier mode, the current source that is the operating current is (1 + n) times that of the reset mode, and the transistor size is also (1 + n) times that of the reset mode. At this time, since the gate-source Vgs is constant, it is possible to prevent the common-mode voltage fluctuation corresponding to the common mode on the input side.
Furthermore, the average operating current can be reduced by switching the current value in accordance with the operation mode and operating efficiently by setting the operation current to I0 in the reset mode and (1 + n) * I0 in the amplifier mode.

  Although the sample hold circuit 10 of the above-described embodiment has shown an example using an NMOS transistor, it can also be constituted by a PMOS transistor, or can be constituted by an FET using an insulated gate.

FIG. 3 shows another embodiment in which the sample hold circuit of this embodiment is used in a pipeline AD converter 50. In FIG. A sample hold (S / H) 31 is arranged in the first stage, and then n-bit / stage bit blocks (32A, 32B, 32C, 32D,...) Are cascaded in accordance with the resolution. Digital data obtained by AD conversion from each bit block is added by the error correction / clock generation circuit 33 and output after error correction.
The n-bit / stage bit block (32A, 32B, 32C, 32D,...) has a difference between the n-bit ADC 41 and the DAC 42 and the input analog voltage In and the output voltage reproduced from the DAC 42 by 2 ^{(n -1) It} comprises a sample hold circuit 44 that amplifies the signal twice. DAC, subtraction, amplification, and hold can be realized by a single circuit called MDAC (Multipleing DAC) 40, and is often used for pipeline ADCs (converters). The S / H circuit of the present invention can also be applied to this MDAC 40.

Next, the operation of the pipeline AD converter 50 will be described. When the analog input signal (Analog In) is input to the sample hold (S / H) circuit 31, the analog signal is sampled in synchronization with the sample clock during the sampling period. The analog signal sampled at the next timing (clock) is held. As described above, in the S / H circuit using the switched capacitor, (Vip−Vag) is charged in the input capacitor CS during the sampling (reset mode) period, and Vag is charged in the feedback capacitor Cf.
In the reset mode, the current flowing through the drain of each NMOS transistor of the common source amplifier of the S / H circuit 31 is set to 1 / (1 + n) times that in the amplifier mode to reduce the current and reduce the power consumption. Further, the size (gate width) of the operating transistor was reduced to 1 / (1 + n) times in order to suppress the variation in Vgs due to the reduction in current.
On the other hand, in the amplifier mode, the charge of the input capacitor is transferred to the feedback capacitor Cf. As a result, a voltage obtained by adding the amount obtained by multiplying the sampling voltage by the gain and Vag is output to the output of the operational amplifier.
In the amplifier mode, the operating current of the common-source NMOS transistor is set to (1 + n) * I0 by switching the switch and adding an n-fold current source to the current source, and the transistor size (gate width) is also ( The current density was made constant, Vgs was made constant, and high-speed operation was performed so as to be 1 + n) times. As a result, Vgs related to the fluctuation of the operating point on the input side of the amplifier becomes constant even if the amount of current is varied, so that the common mode fluctuation of the input does not deteriorate.

The signal held by the S / H circuit 31 is input to the bit block 32A, and the analog signal is converted into a digital signal with a predetermined accuracy (bit). The AD converter 41 has a bit precision of 1.5 bits, 2, 3 or 4 bits, and the precision is properly used for each bit block.
The AD converter 41 has a flash configuration and is operated at high speed so that a pipeline operation is possible. Therefore, since the comparator is proportional to the power of 2 minus the number of bits, the number of bits is made as small as possible. 2 for 1.5 bits, 3 for 3 bits, 7 for 3 bits, and so on. As the number of comparators increases, the chip area increases. Decided in consideration.

The data converted into a digital signal by the AD converter 41 is supplied to the error correction / clock generation circuit 33 shown in FIG. 3 and is also supplied to the DA converter 42 constituting the MDA 40.
The digital signal is converted into an analog signal by the DA converter 42 and supplied to the subtractor 43, and the held input analog signal is subtracted. That is, the signal output from the subtracter 43 is a difference signal obtained by subtracting the upper (32A) signal from the input analog signal. This difference signal is supplied to the S / H 44, where it is multiplied by a gain of (n1-1) to the power of 2, and this amplified signal is held.
Next, the analog signal held by the S / H circuit 44 of the bit block 32A is supplied to the bit block 32B at the next stage, performs the same operation as described in 32A, and performs further quantization. Thereafter, this operation is repeated according to the clock timing output from the error correction / clock generation circuit.

Since each bit block described above has a sample-and-hold function, each bit block sequentially converts an input signal that sequentially continues in time, and a high-speed conversion operation becomes possible. That is, for example, when the bit block 32A is performing an AD conversion operation, the bit block 32B at the next stage is AD converting the analog signal sampled immediately before the signal that the bit block 32A is AD converting. become.
In this way, analog signals sampled in time series corresponding to the number of stages of the configured bit block are simultaneously AD-converted, and the AD-converted data is sequentially subjected to error correction / clock generation as digital data according to the clock timing. The circuit 33 can be taken out.
Further, in the configuration of the present invention, as described above, the operation current of the amplifier in the reset mode and the amplifier (sampling) mode in the S / H circuit is switched to reduce the operation current in the reset mode. Power consumption has been reduced.

As shown in FIG. 3, the MDAC 40 (70) realizes the functions of the DA converter 42, the subtractor 43, and the S / H circuit 44 by a single circuit. A detailed configuration and operation thereof will be described with reference to FIG.
In FIG. 4, one of the current sources I71 is connected to the voltage source VDD, and the other is connected to the drain of the NMOS transistor Q71. Further, the SW 79 and the current source I 73 are connected in series with the current source I 71 in parallel. The source of the NMOS transistor Q71 is connected to the ground, the SW72 is connected between the gate and the drain, and the SW73 and the feedback capacitor Cf71 connected in series in parallel with this are connected. The common connection point of the feedback capacitors Cf71 and SW73 is connected to Vag via SW71.
A common source NMOS transistor Q73 having a common gate connected in parallel with the NMOS transistor 71 is connected, and the drain is connected to the drain of the NMOS transistor 71 via the SW77.

One of the current sources I72 is connected to the voltage source VDD, and the other is connected to the drain of the NMOS transistor Q72. In addition, a SW 80 and a current source I 74 connected in series with the current source I 72 are connected. The source of the NMOS transistor Q72 is connected to the ground, the SW74 is connected between the gate and the drain, and the SW75 and the feedback capacitor Cf72 connected in series are connected in parallel with this. The common connection point of the feedback capacitors Cf72 and SW75 is connected to Vag.
A common source NMOS transistor Q74 whose gate is commonly connected is connected in parallel with the NMOS transistor 72, and its drain is connected to the drain of the NMOS transistor 72 via SW78.
The gate of the NMOS transistor Q71 is connected to the input circuits 72A, 72B,. The gate is connected to, for example, the capacitor CS72A of the input circuit 72A, and further connected to the input signal Vip via SW72AA and to the reference voltages VT and VB via SW72AB and SW72AC. 72B,..., 72N are similarly connected.
The gate of the NMOS transistor Q72 is connected to the input circuits 73A, 73B,. For example, the gate is connected to a capacitor CS73A constituting the input circuit 73A, and further connected to Vin via SW73A, and to reference voltage VT via SW73B and reference voltages VB and SW73C. Input circuits 73B,..., 73N are similarly connected.
The drains of the NMOS transistors Q71, Q73 and Q72, Q74 are connected to the outputs Von and Vop, respectively.

  The sample capacitors CS72 and CS73A provided in the input circuits 72A, 72B, ... 72N, 73A, 73B, ... 73N are provided in accordance with the resolution of the AD of the bit block, and the thermometer code output of the AD of the bit block Are connected to the reference voltages VT and VB.

Next, the operation of the MDAC 70 will be described.
In the reset mode, referring to FIGS. 2A and 2B, CK1 becomes “H” level and CK2 becomes “L” level. In each switch at that time, SW71, SW72, SW72AA, SW74, SW76, and SW73AA are ON, and SW72AB, SW72AC, SW73, SW73AB, SW73AC, SW75, SW77, SW78, SW79, and SW80 are OFF. However, SW72AB, SW72AC, SW73AB, and SW73AC are controlled by the ADC 41 and perform switching operation so that either VT or VB is selected.
Only the NMOS transistors Q71 and Q72 operate, the operating currents are set to I71 and I72, the gates and drains of the input and output terminals of the NMOS transistors Q71 and Q72 are shorted, and operate as a MOS diode.
Since SW71, SW72 and SW74, SW76 are ON and short-circuited, Vag is supplied to the common connection point of SW97 and Cf71 and the common connection point of SW75 and Cf72 via SW71 and SW76, respectively.
In the reset mode, since SW72 and SW74 are ON, the Vag voltage is supplied to the feedback capacitor Cf71, and Vag is charged with respect to Vgs of the NMOS transistor Q71 (MOS diode).
On the other hand, since the switch SW72AA of the input circuit 72A is ON, the output voltage from the MDAC (70) of the preceding bit block is supplied as an input voltage, for example, Vip. The voltage is supplied to the sample capacitor CS72A via this switch, and charged to Vgs of the NMOS transistor Q71 (MOS diode).
However, since the other two SWs (SW72AB, SW72AC) are OFF, thermovoltages (reference voltage sources VB, VT) according to the thermometer code output of the AD converter are not supplied.

Next, in the amplifier mode, the operation of each SW is opposite to that at the time of resetting. As a result, SW71, SW72, SW72AA, SW73AA, SW74, SW76 are turned off and SW73, SW76, SW77, SW78, SW79 are turned off. , SW80 are turned on, and the gates and drains of the input / output terminals of the NMOS transistors Q71, Q73 and Q72, Q74 are opened in a DC manner, and are in an amplification operation state. SW72AB, SW72AC, SW73AB, and SW73AC are turned on / off by a control signal from the ADC 41 and connected to one of VT and VB. As a result, the change between the input signal sampled at reset and VT or VB is transmitted to the operational amplifier via the respective input capacitors. This change is multiplied by the gain of MDAC 70 (= CS72 / Cf71, where CS72 = CS72A + CS72B +... + CS72N) and output.
Thus, in the amplifier mode, the current sources I71 and I73, and I72 and I74 are simultaneously supplied, and the operating currents of the respective amplifiers are set to (1 + n) * I0, which is faster than the operation in the reset period. Has been made to work.
On the other hand, the NMOS transistors constituting the amplifier are also connected to Q71 and Q73, Q72 and Q73 in parallel, the current density is made constant and Vgs is made constant, and the increased current from the constant current source described above is used to increase the speed. It can be operated.

  Similarly, the same operation is repeated between the bit blocks, and AD conversion is performed in synchronization with the clock timing.

Thus, in the reset mode, the operating current value of the amplifier is suppressed to 1 / (1 + n) times, and the average current source of the sample hold is reduced. At this time, the transistor size of the input stage of the amplifier was similarly 1 / (1 + n) times, and the current density of the transistors was always made equal. Therefore, changing only the current value changes the magnitude of the gate-source voltage Vgs of the input transistor, which is equivalent to the input common voltage, and the amplifier at the source-grounded input stage amplifies this change, so the output operating point shifts. Could prevent the problem.
In addition, the switch to be inserted into the current source and the input stage transistor may basically be either on the drain side or the source side. However, when the switch is inserted on the source side with respect to the input stage transistor, the ON resistance of the switch becomes between the source and the ground. It is not preferable because it enters in series and a feedback resistor enters the source. Therefore, in the amplifier configuration of the input stage described above, it is better in terms of characteristics that the switches of the NMOS transistors Q73 and Q74 are provided on the drain side.

  Although the MDAC circuit 70 of the above-described embodiment has shown an example in which an NMOS transistor is used, it can also be constituted by a PMOS transistor, or can be constituted by another insulated gate FET.

As described above, the sample hold circuit of the present invention can reduce the average operating current of the operational amplifier by controlling the bias of the operational amplifier and changing the size of the transistor according to the operation mode.
Furthermore, the current consumption can be reduced by using this sample hold circuit in a pipeline AD converter.

It is a whole block block diagram which shows the structure of the sample hold circuit of this invention. FIG. 2 is an operation timing chart for explaining the sample hold circuit shown in FIG. 1. It is a whole block diagram which shows the structure of a pipeline AD converter. FIG. 4 is a circuit diagram showing a configuration of an MDAC circuit used in the pipeline AD converter shown in FIG. 3. It is a circuit diagram which shows the sample hold circuit of a prior art example. FIG. 6 is an operation timing chart for explaining the operation of the sample and hold circuit shown in FIG. 5. It is a circuit diagram which shows the circuit structure of the amplifier used for a sample hold circuit. It is a circuit diagram which shows the other sample hold circuit structure of a prior art example.

Explanation of symbols

10, 31, 44, 100, 200, 300 ... sample hold circuit, 32A, 32D, 32C, 32D ... bit block, 33 ... error correction / clock generation circuit, 40, 70 ... MDAC (Multiple DAC), 41 ... AD conversion (ADC), 42... DA converter (DAC), 50... Pipeline AD converter, 201... CMFB (common mode feedback) circuit.

Claims (16)

A first switching means which is supplied with a first reference signal and which is turned on / off by a first control signal;
A second switching means which is supplied with a first input signal and is turned on / off by a second control signal;
A third switching means which is supplied with a second reference signal and is turned on / off by the first control signal;
A fourth switching means which is supplied with a second input signal and is turned on / off by a second control signal;
A first capacitor to which a signal from the first and second switching means is alternatively supplied by the first and second control signals;
A second capacitor to which a signal from the third and fourth switching means is alternatively supplied by the first and second control signals;
An amplifier in which the outputs of the first and second capacitors are connected to the first and second input terminals and amplifies and outputs from the first and second output terminals;
A fifth switching means and a third capacitor connected between the first input terminal and the first output terminal;
A sixth switching means and a fourth capacitor connected between the second input terminal and the second output terminal;
First and second variable current sources connected between first and second output terminals of the amplifier and a reference power source;
A sample-and-hold circuit comprising: an operation setting unit configured to fix an operation state of the amplifier during a period in which the second control signal is supplied and the second control signal is supplied. The sample-and-hold circuit according to claim 1, wherein the fifth switching means and the third capacitor are connected in series, and the sixth switching means and the fourth capacitor are also connected in series. The sample-and-hold circuit according to claim 1, wherein the first and second variable current sources have a plurality of current sources that switch current values by using seventh and eighth changeover switches. The sample-and-hold circuit according to claim 1, wherein the amplifier includes a first transistor, and a second transistor is connected in parallel with the first transistor via an eighth changeover switch. The sample-and-hold circuit according to claim 4, wherein the first and second transistors are source-grounded insulated gate field effect transistors. The sample hold circuit according to claim 4, wherein an eighth changeover switch connected to the first transistor is interlocked with the seventh or eighth changeover switch and is switched according to the first or second control signal. The sample and hold circuit according to claim 5, wherein the first and second transistors maintain a constant current density when the eighth changeover switch is switched. A first switching means which is supplied with a first reference signal and which is turned on / off by a first control signal;
A second switching means which is supplied with a first input signal and is turned on / off by a second control signal;
A third switching means which is supplied with a second reference signal and is turned on / off by the first control signal;
A fourth switching means which is supplied with a second input signal and is turned on / off by a second control signal;
A first capacitor to which a signal from the first and second switching means is alternatively supplied by the first and second control signals;
A second capacitor to which a signal from the third and fourth switching means is alternatively supplied by the first and second control signals;
A grounded-source amplifier in which outputs of the first and second capacitors are connected to first and second input terminals and amplified and output from the first and second output terminals;
A fifth switching means and a third capacitor connected between the first input terminal and the first output terminal;
A sixth switching means and a fourth capacitor connected between the second input terminal and the second output terminal;
First and second variable current sources connected between first and second output terminals of the first amplifier and a reference power source;
A sample hold circuit comprising: an operation setting unit configured to fix an operation state of the common-source amplifier during a period in which the second control signal is supplied and the second control signal is supplied. The sample-and-hold circuit according to claim 8, wherein the fifth switching means and the third capacitor are connected in series, and the sixth switching means and the fourth capacitor are also connected in series. 9. The sample and hold circuit according to claim 8, wherein the first and second variable current sources have a plurality of current sources that switch current values by using seventh and eighth changeover switches. 9. The amplifier includes a first insulated gate field effect transistor, and a second insulated gate field effect transistor is connected in parallel with the first insulated gate field effect transistor via an eighth changeover switch. Sample hold circuit. The eighth change-over switch connected to the first insulated gate field effect transistor is linked with the seventh or eighth change-over switch, and is switched according to the first or second control signal. Sample hold circuit. The sample-and-hold circuit according to claim 11, wherein the first and second insulated gate field effect transistors have a constant current density when the eighth changeover switch is switched. First, second, third, fourth, fifth and sixth controlled by first and second clocks that are equal to the sampling frequency and do not overlap each other and become conductive when the first clock is on. And seventh, eighth, ninth, and tenth switches that are conductive when the second clock is on,
An operational amplifier, a capacity for applying negative feedback to the operational amplifier, and a capacity for sampling an input signal through the third or fourth switch,
The first and second switches are connected in parallel with the capacitor that performs negative feedback to the operational amplifier, and when the first clock is on, the input and output of the operational amplifier are short-circuited, and the potential of the summing node and the input voltage are Is charged to the sample volume,
A reference voltage for determining an operating point is supplied to the ninth and tenth switches when the second clock is on;
The difference between the voltage charged in the sample capacitor and the reference voltage is amplified by the ratio of the sample capacitor and the feedback capacitor and output,
The operational amplifier includes two sets of a common source input stage and two sets of current sources. A switch that is turned on by the second clock is inserted into each of the sets, and is synchronized with the second clock. A sample-and-hold circuit in which the bias current value and the gate width size of the input transistor are (n + 1) times [n> 0, integer]. The sample-and-hold circuit according to claim 14, wherein the operational amplifier has a source-grounded input stage switch inserted on the drain side. AD converter for converting analog signal to digital code, DA converter for converting digital code output from AD converter into analog value, analog signal applied to AD converter, and DA converter A pipeline in which a plurality of AD conversion sub-blocks consisting of a sample-and-hold circuit that outputs the difference from the analog signal output by 2 ^(a-1) [a: AD converter resolution] is cascaded Type AD converter,
The sample and hold circuit includes:
First, second, third, fourth, fifth and sixth controlled by first and second clocks that are equal to the sampling frequency and do not overlap each other and become conductive when the first clock is on. And the switch
The seventh, eighth, ninth, and tenth switches that are turned on when the second clock is on, the operational amplifier, the capacitor that applies negative feedback to the operational amplifier, and the third or fourth switch The capacity to sample the input signal;
The first and second switches are connected in parallel with the capacitor that performs negative feedback to the operational amplifier, and when the first clock is on, the input and output of the operational amplifier are short-circuited, and the potential of the summing node and the input voltage are Is charged to the sample volume,
A reference voltage for determining an operating point is supplied to the ninth and tenth switches when the second clock is on;
The difference between the voltage charged in the sample capacitor and the reference voltage is amplified by the ratio of the sample capacitor and the feedback capacitor and output,
The operational amplifier includes two sets of a common source input stage and two sets of current sources. A switch that is turned on by the second clock is inserted into each of the sets, and is synchronized with the second clock. A pipeline AD converter in which the bias current value and the gate width size of the input transistor are (n + 1) times [n> 0, integer].

Images