CN117439602A

CN117439602A - Operational amplifier sharing multiple digital-to-analog conversion circuit

Info

Publication number: CN117439602A
Application number: CN202311764173.6A
Authority: CN
Inventors: 杜子昂; 段维国; 姬厚功; 裴茹霞; 叶毓明
Original assignee: Shanghai Wei'an Semiconductor Co ltd
Current assignee: Shanghai Wei'an Semiconductor Co ltd
Priority date: 2023-12-21
Filing date: 2023-12-21
Publication date: 2024-01-23

Abstract

The invention relates to the technical field of pipeline analog-to-digital converters, in particular to an operational amplifier sharing multiple digital-to-analog conversion circuit. The input end of the first switch capacitor unit is connected with a differential voltage input signal, and the differential voltage input signal is sampled and an output code of a first-stage sub analog-to-digital converter is received based on a first group of clock signals; an operational amplifier including a first pair of inputs, a second pair of inputs, and a differential output, the first pair of inputs being controllably connected to the output of the first switched capacitor unit; and the input end of the second switch capacitor unit is connected with the differential output end of the operational amplifier, samples signals of the differential output end based on a second group of clock signals and receives an output code of a second-stage sub-analog-digital converter. The invention reduces the power consumption and the area of the pipeline converter by arranging the shared operational amplifier.

Description

Operational amplifier sharing multiple digital-to-analog conversion circuit

Technical Field

The invention relates to the technical field of pipeline analog-to-digital converters, in particular to an operational amplifier sharing multiple digital-to-analog conversion circuit.

Background

In mixed signal integrated circuits, particularly for the system on chip (SoC) with higher and higher requirements and more complex functions, the design cost of the analog-to-digital converter and the high power consumption are unavoidable concerns in circuit design. For the pipeline analog-to-digital converter applied to high-speed medium-precision conversion, one of the most effective methods for realizing low power consumption is realized by adopting a multiplication digital-to-analog conversion circuit shared by operational amplifiers between sub-analog-to-digital converters.

The traditional interstage operational amplifier shares the non-ideal effects such as memory effect, interstage crosstalk and the like in the multiple digital-to-analog conversion circuit. In order to solve the problems, the conventional multiplying digital-to-analog conversion circuit generally adopts the technical schemes of adding an isolating switch, serially inputting a differential tube, multiplexing an operational amplifier input current and the like, but the schemes can increase the complexity of a system and improve the power consumption and the area of the circuit.

Disclosure of Invention

The invention aims to provide an operational amplifier sharing multiple digital-to-analog conversion circuit, which solves the technical problems; the technical problems solved by the invention can be realized by adopting the following technical scheme: the operational amplifier sharing multiple digital-to-analog conversion circuit comprises a first switch capacitor unit, wherein the input end of the first switch capacitor unit is connected with a differential voltage input signal, and the differential voltage input signal is sampled and an output code of a first-stage sub-analog-to-digital converter is received based on a first group of clock signals; an operational amplifier comprising a first pair of inputs, a second pair of inputs, and a differential output, said first pair of inputs being controllably connected to the output of said first switched capacitor unit; the input end of the second switch capacitor unit is connected with the differential output end of the operational amplifier, and the signals of the differential output end are sampled and the output code of a second-stage sub-analog-digital converter is received based on a second group of clock signals; the differential output end controllably outputs the residual voltage of the amplified first-stage sub-analog-digital converter when the first pair of inputs are connected with the output end of the first switch capacitor unit, and the differential output end controllably outputs the residual voltage of the amplified second-stage sub-analog-digital converter when the second pair of inputs are connected with the output end of the second switch capacitor unit.

Preferably, the first set of clock signals includes a first sampling signal for controlling the first switched capacitor unit to sample the differential voltage input signal; the first holding signal is used for controlling the first switched capacitor unit to receive the output code of the first-stage sub-analog-digital converter, and the first switched capacitor unit is connected with the operational amplifier to generate and amplify the residual voltage of the first-stage sub-analog-digital converter according to the output code of the first-stage sub-analog-digital converter; the first holding signal and the first sampling signal are clocks with two non-overlapping phases; the first delay signal is a clock after the first sampling signal is delayed; the first delay signal and the first hold signal are two-phase non-overlapping clocks; the second group of clock signals comprises a second sampling signal, which is used for controlling the second switch capacitor unit to sample the signals of the differential output end; the second holding signal is used for controlling the second switch capacitor unit to receive the output code of the second-stage sub-analog-digital converter, and the second switch capacitor unit is connected with the operational amplifier to generate and amplify the residual voltage of the second-stage sub-analog-digital converter according to the output code of the second-stage sub-analog-digital converter; the second holding signal and the second sampling signal are clocks with two non-overlapping phases; the second time delay signal is a clock after the second sampling signal is delayed; the second time delay signal and the second hold signal are clocks with two non-overlapping phases; the first sampled signal and the second hold signal are in phase, and the second sampled signal and the first hold signal are in phase.

Preferably, the first switched capacitor unit includes a differential voltage non-inverting input terminal; differential voltage inverting input; the first end of the first capacitor is provided with a connecting node for receiving an output code of the first-stage sub-analog-digital converter, and the second end of the first capacitor is connected with a first phase difference input end of the operational amplifier; the first switch is controllably connected between the first end of the first capacitor and the differential voltage non-inverting input end under the action of the first sampling signal; the first end of the second capacitor is provided with a connecting node for receiving an output code of the first-stage sub-analog-digital converter, and the second end of the second capacitor is connected with the first phase difference input end of the operational amplifier; the second switch is controllably connected between the first end of the second capacitor and the differential voltage non-inverting input end under the action of the first sampling signal; the first end of the third capacitor is provided with a connecting node for receiving an output code of the first-stage sub-analog-digital converter, and the second end of the third capacitor is connected with the first phase difference input end of the operational amplifier; the third switch is controllably connected between the first end of the third capacitor and the differential voltage non-inverting input end under the action of the first sampling signal; the second end of the fourth capacitor is connected with the first phase difference input end of the operational amplifier; the fourth switch is controllably connected between the first end of the fourth capacitor and the differential voltage non-inverting input end under the action of the first sampling signal; and a fifth switch controllably connected between the first end of the fourth capacitor and the inverted differential output end of the operational amplifier under the action of the first holding signal.

Preferably, the first switched capacitor unit further includes a fifth capacitor, a first end of the fifth capacitor is provided with a connection node for receiving an output code of the first stage sub-analog-digital converter, and a second end of the fifth capacitor is connected with a first inverting differential input end of the operational amplifier; a sixth switch controllably connected between the first end of the fifth capacitor and the differential voltage inverting input end under the action of the first sampling signal; the first end of the sixth capacitor is provided with a connection node for receiving the output code of the first-stage sub-analog-digital converter, and the second end of the sixth capacitor is connected with the first inverting differential input end of the operational amplifier; a seventh switch controllably connected between the first end of the sixth capacitor and the differential voltage inverting input end under the action of the first sampling signal; a seventh capacitor, wherein a first end of the seventh capacitor is provided with a connection node for receiving an output code of the first-stage sub-analog-digital converter, and a second end of the seventh capacitor is connected with a first inverting differential input end of the operational amplifier; an eighth switch controllably connected between the first end of the seventh capacitor and the differential voltage inverting input end under the action of the first sampling signal; the second end of the eighth capacitor is connected with the first phase difference input end of the operational amplifier; a ninth switch controllably connected between the first end of the eighth capacitor and the differential voltage non-inverting input end under the action of the first sampling signal; and a tenth switch controllably connected between the first end of the eighth capacitor and the inverting differential output end of the operational amplifier under the action of the first holding signal.

Preferably, the second switched capacitor unit includes a ninth capacitor, a first end of the ninth capacitor is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the ninth capacitor is connected with a second in-phase differential input end of the operational amplifier; an eleventh switch controllably connected between the first end of the ninth capacitor and the inverting differential output end of the operational amplifier under the action of the second sampling signal; a tenth capacitor, wherein a first end of the tenth capacitor is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the tenth capacitor is connected with a second in-phase differential input end of the operational amplifier; a twelfth switch controllably connected between the first end of the tenth capacitor and the inverting differential output end of the operational amplifier under the action of the second sampling signal; an eleventh capacitor, wherein a first end of the eleventh capacitor is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the eleventh capacitor is connected with a second in-phase differential input end of the operational amplifier; a thirteenth switch controllably connected between the first end of the eleventh capacitor and the inverting differential output end of the operational amplifier under the action of the second sampling signal; a twelfth capacitor, wherein a second end of the twelfth capacitor is connected with a second non-inverting differential input end of the operational amplifier; a fourteenth switch controllably connected between the first end of the twelfth capacitor and the inverting differential output end of the operational amplifier under the action of the second sampling signal; a fifteenth switch controllably connected between the first end of the twelfth capacitor and the inverting differential output of the operational amplifier under the action of the second hold signal.

Preferably, the second switched capacitor unit further includes a thirteenth capacitor, a first end of the thirteenth capacitor is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the thirteenth capacitor is connected with a second inverting differential input end of the operational amplifier; a sixteenth switch controllably connected between the first end of the thirteenth capacitor and the in-phase differential output end of the operational amplifier under the action of the second sampling signal; a fourteenth capacitor, wherein a first end of the fourteenth capacitor is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the fourteenth capacitor is connected with a second inverting differential input end of the operational amplifier; a seventeenth switch controllably connected between the first end of the fourteenth capacitor and the in-phase differential output end of the operational amplifier under the action of the second sampling signal; a fifteenth capacitor, wherein a first end of the fifteenth capacitor is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the fifteenth capacitor is connected with a second inverting differential input end of the operational amplifier; an eighteenth switch controllably connected between the first end of the fifteenth capacitor and the in-phase differential output end of the operational amplifier under the action of the second sampling signal; a sixteenth capacitor, wherein a second end of the sixteenth capacitor is connected with a second inverting differential input end of the operational amplifier; a nineteenth switch controllably connected between the first end of the sixteenth capacitor and the in-phase differential output end of the operational amplifier under the action of the second sampling signal; a twentieth switch controllably connected between the first terminal of the sixteenth capacitor and the in-phase differential output terminal of the operational amplifier under the action of the second hold signal.

Preferably, the first switched capacitor unit further includes a twenty-first switch controllably connected between the first common-mode voltage and the first differential input of the operational amplifier under the action of the first delay signal; a twenty-second switch controllably connected between the first inverting differential input of the operational amplifier and the common mode voltage under the influence of the first delay signal; the second switch capacitor unit further comprises a twenty-third switch controllably connected between a second in-phase differential input end of the operational amplifier and the common mode voltage under the action of the second time delay signal; and the twenty-fourth switch is controllably connected between the second inverting differential input end of the operational amplifier and the common mode voltage under the action of the second time delay signal.

Preferably, the operational amplifier comprises a first PMOS tube, wherein the grid electrode of the first PMOS tube is biased at a second bias voltage; the grid electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube; the source electrode of the third PMOS tube is connected with a power supply signal, the grid electrode of the third PMOS tube is biased at a first bias voltage, and the drain electrode of the third PMOS tube is connected with the source electrode of the first PMOS tube; the source electrode of the fourth PMOS tube is connected with the power supply signal, the grid electrode of the fourth PMOS tube is connected with the grid electrode of the third PMOS tube, and the drain electrode of the fourth PMOS tube is connected with the source electrode of the second PMOS tube; the grid electrode of the first NMOS tube is connected with a first-stage switched capacitor common mode feedback module, and the source electrode of the first NMOS tube is grounded; the grid of the third NMOS tube is a first phase difference input end of the operational amplifier; the grid of the fourth NMOS tube is a first inverting differential input end of the operational amplifier; a gate of the fifth NMOS tube is connected with a first clock effective signal, a drain of the fifth NMOS tube is connected with a source of the third NMOS tube, and a source of the fifth NMOS tube is connected with a drain of the first NMOS tube; a sixth NMOS tube, wherein the grid electrode of the sixth NMOS tube is connected with the first clock effective signal, the drain electrode of the sixth NMOS tube is connected with the source electrode of the fourth NMOS tube, and the source electrode of the sixth NMOS tube is connected with the drain electrode of the first NMOS tube; a seventh NMOS tube, the gate of which is the second in-phase differential input end of the operational amplifier; the drain electrode of the seventh NMOS tube is connected with the drain electrode of the third NMOS tube; an eighth NMOS transistor having a gate that is a second inverting differential input of the operational amplifier; the drain electrode of the eighth NMOS tube is connected with the drain electrode of the fourth NMOS tube; a ninth NMOS tube, wherein the grid electrode of the ninth NMOS tube is connected with a second clock effective signal, the drain electrode of the ninth NMOS tube is connected with the source electrode of the seventh NMOS tube, and the source electrode of the ninth NMOS tube is connected with the drain electrode of the first NMOS tube; a tenth NMOS tube, wherein the grid electrode of the tenth NMOS tube is connected with the second clock effective signal, the drain electrode of the tenth NMOS tube is connected with the source electrode of the eighth NMOS tube, and the source electrode of the tenth NMOS tube is connected with the drain electrode of the first NMOS tube; an eleventh NMOS tube, the drain electrode of the eleventh NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the eleventh NMOS tube is biased on a third bias voltage, and the source electrode of the eleventh NMOS tube is connected with the drain electrode of the third NMOS tube; and a twelfth NMOS tube, wherein the drain electrode of the twelfth NMOS tube is connected with the drain electrode of the second PMOS tube, the grid electrode of the twelfth NMOS tube is connected with the eleventh NMOS tube, and the source electrode of the eleventh NMOS tube is connected with the drain electrode of the third NMOS tube.

Preferably, the operational amplifier further comprises a fifth PMOS transistor, wherein a source electrode of the fifth PMOS transistor is connected to the power signal, and a gate electrode of the fifth PMOS transistor is connected to a gate electrode of the third PMOS transistor; a sixth PMOS tube, wherein the source electrode of the sixth PMOS tube is connected with the power supply signal, and the grid electrode of the sixth PMOS tube is connected with the grid electrode of the fifth PMOS tube; the grid electrode of the second NMOS tube is connected with a second-stage switched capacitor common mode feedback module, and the source electrode of the second NMOS tube is grounded; a thirteenth NMOS transistor, the gate of the thirteenth NMOS transistor is connected to the drain of the eleventh NMOS transistor, the source of the thirteenth NMOS transistor is connected to the drain of the second NMOS transistor, and the drain of the thirteenth NMOS transistor is connected to the drain of the fifth PMOS transistor and is an in-phase differential output terminal of the operational amplifier; a fourteenth NMOS tube, wherein the grid electrode of the fourteenth NMOS tube is connected with the drain electrode of the twelfth NMOS tube, the source electrode of the fourteenth NMOS tube is connected with the drain electrode of the second NMOS tube, and the drain electrode of the fourteenth NMOS tube is connected with the drain electrode of the sixth PMOS tube and is an inverted differential output end of the operational amplifier; the top polar plate of the first miller compensation capacitor is connected with the drain electrode of the third NMOS tube, and the bottom polar plate of the first miller compensation capacitor is connected with the drain electrode of the thirteenth NMOS tube; and the top polar plate of the second miller compensation capacitor is connected with the drain electrode of the fourth NMOS tube, and the bottom polar plate of the second miller compensation capacitor is connected with the drain electrode of the fourteenth NMOS tube.

Preferably, the first stage switched capacitor common mode feedback module includes a seventeenth capacitor, wherein a first end of the seventeenth capacitor is connected to the drain of the eleventh NMOS transistor through a twenty-fifth switch controlled based on the first holding signal; an eighteenth capacitor, wherein a first end of the eighteenth capacitor is connected to the drain of the twelfth NMOS transistor through a twenty-first sixteen switch controlled based on the first holding signal, and a second end of the eighteenth capacitor is connected to a second end of the seventeenth capacitor; a nineteenth capacitor, wherein a first end of the nineteenth capacitor is connected with the drain electrode of the eleventh NMOS tube, and a second end of the nineteenth capacitor is connected with the gate electrode of the first NMOS tube to output a first common mode feedback voltage; a twentieth capacitor, wherein a first end of the twentieth capacitor is connected with the drain electrode of the twelfth NMOS transistor, and a second end of the twentieth capacitor is connected with the second end of the nineteenth capacitor; a seventeenth switch controllably connected between the second terminal of the seventeenth capacitor and the second terminal of the nineteenth capacitor under the action of the first holding signal; the twenty-eighth switch is controllably connected between the first end of the seventeenth capacitor and a first reference voltage under the action of the first sampling signal; a twenty-ninth switch controllably connected between the first end of the eighteenth capacitor and the first reference voltage under the action of the first sampling signal; a thirty-first switch controllably connected between the second end of the seventeenth capacitor and a second reference voltage under the action of the first sampling signal; the second-stage switched capacitor common mode feedback module comprises a twenty-first capacitor, wherein a first end of the twenty-first capacitor is connected with a drain electrode of the thirteenth NMOS tube through a thirty-first switch controlled based on the first holding signal; a twenty-second capacitor, wherein a first end of the twenty-second capacitor is connected with the drain electrode of the fourteenth NMOS tube through a thirty-second switch controlled based on the first holding signal, and a second end of the twenty-second capacitor is connected with a second end of the twenty-first capacitor; a twenty-third capacitor, wherein a first end of the twenty-third capacitor is connected with the drain electrode of the thirteenth NMOS tube, and a second end of the twenty-third capacitor is connected with the grid electrode of the second NMOS tube to output a second common mode feedback voltage; a twenty-fourth capacitor, wherein a first end of the twenty-fourth capacitor is connected with the drain electrode of the fourteenth NMOS tube, and a second end of the twenty-fourth capacitor is connected with a second end of the twenty-third capacitor; a thirty-third switch controllably connected between the second terminal of the twenty-first capacitor and the second terminal of the twenty-third capacitor under the influence of the first hold signal; a thirty-fourth switch controllably connected between the first end of the twenty-first capacitor and the first reference voltage under the action of the first sampling signal; a thirty-fifth switch controllably connected between the first end of the twenty-second capacitor and the first reference voltage under the action of the first sampling signal; and a thirty-sixth switch controllably connected between the second end of the twenty-first capacitor and the second reference voltage under the action of the first sampling signal.

The invention has the beneficial effects that: by adopting the technical scheme, the power consumption and the area of the pipeline converter are reduced by arranging the shared operational amplifier.

Drawings

FIG. 1 is a schematic diagram of an operational amplifier sharing multiple digital-to-analog conversion circuit in an embodiment of the invention;

FIG. 2 is a timing diagram of a switch according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an operational amplifier according to an embodiment of the present invention;

FIG. 4 is a circuit diagram of a first stage switched capacitor common mode feedback module according to an embodiment of the present invention;

fig. 5 is a circuit diagram of a second-stage switched capacitor common mode feedback module according to an embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.

The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.

An operational amplifier sharing multiple digital-to-analog conversion circuit, as shown in fig. 1 to 5, includes a first switched capacitor unit 101, an input terminal of the first switched capacitor unit 101 is connected with a differential voltage input signal, and the differential voltage input signal is sampled and an output code of a first-stage sub-analog-to-digital converter is received based on a first group of clock signals; an operational amplifier 103 comprising a first pair of inputs, a second pair of inputs and a differential output, the first pair of inputs being controllably connected to the output of the first switched capacitor unit 101; the input end of the second switched capacitor unit 102 is connected with the differential output end of the operational amplifier 103, and samples signals of the differential output end based on a second group of clock signals and receives an output code of a second-stage sub-analog-digital converter; the differential output terminal controllably outputs the residual voltage of the amplified first-stage sub-analog-digital converter when the first pair of inputs is connected to the output terminal of the first switched-capacitor unit 101, and the differential output terminal controllably outputs the residual voltage of the amplified second-stage sub-analog-digital converter when the second pair of inputs is connected to the output terminal of the second switched-capacitor unit 102.

Specifically, the invention provides a multiplying digital-to-analog conversion circuit (Multiplying Digital to Analog Converter, MDAC) applied to a pipeline analog-to-digital converter. The multiple digital-to-analog conversion circuit provided by the invention is applied to sub-ADCs of each stage of 2.5bit in a pipeline ADC, and the adjacent two stages of sub-ADCs share the operational amplifier 103 in the same multiple digital-to-analog conversion circuit. The multiplying digital-to-analog conversion circuit provided by the invention utilizes the idle phase of the operational amplifier 103 to carry out digital-to-analog conversion, and when the front-stage ADC, namely the first-stage sub-analog-to-digital converter, the output of the rear-stage ADC, namely the second-stage sub-analog-to-digital converter, is converted into an analog signal, so that the working efficiency of the whole assembly line ADC is improved; compared with a non-operational amplifier sharing type MDAC circuit, the MDAC circuit designed by the scheme has lower power consumption and smaller area.

In a preferred embodiment, as shown in fig. 2, the first set of clock signals includes a first sampling signal Φa_sample for controlling the first switched capacitor unit 101 to sample the differential voltage input signal; the first holding signal Φa_hold is used for controlling the first switched capacitor unit 101 to receive the output code of the first-stage sub-analog-digital converter, and the first switched capacitor unit 101 and the operational amplifier 103 are connected to generate and amplify the residual voltage of the first-stage sub-analog-digital converter according to the output code of the first-stage sub-analog-digital converter; the first holding signal phia_hold and the first sampling signal phia_sample are clocks with two non-overlapping phases; the first delay signal phia_sample_delay is a clock after delay of the first sampling signal phia_sample; the first delay signal phia_sample_delay and the first hold signal phia_hold are clocks with two non-overlapping phases; the second set of clock signals includes a second sampling signal Φb_sample, which is used to control the second switched capacitor unit 102 to sample the signals of the differential output terminals; the second hold signal Φb_hold is used for controlling the second switched capacitor unit 102 to receive the output code of the second-stage sub-analog-digital converter, and the second switched capacitor unit 102 and the operational amplifier 103 are connected to generate and amplify the residual voltage of the second-stage sub-analog-digital converter according to the output code of the second-stage sub-analog-digital converter; the second holding signal phib_hold and the second sampling signal phib_sample are clocks with two non-overlapping phases; the second delay signal phib_sample_delay is a clock delayed by the second sampling signal phib_sample; the second delay signal phi b_sample_delay and the second hold signal phi b_hold are clocks with two non-overlapping phases; the first sampling signal Φa_sample and the second holding signal Φb_hold are in phase, and the second sampling signal Φb_sample and the first holding signal Φa_hold are in phase.

In a preferred embodiment, the first switched capacitor unit 101 includes a differential voltage non-inverting input terminal Vinp, a differential voltage inverting input terminal Vinn, a first capacitor Cap1, a first end of the first capacitor Cap1 is provided with a connection node for receiving an output code of the first stage sub-analog-digital converter, and a second end of the first capacitor Cap1 is connected to a first non-inverting input terminal Vinpa of the operational amplifier 103; the first switch SWap1 is controllably connected between the first end of the first capacitor Cap1 and the differential voltage non-inverting input terminal Vinp under the action of a first sampling signal phia_sample; the first end of the second capacitor Cap2 is provided with a connection node for receiving an output code of the first-stage sub-analog-digital converter, and the second end of the second capacitor Cap2 is connected with the first phase difference input end Vinpa of the operational amplifier 103; the second switch SWap2 is controllably connected between the first end of the second capacitor Cap2 and the differential voltage non-inverting input terminal Vinp under the action of the first sampling signal phia_sample; the first end of the third capacitor Cap3 is provided with a connection node for receiving an output code of the first-stage sub-analog-digital converter, and the second end of the third capacitor Cap3 is connected with the first phase difference input end Vinpa of the operational amplifier 103; the third switch SWap3 is controllably connected between the first end of the third capacitor Cap3 and the differential voltage non-inverting input terminal Vinp under the action of the first sampling signal phia_sample; the second end of the fourth capacitor Cafp is connected with the first phase difference input end Vinpa of the operational amplifier 103; the fourth switch SWap4 is controllably connected between the first end of the fourth capacitor Cafp and the differential voltage non-inverting input terminal Vinp under the action of the first sampling signal Φa_sample; the fifth switch SWap5 is controllably connected between the first terminal of the fourth capacitor Cafp and the inverted differential output terminal Voutn of the operational amplifier 103 under the action of the first hold signal Φa_hold.

In a preferred embodiment, the first switched capacitor unit 101 further includes a fifth capacitor Can1, where a first end of the fifth capacitor Can1 is provided with a connection node for receiving an output code of the first stage of the sub-analog-digital converter, and a second end of the fifth capacitor Can1 is connected to the first inverting differential input terminal Vinna of the operational amplifier 103; the sixth switch SWan1 is controllably connected between the first end of the fifth capacitor Can1 and the differential voltage inverting input terminal Vinn under the action of the first sampling signal Φa_sample; a first end of the sixth capacitor Can2 is provided with a connection node for receiving an output code of the first-stage sub-analog-digital converter, and a second end of the sixth capacitor Can2 is connected with a first inverting differential input end Vinna of the operational amplifier 103; the seventh switch SWan2 is controllably connected between the first end of the sixth capacitor Can2 and the differential voltage inverting input terminal Vinn under the action of the first sampling signal Φa_sample; a first end of the seventh capacitor Can3 is provided with a connection node for receiving an output code of the first-stage sub-analog-digital converter, and a second end of the seventh capacitor Can3 is connected with a first inverting differential input end Vinna of the operational amplifier 103; the eighth switch SWan3 is controllably connected between the first end of the seventh capacitor Can3 and the differential voltage inverting input terminal Vinn under the action of the first sampling signal Φa_sample; the second end of the eighth capacitor Cafn is connected with the first phase difference input end Vinpa of the operational amplifier 103; a ninth switch SWan4 controllably connected between the first end of the eighth capacitor Cafn and the differential voltage non-inverting input terminal Vinp under the action of the first sampling signal Φa_sample; the tenth switch SWan5 is controllably connected between the first terminal of the eighth capacitor Cafn and the inverted differential output terminal Voutn of the operational amplifier 103 under the action of the first hold signal Φa_hold.

In particular, the invention aims to design a digital-to-analog conversion circuit applied to a pipeline analog-to-digital converter, and the MDAC circuit can reduce the power consumption and the area of an ADC. To achieve the object, the present invention provides a 2.5bit op-amp shared digital-to-analog conversion circuit, which includes an operational amplifier 103, a first switched capacitor unit 101 and a second switched capacitor unit 102, wherein: the first switched capacitor unit 101 and the operational amplifier 103 form a 2.5bit digital-to-analog conversion circuit of the first-stage sub-analog-to-digital converter, the digital-to-analog conversion circuit of the invention receives the current 3bit Flash ADC, namely the three-bit binary digital code of the first-stage sub-analog-to-digital converter, which can be the signal after the conversion of other bit data, such as a 6-bit temperature counting signal, through the first switched capacitor unit 101, and the analog-to-digital conversion circuit is used for generating and amplifying the residual voltage of the first-stage sub-analog-to-digital converter; the first switched capacitor unit 101 specifically includes a first switch SWap1, a second switch SWap2, a third switch SWap3, a fourth switch SWap4, a fifth switch SWap5, a sixth switch SWan1, a seventh switch SWan2, an eighth switch SWan3, a ninth switch SWan4, a tenth switch SWan5, a twenty-first switch SWas1, a twenty-second switch SWas2, a first capacitor Cap1, a second capacitor Cap2, a third capacitor Cap3, a fourth capacitor caf, a fifth capacitor Can1, a sixth capacitor Can2, a seventh capacitor Can3, and an eighth capacitor Can.

In a preferred embodiment, the second switched capacitor unit 102 includes a ninth capacitor Cbp1, where a first end of the ninth capacitor Cbp1 is provided with a connection node for receiving an output code of the second stage sub-analog-digital converter, and a second end of the ninth capacitor Cbp1 is connected to the second in-phase differential input terminal Vinpb of the operational amplifier 103; the eleventh switch SWbp1 is controllably connected between the first end of the ninth capacitor Cbp1 and the inverting differential output end Voutn of the operational amplifier 103 under the action of the second sampling signal Φb_sample; a first end of the tenth capacitor Cbp2 is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the tenth capacitor Cbp2 is connected with a second in-phase differential input end Vinpb of the operational amplifier 103; the twelfth switch SWbp2 is controllably connected between the first end of the tenth capacitor Cbp2 and the inverting differential output end Voutn of the operational amplifier 103 under the action of the second sampling signal Φb_sample; an eleventh capacitor Cbp3, wherein a first end of the eleventh capacitor Cbp3 is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the eleventh capacitor Cbp3 is connected with a second in-phase differential input end Vinpb of the operational amplifier 103; the thirteenth switch SWbp3 is controllably connected between the first end of the eleventh capacitor Cbp3 and the inverting differential output terminal Voutn of the operational amplifier 103 under the action of the second sampling signal Φb_sample; a second end of the twelfth capacitor Cbfp is connected to the second non-inverting differential input Vinpb of the operational amplifier 103; a fourteenth switch SWbp4 controllably connected between the first end of the twelfth capacitor Cbfp and the inverting differential output terminal Voutn of the operational amplifier 103 under the action of the second sampling signal Φb_sample; the fifteenth switch SWbp5 is controllably connected between the first terminal of the twelfth capacitor Cbfp and the inverted differential output terminal Voutn of the operational amplifier 103 under the action of the second hold signal Φb_hold.

In a preferred embodiment, the second switched capacitor unit 102 further includes a thirteenth capacitor Cbn1, a first end of the thirteenth capacitor Cbn1 is provided with a connection node for receiving an output code of the second stage of the sub-analog-digital converter, and a second end of the thirteenth capacitor Cbn1 is connected to the second inverting differential input Vinnb of the operational amplifier 103; the sixteenth switch SWbn1 is controllably connected between the first end of the thirteenth capacitor Cbn1 and the in-phase differential output terminal Voutp of the operational amplifier 103 under the action of the second sampling signal Φb_sample; a first end of the fourteenth capacitor Cbn2 is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the fourteenth capacitor Cbn2 is connected with a second inverting differential input terminal Vinnb of the operational amplifier 103; the seventeenth switch SWbn2 is controllably connected between the first end of the fourteenth capacitor Cbn2 and the in-phase differential output terminal Voutp of the operational amplifier 103 under the action of the second sampling signal Φb_sample; a first end of the fifteenth capacitor Cbn3, a connection node is arranged at a first end of the fifteenth capacitor Cbn3 and is used for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the fifteenth capacitor Cbn3 is connected with a second inverting differential input terminal Vinnb of the operational amplifier 103; the eighteenth switch SWbn3 is controllably connected between the first end of the fifteenth capacitor Cbn3 and the in-phase differential output end Voutp of the operational amplifier 103 under the action of the second sampling signal Φb_sample; a second end of the sixteenth capacitor Cbfn is connected to the second inverting differential input terminal Vinnb of the operational amplifier 103; the nineteenth switch SWbn4 is controllably connected between the first end of the sixteenth capacitor Cbfn and the in-phase differential output terminal Voutp of the operational amplifier 103 under the action of the second sampling signal Φb_sample; the twentieth switch SWbn5 is controllably connected between the first terminal of the sixteenth capacitor Cbfn and the in-phase differential output terminal Voutp of the operational amplifier 103 under the action of the second hold signal Φb_hold.

Specifically, the second switched capacitor unit 102 and the operational amplifier 103 form a 2.5bit digital-to-analog conversion circuit of the second-stage sub-analog-to-digital converter, the digital-to-analog conversion circuit of the invention receives the second-stage 3bit Flash ADC, that is, the three-bit binary digital code of the second-stage sub-analog-to-digital converter, through the second switched capacitor unit 102, wherein the three-bit binary digital code can be a signal after conversion of other bits, such as a 6-bit temperature count signal, and the analog-to-digital conversion circuit is used for generating and amplifying the residual voltage of the second-stage sub-analog-to-digital converter; the second switch capacitor unit 102 specifically includes an eleventh switch SWbp1, a twelfth switch SWbp2, a thirteenth switch SWbp3, a fourteenth switch SWbp4, a fifteenth switch SWbp5, a sixteenth switch SWbn1, a seventeenth switch SWbn2, an eighteenth switch SWbn3, a nineteenth switch SWbn4 the twenty-third switch SWbn5, the twenty-third switch SWbs1, the twenty-fourth switch SWbs2, the ninth capacitor Cbp1, the tenth capacitor Cbp2, the eleventh capacitor Cbp3, the twelfth capacitor Cbfp, the thirteenth capacitor Cbn1, the fourteenth capacitor Cbn2, the fifteenth capacitor Cbn3, and the sixteenth capacitor Cbfn.

Specifically, the first capacitor Cap1 switch unit and the operational amplifier 103 form a digital-to-analog conversion circuit, and the second capacitor Cap2 switch unit and the operational amplifier 103 form a digital-to-analog conversion circuit to operate under the control of two groups of two non-overlapping clock signals, wherein the first group of clocks are a first sampling phase and a first holding phase, and the second group of clocks are a second sampling phase and a second holding phase. In a first sampling phase, the digital-to-analog conversion circuit samples differential input signals of a first-stage 3bit Flash ADC; in the first holding phase, the digital-to-analog conversion circuit completes the summation amplification of the residual voltage according to the output code of the first-stage 3bit Flash ADC; in a second sampling phase, the digital-to-analog conversion circuit samples differential input signals of a second-stage 3bit Flash ADC; and in the second holding phase, the digital-to-analog conversion circuit completes the summation amplification of the residual voltage according to the output code of the second-stage 3bit Flash ADC.

In a preferred embodiment, the first switched capacitor unit 101 further includes a twenty-first switch SWas1 controllably connected between the first common-mode voltage Vinpa and a common-mode voltage Vcm of the operational amplifier 103 under the action of the first delay signal Φa_sample_delay; the twenty-second switch SWas2 is controllably connected between the first inverting differential input terminal Vinna of the operational amplifier 103 and the common-mode voltage Vcm under the action of the first delay signal Φa_sample_delay; the second switched capacitor unit 102 further includes a twenty-third switch SWbs1 controllably connected between the second non-inverting differential input Vinpb and the common-mode voltage Vcm of the operational amplifier 103 under the action of the second delay signal Φb_sample_delay; the twenty-fourth switch SWbs2 is controllably connected between the second inverting differential input Vinnb of the operational amplifier 103 and the common mode voltage Vcm under the action of the second delay signal Φb_sample_delay.

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings, and the specific embodiment is shown in fig. 1, in which 101 is a first switched capacitor unit in a digital-to-analog conversion circuit, 102 is a second switched capacitor unit in an MDAC circuit, and 103 is an operational amplifier. The switching sequence related to the present invention is shown in fig. 2, and the specific sequence includes a first sampling signal Φa_sample, a first hold signal Φa_hold, a first delay signal Φa_sample_delay, a second sampling signal Φb_sample, a second hold signal Φb_hold, and a second delay signal Φb_sample_delay. The first sampling signal Φa_sample and the first holding signal Φa_hold are two-phase non-overlapping clocks, the first delay signal Φa_sample_delay is a clock after the first sampling signal Φa_sample is delayed, and the first delay signal Φa_sample_delay and the first holding signal Φa_hold are still two-phase non-overlapping clocks; the second sampling signal phib_sample and the second holding signal phib_hold are two-phase non-overlapping clocks, the second delay signal phib_sample_delay is a clock after the second sampling signal phib_sample delays, and the second delay signal phib_sample_delay and the second holding signal phib_hold are still two-phase non-overlapping clocks; the first sampling signal Φa_sample is in phase with the second holding signal Φb_hold, and the second sampling signal Φb_sample is in phase with the first holding signal Φa_hold.

In the switch time sequence related by the invention, a switch controlled by a first sampling signal phia_sample is provided with a first switch SWap1, a second switch SWap2, a third switch SWap3, a fourth switch SWap4, a sixth switch SWan1, a seventh switch SWan2, an eighth switch SWan3 and a ninth switch SWan4 in a first switch capacitor common mode feedback module 104, a twenty eighth switch SW28, a twenty ninth switch SW29 and a thirty-fifth switch SW30 in a first switch capacitor common mode feedback module 104, a thirty-fourth switch SW34, a thirty-fifth switch SW35 and a thirty-sixth switch SW36 in a second switch capacitor common mode feedback module 105, and a switch controlled by a first holding signal phia_hold is provided with a fifth switch SWap5 and a tenth switch SWan5 in the first switch capacitor common mode feedback module 101, a twenty-fifth switch SW25, a twenty-fifth switch SW26 and a twenty-fifth switch SW27 in the first switch capacitor common mode feedback module 104, and a thirty-fifth switch SW32 in the first switch capacitor common mode feedback module 105; the first delay signal Φa_sample_delay controlled switch has a twenty-first switch SWas1 and a twenty-second switch SWas2 in the first switched capacitor unit 101.

The switches controlled by the second sampling signal Φb_sample are provided with an eleventh switch SWbp1, a twelfth switch SWbp2, a thirteenth switch SWbp3, a fourteenth switch SWbp4, a sixteenth switch SWbn1, a seventeenth switch SWbn2, an eighteenth switch SWbn3 and a nineteenth switch SWbn4 in the second switched capacitor unit 102, and the switches controlled by the second holding signal Φb_hold are provided with a fifteenth switch SWbp5 and a twentieth switch SWbn5 in the second switched capacitor unit 102; the switches controlled by the second delay signal Φb_sample_delay have a twenty-third switch SWbs1 and a twenty-fourth switch SWbs2 in the second switched capacitor unit 102.

In the phase of the first sampling signal Φa_sample, the first switched capacitor unit 101 of the digital-to-analog conversion circuit samples differential input signals Vinp and Vinn of the first-stage sub-analog converter, the in-phase differential voltage signal Vinp is stored in the first capacitor Cap1, the second capacitor Cap2, the third capacitor Cap3 and the fourth capacitor Cap of the first switched capacitor unit 101, and the opposite-phase differential voltage signal Vinn is stored in the fifth capacitor Cap1, the sixth capacitor Cap2, the seventh capacitor Cap3 and the eighth capacitor Cap of the first switched capacitor unit 101.

Before the phase of the first hold signal Φa_hold arrives, the first switch SWap1, the second switch SWap2, the third switch SWap3, the fourth switch SWap4, the sixth switch SWan1, the seventh switch SWan2, the eighth switch SWan3, and the ninth switch SWan4 of the first switched capacitor unit 101 are turned off, and after a delay, the twenty-first switch SWas1 and the twenty-second switch SWas2 of the first switched capacitor unit 101 are turned off.

In the phase of the first holding signal phia_hold, the output code of the first-stage sub-analog-digital converter controls the switch of the first switched capacitor unit 101 of the digital-analog conversion circuit, and the analog voltage corresponding to the current output code is stored on a capacitor in the first switched capacitor unit 101; according to the principle of conservation of charge, the amount of charge accumulated by the capacitor of the first switched capacitor unit 101 on the phase of the first sampling signal Φa_sample is conserved with the amount of charge accumulated by the capacitor of the first switched capacitor unit 101 on the phase of the first holding signal Φa_hold, so that the output voltage of the digital-to-analog conversion circuit at the moment is four times the amount of analog voltage corresponding to the output voltage of the first-stage sub-analog-to-digital converter subtracted from the input voltage of the first-stage sub-analog-digital converter.

In the phase of the second sampling signal Φb_sample, the differential output voltage of the digital-to-analog conversion circuit is sampled and stored on the ninth capacitor Cbp1, tenth capacitor Cbp2, eleventh capacitor Cbp3, twelfth capacitor Cbfp, thirteenth capacitor Cbn1, fourteenth capacitor Cbn2, fifteenth capacitor Cbn3, sixteenth capacitor Cbfn of the second switched capacitor unit 102.

Before the second hold signal Φb_hold phase arrives, the eleventh switch SWbp1, the twelfth switch SWbp2, the thirteenth switch SWbp3, the fourteenth switch SWbp4, the sixteenth switch SWbn1, the seventeenth switch SWbn2, the eighteenth switch SWbn3, and the nineteenth switch SWbn4 of the second switched capacitor unit 102 are turned off first; after a delay, the twenty-third switch SWbs1 and the twenty-fourth switch SWbs2 of the second switched capacitor unit 102 are turned off again.

In the phase of the second hold signal Φb_hold, the output code of the second-stage sub-analog-digital converter controls the switch of the second switched capacitor unit 102 of the digital-analog conversion circuit, and the analog voltage corresponding to the current output code is stored on the capacitor in the second switched capacitor unit 102; according to the principle of conservation of charge, the amount of charge accumulated by the capacitor of the second switched capacitor unit 102 on the phase of the second sampling signal Φb_sample is conserved with the amount of charge accumulated by the capacitor of the second switched capacitor unit 102 on the phase of the second holding signal Φb_hold, so that the output voltage of the digital-to-analog conversion circuit at the moment is four times the amount of analog voltage corresponding to the output voltage of the second-stage sub-analog-digital converter subtracted from the input voltage of the second-stage sub-analog-digital converter.

More specifically, in the residual voltage amplifying process of the present invention, taking the same-directional end of the first switched capacitor unit 101 as an example, in the phase of the first sampling signal Φa_sample, the digital-to-analog conversion circuit samples the input voltage signal of the first stage of the sub-analog converter at the same-directional end of the first switched capacitor unit 101, and stores the same-directional end differential voltage signal Vinp on the first capacitor Cap1, the second capacitor Cap2, the third capacitor Cap3 and the fourth capacitor Cap of the first switched capacitor unit 101. In this stage, the first switch SWap1, the second switch SWap2, the third switch SWap3, the fourth switch SWap4 and the twenty-first switch SWas1 at the same direction end of the first switch capacitor unit 101 are closed, and the total charge amount accumulated on the first capacitor Cap1, the second capacitor Cap2, the third capacitor Cap3 and the fourth capacitor Cap is as follows:

wherein the method comprises the steps ofFor the input voltage of the same-phase end, the capacitance values of the first capacitor Cap1, the second capacitor Cap2 and the third capacitor Cap3 are the same, and +.>Instead of (I)>Is the capacitance value of the fourth capacitor Cafp, ">Is a common mode voltage.

Before the phase of the first holding signal phia_hold arrives, the switches of the same-direction end of the first switch capacitor unit 101, namely a first switch SWap1, a second switch SWap2, a third switch SWap3 and a fourth switch SWap4, are disconnected firstly; after a delay, the twenty-first switch SWas1 at the same direction of the first switched capacitor unit 101 is turned off.

In the phase of the first holding signal phia_hold, the output code of the first-stage sub-analog-digital converter controls the switch of the same-direction end of the first switched capacitor unit 101 of the digital-analog conversion circuit, and the analog voltage corresponding to the current output code is stored on a capacitor in the same-direction end of the first switched capacitor unit 101; in this stage, the total charge amounts accumulated on the first capacitor Cap1, the second capacitor Cap2, the third capacitor Cap3, and the fourth capacitor Cap by the first switched capacitor unit 101 are:

wherein the method comprises the steps ofFor the reference voltage of the sub-A/D converter, +.>And D2, D1 and D0 are respectively corresponding to three-bit output codes of the first-stage 3-bit Flash ADC.

According to the principle of conservation of charge, the charge amount accumulated by the capacitor at the same direction of the first switch capacitor unit 101 on the phase of the first sampling signal phia_sample is conserved with the charge amount accumulated by the capacitor of the first switch capacitor unit 101 on the phase of the first holding signal phia_hold, there is

Taking outEqual to Cafp, there are,

the output voltage of the digital-to-analog conversion circuit is four times of the input voltage of the first-stage sub-analog-to-digital converter minus the corresponding analog voltage of the output voltage of the first-stage sub-analog-to-digital converter.

In a preferred embodiment, as shown in fig. 3, the operational amplifier 103 includes a first PMOS transistor MP1, wherein the gate of the first PMOS transistor MP1 is biased at a second bias voltage Vbias 2; the grid electrode of the second PMOS tube MP2 is connected with the grid electrode of the first PMOS tube MP 1; the source electrode of the third PMOS tube MP3 is connected with the power supply signal Vdd, the grid electrode of the third PMOS tube MP3 is biased on a first bias voltage Vbias1, and the drain electrode of the third PMOS tube MP3 is connected with the source electrode of the first PMOS tube MP 1; the source electrode of the fourth PMOS tube MP4 is connected with the power supply signal Vdd, the grid electrode of the fourth PMOS tube MP4 is connected with the grid electrode of the third PMOS tube MP3, and the drain electrode of the fourth PMOS tube MP4 is connected with the source electrode of the second PMOS tube MP 2; the grid electrode of the first NMOS tube MN1 is connected with a first-stage switched capacitor common mode feedback module 104, and the source electrode of the first NMOS tube MN1 is grounded; the gate of the third NMOS transistor MN3 is the first phase difference input Vinpa of the operational amplifier 103; the gate of the fourth NMOS transistor MN4 is the first inverting differential input Vinna of the operational amplifier 103; the grid electrode of the fifth NMOS tube MN5 is connected with the first clock effective signal, the drain electrode of the fifth NMOS tube MN5 is connected with the source electrode of the third NMOS tube MN3, and the source electrode of the fifth NMOS tube MN5 is connected with the drain electrode of the first NMOS tube MN 1; the grid electrode of the sixth NMOS tube MN6 is connected with the first clock effective signal, the drain electrode of the sixth NMOS tube MN6 is connected with the source electrode of the fourth NMOS tube MN4, and the source electrode of the sixth NMOS tube MN6 is connected with the drain electrode of the first NMOS tube MN 1; a gate of the seventh NMOS transistor MN7 is the second non-inverting differential input Vinpb of the operational amplifier 103; the drain electrode of the seventh NMOS tube MN7 is connected with the drain electrode of the third NMOS tube MN 3; an eighth NMOS transistor MN8, a gate of the eighth NMOS transistor MN8 being a second inverting differential input Vinnb of the operational amplifier 103; the drain electrode of the eighth NMOS tube MN8 is connected with the drain electrode of the fourth NMOS tube MN 4; a ninth NMOS transistor MN9, wherein the grid electrode of the ninth NMOS transistor MN9 is connected with the second clock effective signal, the drain electrode of the ninth NMOS transistor MN9 is connected with the source electrode of the seventh NMOS transistor MN7, and the source electrode of the ninth NMOS transistor MN9 is connected with the drain electrode of the first NMOS transistor MN 1; a tenth NMOS transistor MN10, wherein the grid electrode of the tenth NMOS transistor MN10 is connected with the second clock effective signal, the drain electrode of the tenth NMOS transistor MN10 is connected with the source electrode of the eighth NMOS transistor MN8, and the source electrode of the tenth NMOS transistor MN10 is connected with the drain electrode of the first NMOS transistor MN 1; an eleventh NMOS transistor MN11, wherein the drain electrode of the eleventh NMOS transistor MN11 is connected with the drain electrode of the first PMOS transistor MP1, the grid electrode of the eleventh NMOS transistor MN11 is biased on a third bias voltage Vbias3, and the source electrode of the eleventh NMOS transistor MN11 is connected with the drain electrode of the third NMOS transistor MN 3; the twelfth NMOS transistor MN12, the drain electrode of the twelfth NMOS transistor MN12 is connected with the drain electrode of the second PMOS transistor MP2, the grid electrode of the twelfth NMOS transistor MN12 is connected with the eleventh NMOS transistor MN11, and the source electrode of the eleventh NMOS transistor MN11 is connected with the drain electrode of the third NMOS transistor MN 3.

In a preferred embodiment, the operational amplifier 103 further includes a fifth PMOS transistor MP5, a source of the fifth PMOS transistor MP5 is connected to the power supply signal Vdd, and a gate of the fifth PMOS transistor MP5 is connected to a gate of the third PMOS transistor MP 3; the source electrode of the sixth PMOS tube MP6 is connected with the power supply signal Vdd, and the grid electrode of the sixth PMOS tube MP6 is connected with the grid electrode of the fifth PMOS tube MP 5; the grid electrode of the second NMOS tube MN2 is connected with a second-stage switched capacitor common mode feedback module 105, and the source electrode of the second NMOS tube MN2 is grounded; a thirteenth NMOS transistor MN13, the gate of the thirteenth NMOS transistor MN13 is connected to the drain of the eleventh NMOS transistor MN11, the source of the thirteenth NMOS transistor MN13 is connected to the drain of the second NMOS transistor MN2, and the drain of the thirteenth NMOS transistor MN13 is connected to the drain of the fifth PMOS transistor MP5 and is the in-phase differential output terminal Voutp of the operational amplifier 103; a fourteenth NMOS transistor MN14, wherein the gate of the fourteenth NMOS transistor MN14 is connected to the drain of the twelfth NMOS transistor MN12, the source of the fourteenth NMOS transistor MN14 is connected to the drain of the second NMOS transistor MN2, and the drain of the fourteenth NMOS transistor MN14 is connected to the drain of the sixth PMOS transistor MP6 and is the inverting differential output terminal Voutn of the operational amplifier 103; the top polar plate of the first miller compensation capacitor C1 is connected with the drain electrode of the third NMOS tube MN3, and the bottom polar plate of the first miller compensation capacitor C1 is connected with the drain electrode of the thirteenth NMOS tube MN 13; the top plate of the second miller compensation capacitor C2 is connected with the drain electrode of the fourth NMOS tube MN4, and the bottom plate of the second miller compensation capacitor C2 is connected with the drain electrode of the fourteenth NMOS tube MN 14.

Preferably, the operational amplifier 103 of the present invention adopts a two-stage amplifying structure, and compared with the operational amplifier 103 adopting a single-stage amplifying but gain boosting technology, the operational amplifier 103 of the present invention has the advantages of simpler and more stable structure, small area, low power consumption, high efficiency, etc.

Specifically, in the above embodiment, the digital-to-analog conversion circuit core operational amplifier 103 has two pairs of inputs. The first pair of inputs being a first phase-difference input and a first inverting differential input, the op-amp 103 input switching to a first pair of inputs Vinpa and Vinna when receiving the first clock enable signal Φa; the second pair of inputs is a second in-phase differential input and a second out-of-phase differential input, and the op-amp input switches to a second pair of inputs Vinpb and Vinnb when receiving the second clock enable signal Φb.

In the above scheme, the operational amplifier 103 is used as a core module of a digital-to-analog conversion circuit, and includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a ninth NMOS transistor MN9, a tenth NMOS transistor MN10, an eleventh NMOS transistor MN11, a twelfth NMOS transistor MN12, a thirteenth NMOS transistor MN13, a fourteenth NMOS transistor MN14, a first miller compensation capacitor C1, a second miller compensation capacitor C2, a first switch capacitor common mode feedback module 104, and a second switch capacitor common mode feedback module 105.

The grid electrode of the first PMOS tube MP1 is connected with the grid electrode of the second PMOS tube MP2, and the grid electrode voltage of the first PMOS tube MP1 is biased on the second bias voltage Vbias 2; the grid electrode of the third PMOS tube MP3 is connected with the grid electrode of the fourth PMOS tube MP4, the grid electrode of the fifth PMOS tube MP5 and the grid electrode of the sixth PMOS tube MP6, and the grid electrode voltage is biased on the first bias voltage Vbias 1; the source electrode of the first PMOS tube MP1 is connected with the drain electrode of the third PMOS tube MP3, and the source electrode of the second PMOS tube MP2 is connected with the drain electrode of the fourth PMOS tube MP 4; the grid electrode of the eleventh NMOS tube MN11 is connected with the grid electrode of the twelfth NMOS tube MN12, the grid electrode voltage of the eleventh NMOS tube MN11 is biased on the third bias voltage Vbias3, the drain electrode of the eleventh NMOS tube MN11 is connected with the drain electrode of the first PMOS tube MP1, and the drain electrode of the twelfth NMOS tube MN12 is connected with the drain electrode of the second PMOS tube MP 2; the drain electrode of the third NMOS tube MN3 is connected with the drain electrode of the seventh NMOS tube MN7, the source electrode of the third NMOS tube MN3 is connected with the drain electrode of the fifth NMOS tube MN5, the source electrode of the seventh NMOS tube MN7 is connected with the drain electrode of the ninth NMOS tube MN9, the source electrode of the eighth NMOS tube MN8NM8 is connected with the drain electrode of the tenth NMOS tube MN10NM10, the source electrode of the fourth NMOS tube MN4 is connected with the drain electrode of the sixth NMOS tube MN6, the drain electrode of the first NMOS tube MN1 is connected with the source electrode of the fifth NMOS tube MN5, the source electrode of the ninth NMOS tube MN9, the source electrode of the tenth NMOS tube MN10 and the source electrode of the sixth NMOS tube MN6, and the gate electrode of the first NMOS tube MN1 is connected with the output of the first switch capacitor common mode feedback module 104; the drain electrode of the fifth PMOS tube MP5 is connected with the drain electrode of the thirteenth NMOS tube MN13, and the drain electrode of the sixth PMOS tube MP6 is connected with the drain electrode of the fourteenth NMOS tube MN 14; the grid electrode of the thirteenth NMOS tube MN13 is connected with the grid electrode of the eleventh NMOS tube MN11, and the grid electrode of the fourteenth NMOS tube MN14 is connected with the grid electrode of the twelfth NMOS tube MN 12; the drain electrode of the second NMOS tube MN2 is connected with the source electrode of the thirteenth NMOS tube MN13 and the source electrode of the fourteenth NMOS tube MN14, and the grid electrode of the second NMOS tube MN2 is connected with the output of the second switched capacitor common mode feedback module 105; two inputs of the first switch capacitor common mode feedback module 104 are respectively connected with the grid electrode of the eleventh NMOS tube MN11 and the grid electrode of the twelfth NMOS tube MN 12; two inputs of the second switched capacitor common mode feedback module 105 are respectively connected with the grid electrode of the thirteenth NMOS tube MN13 and the grid electrode of the fourteenth NMOS tube MN 14; the top polar plate of the first miller compensation capacitor C1 is connected with the drain electrode of the third NMOS tube MN3, and the bottom polar plate is connected with the drain electrode of the thirteenth NMOS tube MN 13; the top plate of the second miller compensation capacitor C2 is connected with the drain electrode of the fourth NMOS transistor MN4, and the bottom plate is connected with the drain electrode of the fourteenth NMOS transistor MN 14.

Specifically, the operational amplifier 103 includes a two-stage amplifier. The first-stage amplifier is composed of a first NMOS tube MN1, a third NMOS tube MN3 to a twelfth NMOS tube MN12, a first PMOS tube MP1 to a fourth PMOS tube MP4 and a first-stage switched capacitor common mode feedback module 104; the second-stage amplifier is composed of a second NMOS tube MN2, a thirteenth NMOS tube MN13, a fourteenth NMOS tube MN14, a fifth PMOS tube MP5, a sixth PMOS tube MP6, a first miller compensation capacitor C1, a second miller compensation capacitor C2 and a second-stage switch capacitor common mode feedback module 105.

In the first stage amplifier, a first NMOS tube MN1 is provided for providing bias working current for the stage amplifier; the first pair of inputs Vinpa and Vinna, when the first switched capacitor unit 101 is operating, the differential inputs of the operational amplifier 103 are switched to the first pair of differential inputs Vinpa and Vinna when the first clock enable signal Φa is active; the second pair of differential inputs Vinpb and Vinnb, when the second switched capacitor unit 102 is active, the op-amp differential input switches to the second pair of differential inputs Vinpb and Vinnb when the second clock enable signal Φb is active. The eleventh NMOS tube MN11 and the twelfth NMOS tube MN12 are common gate tubes, and form a common source-common gate amplifier stage with the first differential input tube pair, the third NMOS tube MN3 and the fourth NMOS tube MN4 or the second differential input tube pair, the seventh NMOS tube MN7 and the eighth NMOS tube MN 8; the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3 and the fourth PMOS tube MP4 form a cascode current mirror load; the differential input voltage signal is converted into a differential current signal through a common-source common-gate amplifying stage, the differential current signal is converted into a differential voltage signal through a common-source common-gate current mirror load, the first-stage amplifying process is completed, and the amplified differential voltage signal is sent to the differential input end of the second-stage amplifier; the first-stage switch capacitor common mode feedback circuit provides a stable direct current working point for the first-stage amplifier.

In the second stage amplifier, a second NMOS tube MN2 is provided for providing bias working current for the stage amplifier; the thirteenth NMOS tube MN13 and the fourteenth NMOS tube MN14 are differential input ends of the amplifier and are used for receiving differential voltage signals from the first-stage amplifier; the fifth PMOS tube MP5 and the sixth PMOS tube MP6 form a current mirror load; the differential input voltage signal is converted into a differential current signal through a differential input tube pair, and then is converted into a differential voltage signal through a current mirror load, and the differential voltage signal is sent to differential output ports Voutp and Voutn; the second-stage switched capacitor common mode feedback circuit provides a stable direct current working point for the first-stage amplifier; the first miller capacitance and the second miller capacitance are connected across the second stage amplifier input/output ports to provide stable frequency characteristics for closed loop applications of the first stage amplifier and the second stage amplifier.

In a preferred embodiment, the first stage switched capacitor common mode feedback module 104 includes a seventeenth capacitor C17, where a first end of the seventeenth capacitor C17 is connected to the drain of the eleventh NMOS transistor MN11 through a twenty-fifth switch SW25 controlled based on the first hold signal Φa_hold; an eighteenth capacitor C18, wherein a first end of the eighteenth capacitor C18 is connected to the drain of the twelfth NMOS transistor MN12 through a twenty-sixth switch SW26 controlled based on the first hold signal Φa_hold, and a second end of the eighteenth capacitor C18 is connected to a second end of the seventeenth capacitor C17; a nineteenth capacitor C19, where a first end of the nineteenth capacitor C19 is connected to the drain of the eleventh NMOS transistor MN11, and a second end of the nineteenth capacitor C19 is connected to the gate of the first NMOS transistor MN1 to output a first common mode feedback voltage; a twentieth capacitor C20, wherein a first end of the twentieth capacitor C20 is connected to the drain of the twelfth NMOS transistor MN12, and a second end of the twentieth capacitor C20 is connected to the second end of the nineteenth capacitor C19; a twenty-seventh switch SW27 controllably connected between the second terminal of the seventeenth capacitor C17 and the second terminal of the nineteenth capacitor C19 under the action of the first hold signal Φa_hold; the twenty-eighth switch SW28 is controllably connected between the first end of the seventeenth capacitor C17 and a first reference voltage Vref1 under the action of the first sampling signal Φa_sample; a twenty-ninth switch SW29 controllably connected between the first end of the eighteenth capacitor C18 and the first reference voltage Vref1 under the action of the first sampling signal Φa_sample; the thirty-first switch SW30 is controllably connected between the second terminal of the seventeenth capacitor C17 and a second reference voltage Vref2 under the action of the first sampling signal Φa_sample; the second-stage switched capacitor common mode feedback module 105 includes a twenty-first capacitor C21, wherein a first end of the twenty-first capacitor C21 is connected to the drain of the thirteenth NMOS transistor MN13 through a thirty-first switch SW31 controlled based on the first hold signal Φa_hold; a twenty-second capacitor C22, wherein a first end of the twenty-second capacitor C22 is connected to the drain of the fourteenth NMOS transistor MN14 through a thirty-second switch SW32 controlled based on the first hold signal Φa_hold, and a second end of the twenty-second capacitor C22 is connected to a second end of the twenty-first capacitor C21; a twenty-third capacitor C23, wherein a first end of the twenty-third capacitor C23 is connected with the drain electrode of the thirteenth NMOS tube MN13, and a second end of the twenty-third capacitor C23 is connected with the grid electrode of the second NMOS tube MN2 to output a second common mode feedback voltage; a first end of the twenty-fourth capacitor C24 is connected to the drain of the fourteenth NMOS transistor MN14, and a second end of the twenty-fourth capacitor C24 is connected to the second end of the twenty-third capacitor C23; a thirty-third switch SW33 controllably connected between the second terminal of the twenty-first capacitor C21 and the second terminal of the twenty-third capacitor C23 under the action of the first hold signal Φa_hold; a thirty-fourth switch SW34 controllably connected between the first end of the twenty-first capacitor C21 and the first reference voltage Vref1 under the action of the first sampling signal Φa_sample; a thirty-fifth switch SW35 controllably connected between the first end of the twenty-second capacitor C22 and the first reference voltage Vref1 under the action of the first sampling signal Φa_sample; the thirty-sixth switch SW36 is controllably connected between the second terminal of the twenty-first capacitor C21 and the second reference voltage Vref2 under the action of the first sampling signal Φa_sample.

Specifically, fig. 4 and 5 are schematic circuit diagrams of the switched capacitor common mode feedback module of the operational amplifier 103. The first switched capacitor common mode feedback module 104 and the second switched capacitor common mode feedback module 105 have the same circuit structure, wherein Voutp1 and Voutn1 are differential output ends of the first-stage amplifier; voutp2 and Voutn2 are differential output ends of the second-stage amplifier, vcmfb1 is a first common mode feedback voltage output end, and the first common mode feedback voltage is sent back to a tail current tube of the first-stage amplifier; vcmfb2 is a second common mode feedback voltage output end and sends the second common mode feedback voltage back to the tail current tube of the second-stage amplifier; a twenty eighth switch SW28, a twenty ninth switch SW29, and a thirty third switch SW30 in the first switched capacitor common mode feedback module 104, a thirty fourth switch SW34, a thirty fifth switch SW35, and a thirty sixth switch SW36 in the second switched capacitor common mode feedback module 105 are controlled by a first sampling signal Φa_sample, a twenty fifth switch SW25, a twenty sixth switch SW26, and a twenty seventh switch SW27 in the first switched capacitor common mode feedback module 104, a thirty first switch SW31, a thirty second switch SW32, and a thirty third switch SW33 in the second switched capacitor common mode feedback module 105 are controlled by a first hold signal Φa_hold, and the first sampling signal Φa_sample and the first hold signal Φa_hold are two-phase non-overlapping clocks; the seventeenth capacitor C17 and the eighteenth capacitor C18 have the same capacitance, the nineteenth capacitor C19 and the twentieth capacitor C20 have the same capacitance, the twenty-first capacitor C21 and the twenty-second capacitor C22 have the same capacitance, and the twenty-third capacitor C23 and the twenty-fourth capacitor C24 have the same capacitance.

In the present invention, the first switched capacitor common mode feedback module 104 is taken as an example, when the first sampling signal Φa_sample is high and the first holding signal Φa_hold is low, the nineteenth capacitor C19 is connected in parallel with the seventeenth capacitor C17 and is connected across Voutp1 and Vcmfb 1; the twentieth capacitor C20 is connected in parallel with the eighteenth capacitor C18 and is connected between Voutn1 and Vcmfb1 in a bridging manner; the total amount of charge Qtot1 accumulated on the capacitor at this time is,

the materials are arranged to be obtained,

wherein the seventeenth capacitor C17 and the eighteenth capacitor C18 have the same capacitanceInstead, the nineteenth capacitor C19 and the twentieth capacitor C20 have the same capacitance value and are +.>Instead of (I)>For the first common mode feedback voltage, ">And->Is the output voltage of the first stage amplifier.

According to the principle of conservation of charge, the charge quantity accumulated by the two-stage capacitor is the same, and the capacitor is obtained,

wherein the method comprises the steps ofFor the first reference voltage->Is the second reference voltage.

When the output common mode voltage of the first-stage or second-stage amplifier becomes high, the output of the first switch capacitor common mode feedback module 104 and the output of the second switch capacitor common mode feedback module 105 are also increased at the moment according to analysis, so that the bias current is increased, the output common mode voltage is reduced, and the effect of stabilizing the output common mode level of the amplifier is achieved; when the output common-mode voltage of the first-stage or second-stage amplifier becomes low, the output of the first switch capacitor common-mode feedback module 104 and the output of the second switch capacitor common-mode feedback module 105 are also reduced at the moment according to analysis, the bias current is reduced, the output common-mode voltage is increased, and therefore the effect of stabilizing the output common-mode level of the amplifier is achieved; wherein the two reference voltages Vref1 and Vref2 are used to provide the difference between the output common-mode voltage of the amplifier and the Vcmfb1 or Vcmfb2 voltage, which can be selected according to the actual circuit design.

The foregoing description is only illustrative of the preferred embodiments of the present invention and is not to be construed as limiting the scope of the invention, and it will be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. The operational amplifier sharing multiplying digital-to-analog conversion circuit is characterized by comprising a first switch capacitor unit (101), wherein the input end of the first switch capacitor unit (101) is connected with a differential voltage input signal, and the differential voltage input signal is sampled and an output code of a first-stage sub-analog-to-digital converter is received based on a first group of clock signals; -an operational amplifier (103) comprising a first pair of inputs, a second pair of inputs and a differential output, said first pair of inputs being controllably connected to the output of said first switched capacitor unit (101); the input end of the second switch capacitor unit (102) is connected with the differential output end of the operational amplifier (103), and the signals of the differential output end are sampled and the output code of a second-stage sub-analog-digital converter is received based on a second group of clock signals; the differential output end controllably outputs the residual voltage of the amplified first-stage sub-analog-digital converter when the first pair of inputs is connected with the output end of the first switched capacitor unit (101), and the differential output end controllably outputs the residual voltage of the amplified second-stage sub-analog-digital converter when the second pair of inputs is connected with the output end of the second switched capacitor unit (102).

2. The op-amp, shared multiple digital to analog conversion circuit of claim 1, wherein the first set of clock signals comprises a first sampling signal (Φa_sample) for controlling the first switched capacitor unit (101) to sample the differential voltage input signal; a first hold signal (Φa_hold) for controlling the first switched capacitor unit (101) to receive the output code of the first-stage sub-analog-digital converter, wherein the first switched capacitor unit (101) and the operational amplifier (103) are connected to generate and amplify a residual voltage of the first-stage sub-analog-digital converter according to the output code of the first-stage sub-analog-digital converter; the first hold signal (Φa_hold) and the first sample signal (Φa_sample) are two non-overlapping clocks; a first delay signal (Φa_sample_delay) which is a clock after the first sampling signal (Φa_sample) is delayed; the first delay signal (Φa_sample_delay) and the first hold signal (Φa_hold) are two non-overlapping clocks; the second set of clock signals includes a second sampling signal (Φb_sample) for controlling the second switched capacitor unit (102) to sample the signals at the differential output terminals; a second hold signal (Φb_hold) for controlling the second switched capacitor unit (102) to receive the output code of the second-stage sub-adc, the second switched capacitor unit (102) and the operational amplifier (103) being connected to generate and amplify a residual voltage of the second-stage sub-adc according to the output code of the second-stage sub-adc; the second hold signal (Φb_hold) and the second sample signal (Φb_sample) are two non-overlapping clocks; a second delay signal (Φb_sample_delay) which is a clock delayed by the second sampling signal (Φb_sample); the second delay signal (Φb_sample_delay) and the second hold signal (Φb_hold) are two non-overlapping clocks; the first sampling signal (Φa_sample) and the second holding signal (Φb_hold) are in phase, and the second sampling signal (Φb_sample) and the first holding signal (Φa_hold) are in phase.

3. An op-amp, shared multiple digital to analog conversion circuit according to claim 2, wherein the first switched capacitor unit (101) comprises a differential voltage non-inverting input (Vinp); a differential voltage inverting input (Vinn); the first end of the first capacitor (Cap 1) is provided with a connecting node for receiving an output code of the first-stage sub-analog-digital converter, and the second end of the first capacitor (Cap 1) is connected with a first phase difference input end (Vinpa) of the operational amplifier (103); a first switch (SWap 1) controllably connected between a first terminal of the first capacitor (Cap 1) and the differential voltage non-inverting input terminal (Vinp) under the action of the first sampling signal (Φa_sample); the first end of the second capacitor (Cap 2) is provided with a connecting node for receiving the output code of the first-stage sub-analog-digital converter, and the second end of the second capacitor (Cap 2) is connected with the first phase difference input end (Vinpa) of the operational amplifier (103); a second switch (SWap 2) controllably connected between a first terminal of the second capacitor (Cap 2) and the differential voltage non-inverting input terminal (Vinp) under the action of the first sampling signal (Φa_sample); the first end of the third capacitor (Cap 3) is provided with a connecting node for receiving the output code of the first-stage sub-analog-digital converter, and the second end of the third capacitor (Cap 3) is connected with the first phase difference input end (Vinpa) of the operational amplifier (103); a third switch (SWap 3) controllably connected between a first terminal of the third capacitor (Cap 3) and the differential voltage non-inverting input terminal (Vinp) under the action of the first sampling signal (Φa_sample); -a fourth capacitor (Cafp), the second end of which is connected to a first phase-difference input (Vinpa) of the operational amplifier (103); a fourth switch (SWap 4) controllably connected between a first terminal of the fourth capacitor (Cafp) and the differential voltage non-inverting input terminal (Vinp) under the action of the first sampling signal (Φa_sample); a fifth switch (SWap 5) controllably connected between the first terminal of the fourth capacitor (Cafp) and the inverted differential output (Voutn) of the operational amplifier (103) under the influence of the first hold signal (Φa_hold).

4. An op-amp, shared multiple digital to analog converter circuit according to claim 3, wherein the first switched capacitor unit (101) further comprises a fifth capacitor (Can 1), a first end of the fifth capacitor (Can 1) is provided with a connection node for receiving an output code of the first stage sub-analog to digital converter, and a second end of the fifth capacitor (Can 1) is connected to a first inverting differential input (Vinna) of the operational amplifier (103); a sixth switch (SWan 1) controllably connected between the first terminal of the fifth capacitor (Can 1) and the differential voltage inverting input terminal (Vinn) under the action of the first sampling signal (Φa_sample); a first end of the sixth capacitor (Can 2) is provided with a connection node for receiving an output code of the first-stage sub-analog-digital converter, and a second end of the sixth capacitor (Can 2) is connected with a first inverting differential input end (Vinna) of the operational amplifier (103); a seventh switch (SWan 2) controllably connected between the first terminal of the sixth capacitor (Can 2) and the differential voltage inverting input terminal (Vinn) under the action of the first sampling signal (Φa_sample); a seventh capacitor (Can 3), wherein a first end of the seventh capacitor (Can 3) is provided with a connection node for receiving an output code of the first-stage sub-analog-digital converter, and a second end of the seventh capacitor (Can 3) is connected with a first inverting differential input end (Vinna) of the operational amplifier (103); an eighth switch (SWan 3) controllably connected between a first terminal of the seventh capacitor (Can 3) and the differential voltage inverting input terminal (Vinn) under the action of the first sampling signal (Φa_sample); an eighth capacitor (Cafn), a second end of the eighth capacitor (Cafn) is connected with a first phase difference input end (Vinpa) of the operational amplifier (103); a ninth switch (SWan 4) controllably connected between the first terminal of the eighth capacitor (Cafn) and the differential voltage non-inverting input terminal (Vinp) under the action of the first sampling signal (Φa_sample); a tenth switch (SWan 5) controllably connected between the first terminal of the eighth capacitor (Cafn) and the inverted differential output terminal (Voutn) of the operational amplifier (103) under the influence of the first hold signal (Φa_hold).

5. An op-amp, shared multiple digital to analog converter circuit according to claim 2, wherein the second switched capacitor unit (102) comprises a ninth capacitor (Cbp 1), a first end of the ninth capacitor (Cbp 1) being provided with a connection node for receiving an output code of the second stage sub-analog to digital converter, a second end of the ninth capacitor (Cbp 1) being connected to a second non-inverting differential input (Vinpb) of the operational amplifier (103); an eleventh switch (SWbp 1) controllably connected between the first terminal of the ninth capacitor (Cbp 1) and the inverting differential output terminal (Voutn) of the operational amplifier (103) under the influence of the second sampling signal (Φb_sample); a tenth capacitor (Cbp 2), wherein a first end of the tenth capacitor (Cbp 2) is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the tenth capacitor (Cbp 2) is connected with a second non-inverting differential input end (Vinpb) of the operational amplifier (103); a twelfth switch (SWbp 2) controllably connected between a first terminal of the tenth capacitor (Cbp 2) and an inverting differential output terminal (Voutn) of the operational amplifier (103) under the action of the second sampling signal (Φb_sample); an eleventh capacitor (Cbp 3), wherein a first end of the eleventh capacitor (Cbp 3) is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the eleventh capacitor (Cbp 3) is connected with a second non-inverting differential input end (Vinpb) of the operational amplifier (103); a thirteenth switch (SWbp 3) controllably connected between the first terminal of the eleventh capacitor (Cbp 3) and the inverting differential output terminal (Voutn) of the operational amplifier (103) under the influence of the second sampling signal (Φb_sample); -a twelfth capacitance (Cbfp), a second end of the twelfth capacitance (Cbfp) being connected to a second non-inverting differential input (Vinpb) of the operational amplifier (103); a fourteenth switch (SWbp 4) controllably connected between the first terminal of the twelfth capacitor (Cbfp) and the inverting differential output terminal (Voutn) of the operational amplifier (103) under the influence of the second sampling signal (Φb_sample); a fifteenth switch (SWbp 5) is controllably connected between the first terminal of the twelfth capacitor (Cbfp) and the inverted differential output terminal (Voutn) of the operational amplifier (103) under the influence of the second hold signal (Φb_hold).

6. An op-amp, shared multiple digital to analog converter circuit according to claim 2, wherein the second switched capacitor unit (102) further comprises a thirteenth capacitor (Cbn 1), a first end of the thirteenth capacitor (Cbn 1) being provided with a connection node for receiving an output code of the second stage sub-analog to digital converter, a second end of the thirteenth capacitor (Cbn 1) being connected to a second inverting differential input (Vinnb) of the operational amplifier (103); a sixteenth switch (SWbn 1) controllably connected between a first terminal of the thirteenth capacitor (Cbn 1) and an in-phase differential output terminal (Voutp) of the operational amplifier (103) under the influence of the second sampling signal (Φb_sample); a fourteenth capacitor (Cbn 2), wherein a first end of the fourteenth capacitor (Cbn 2) is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the fourteenth capacitor (Cbn 2) is connected with a second inverting differential input end (Vinnb) of the operational amplifier (103); a seventeenth switch (SWbn 2) controllably connected between the first terminal of the fourteenth capacitor (Cbn 2) and the in-phase differential output terminal (Voutp) of the operational amplifier (103) under the influence of the second sampling signal (Φb_sample); a fifteenth capacitor (Cbn 3), wherein a first end of the fifteenth capacitor (Cbn 3) is provided with a connection node for receiving an output code of the second-stage sub-analog-digital converter, and a second end of the fifteenth capacitor (Cbn 3) is connected with a second inverting differential input end (Vinnb) of the operational amplifier (103); an eighteenth switch (SWbn 3) controllably connected between the first terminal of the fifteenth capacitor (Cbn 3) and the in-phase differential output terminal (Voutp) of the operational amplifier (103) under the influence of the second sampling signal (Φb_sample); -a sixteenth capacitance (Cbfn), a second terminal of the sixteenth capacitance (Cbfn) being connected to a second inverting differential input terminal (Vinnb) of the operational amplifier (103); a nineteenth switch (SWbn 4) controllably connected between the first terminal of the sixteenth capacitor (Cbfn) and the in-phase differential output terminal (Voutp) of the operational amplifier (103) under the influence of the second sampling signal (Φb_sample); a twentieth switch (SWbn 5) controllably connected between the first terminal of the sixteenth capacitor (Cbfn) and the in-phase differential output terminal (Voutp) of the operational amplifier (103) under the influence of the second hold signal (Φb_hold).

7. An op-amp, shared multiple digital to analog conversion circuit according to claim 2, wherein the first switched capacitor unit (101) further comprises a twenty-first switch (SWas 1) controllably connected between the first common-mode voltage (Vcm) and the first differential input (Vinpa) of the op-amp (103) under the action of the first delay signal (Φa_sample_delay); -a twenty-second switch (SWas 2) controllably connected between the first inverting differential input (Vinna) of the operational amplifier (103) and the common mode voltage (Vcm) under the action of the first delay signal (Φa_sample_delay); -the second switched capacitor unit (102) further comprises a twenty-third switch (SWbs 1) controllably connected between a second non-inverting differential input (Vinpb) of the operational amplifier (103) and the common mode voltage (Vcm) under the influence of the second delay signal (Φb_sample_delay); -a twenty-fourth switch (SWbs 2) controllably connected between the second inverting differential input (Vinnb) of the operational amplifier (103) and the common mode voltage (Vcm) under the action of the second delay signal (Φb_sample_delay).

8. The op-amp, shared multiple digital-to-analog conversion circuit of claim 2, wherein the op-amp (103) comprises a first PMOS transistor (MP 1), the gate of the first PMOS transistor (MP 1) being biased at a second bias voltage (Vbias 2); the grid electrode of the second PMOS tube (MP 2) is connected with the grid electrode of the first PMOS tube (MP 1); the source electrode of the third PMOS tube (MP 3) is connected with a power supply signal (Vdd), the grid electrode of the third PMOS tube (MP 3) is biased on a first bias voltage (Vbias 1), and the drain electrode of the third PMOS tube (MP 3) is connected with the source electrode of the first PMOS tube (MP 1); a fourth PMOS tube (MP 4), wherein the source electrode of the fourth PMOS tube (MP 4) is connected with the power supply signal (Vdd), the grid electrode of the fourth PMOS tube (MP 4) is connected with the grid electrode of the third PMOS tube (MP 3), and the drain electrode of the fourth PMOS tube (MP 4) is connected with the source electrode of the second PMOS tube (MP 2); the first NMOS tube (MN 1), the grid electrode of the first NMOS tube (MN 1) is connected with a first-stage switch capacitor common mode feedback module (104), and the source electrode of the first NMOS tube (MN 1) is grounded; a third NMOS transistor (MN 3), wherein a gate of the third NMOS transistor (MN 3) is a first phase-difference input terminal (Vinpa) of the operational amplifier (103); a fourth NMOS transistor (MN 4), the gate of the fourth NMOS transistor (MN 4) being the first inverting differential input (Vinna) of the operational amplifier (103); a fifth NMOS tube (MN 5), wherein the grid electrode of the fifth NMOS tube (MN 5) is connected with a first clock effective signal, the drain electrode of the fifth NMOS tube (MN 5) is connected with the source electrode of the third NMOS tube (MN 3), and the source electrode of the fifth NMOS tube (MN 5) is connected with the drain electrode of the first NMOS tube (MN 1); a sixth NMOS (MN 6), wherein a gate of the sixth NMOS (MN 6) is connected to the first clock enable signal, a drain of the sixth NMOS (MN 6) is connected to a source of the fourth NMOS (MN 4), and a source of the sixth NMOS (MN 6) is connected to a drain of the first NMOS (MN 1); a seventh NMOS transistor (MN 7), the gate of the seventh NMOS transistor (MN 7) being the second non-inverting differential input (Vinpb) of the operational amplifier (103); the drain electrode of the seventh NMOS tube (MN 7) is connected with the drain electrode of the third NMOS tube (MN 3); an eighth NMOS transistor (MN 8), the gate of the eighth NMOS transistor (MN 8) being the second inverting differential input (Vinnb) of the operational amplifier (103); the drain electrode of the eighth NMOS tube (MN 8) is connected with the drain electrode of the fourth NMOS tube (MN 4); a ninth NMOS transistor (MN 9), wherein a gate of the ninth NMOS transistor (MN 9) is connected to the second clock enable signal, a drain of the ninth NMOS transistor (MN 9) is connected to the source of the seventh NMOS transistor (MN 7), and a source of the ninth NMOS transistor (MN 9) is connected to the drain of the first NMOS transistor (MN 1); a tenth NMOS tube (MN 10), wherein a grid electrode of the tenth NMOS tube (MN 10) is connected with the second clock effective signal, a drain electrode of the tenth NMOS tube (MN 10) is connected with a source electrode of the eighth NMOS tube (MN 8), and a source electrode of the tenth NMOS tube (MN 10) is connected with a drain electrode of the first NMOS tube (MN 1); an eleventh NMOS (MN 11), wherein a drain of the eleventh NMOS (MN 11) is connected to the drain of the first PMOS (MP 1), a gate of the eleventh NMOS (MN 11) is biased at a third bias voltage (Vbias 3), and a source of the eleventh NMOS (MN 11) is connected to the drain of the third NMOS (MN 3); a twelfth NMOS tube (MN 12), wherein the drain electrode of the twelfth NMOS tube (MN 12) is connected with the drain electrode of the second PMOS tube (MP 2), the grid electrode of the twelfth NMOS tube (MN 12) is connected with the eleventh NMOS tube (MN 11), and the source electrode of the eleventh NMOS tube (MN 11) is connected with the drain electrode of the third NMOS tube (MN 3).

9. The operational amplifier sharing multiple digital-to-analog conversion circuit according to claim 8, wherein the operational amplifier (103) further comprises a fifth PMOS transistor (MP 5), a source of the fifth PMOS transistor (MP 5) is connected to the power supply signal (Vdd), and a gate of the fifth PMOS transistor (MP 5) is connected to a gate of the third PMOS transistor (MP 3); a sixth PMOS transistor (MP 6), a source of the sixth PMOS transistor (MP 6) is connected to the power supply signal (Vdd), and a gate of the sixth PMOS transistor (MP 6) is connected to a gate of the fifth PMOS transistor (MP 5); the grid electrode of the second NMOS tube (MN 2) is connected with a second-stage switch capacitor common mode feedback module (105), and the source electrode of the second NMOS tube (MN 2) is grounded; a thirteenth NMOS transistor (MN 13), wherein a gate of the thirteenth NMOS transistor (MN 13) is connected to a drain of the eleventh NMOS transistor (MN 11), a source of the thirteenth NMOS transistor (MN 13) is connected to a drain of the second NMOS transistor (MN 2), and a drain of the thirteenth NMOS transistor (MN 13) is connected to a drain of the fifth PMOS transistor (MP 5) and is an in-phase differential output terminal (Voutp) of the operational amplifier (103); a fourteenth NMOS (MN 14), wherein a gate of the fourteenth NMOS (MN 14) is connected to a drain of the twelfth NMOS (MN 12), a source of the fourteenth NMOS (MN 14) is connected to a drain of the second NMOS (MN 2), and a drain of the fourteenth NMOS (MN 14) is connected to a drain of the sixth PMOS (MP 6) and is an inverting differential output terminal (Voutn) of the operational amplifier (103); the top polar plate of the first miller compensation capacitor (C1) is connected with the drain electrode of the third NMOS tube (MN 3), and the bottom polar plate of the first miller compensation capacitor (C1) is connected with the drain electrode of the thirteenth NMOS tube (MN 13); the top polar plate of the second miller compensation capacitor (C2) is connected with the drain electrode of the fourth NMOS tube (MN 4), and the bottom polar plate of the second miller compensation capacitor (C2) is connected with the drain electrode of the fourteenth NMOS tube (MN 14).

10. The op-amp, shared multiple digital-to-analog conversion circuit of claim 9, wherein the first stage switched capacitor common mode feedback module (104) comprises a seventeenth capacitor (C17), a first end of the seventeenth capacitor (C17) being connected to the drain of the eleventh NMOS transistor (MN 11) through a twenty-fifth switch (SW 25) controlled based on the first hold signal (Φa_hold); an eighteenth capacitor (C18), wherein a first end of the eighteenth capacitor (C18) is connected to the drain of the twelfth NMOS transistor (MN 12) through a second sixteen switch (SW 26) controlled based on the first hold signal (Φa_hold), and a second end of the eighteenth capacitor (C18) is connected to a second end of the seventeenth capacitor (C17); a nineteenth capacitor (C19), wherein a first end of the nineteenth capacitor (C19) is connected to the drain of the eleventh NMOS transistor (MN 11), and a second end of the nineteenth capacitor (C19) is connected to the gate of the first NMOS transistor (MN 1) to output a first common mode feedback voltage; a twentieth capacitor (C20), wherein a first end of the twentieth capacitor (C20) is connected to the drain of the twelfth NMOS transistor (MN 12), and a second end of the twentieth capacitor (C20) is connected to the second end of the nineteenth capacitor (C19); a twenty-seventh switch (SW 27) controllably connected between the second terminal of the seventeenth capacitor (C17) and the second terminal of the nineteenth capacitor (C19) under the action of the first hold signal (Φa_hold); a twenty-eighth switch (SW 28) controllably connected between the first terminal of the seventeenth capacitor (C17) and a first reference voltage (Vref 1) under the action of the first sampling signal (Φa_sample); a twenty-ninth switch (SW 29) controllably connected between the first terminal of the eighteenth capacitor (C18) and the first reference voltage (Vref 1) under the action of the first sampling signal (Φa_sample); a thirty-first switch (SW 30) controllably connected between the second terminal of the seventeenth capacitor (C17) and a second reference voltage (Vref 2) under the action of the first sampling signal (Φa_sample); the second-stage switched capacitor common mode feedback module (105) comprises a twenty-first capacitor (C21), wherein a first end of the twenty-first capacitor (C21) is connected with the drain electrode of the thirteenth NMOS tube (MN 13) through a thirty-first switch (SW 31) controlled based on the first holding signal (Φa_hold); a twenty-second capacitor (C22), a first end of the twenty-second capacitor (C22) being connected to the drain of the fourteenth NMOS transistor (MN 14) through a thirty-second switch (SW 32) controlled based on the first hold signal (Φa_hold), a second end of the twenty-second capacitor (C22) being connected to a second end of the twenty-first capacitor (C21); a twenty-third capacitor (C23), wherein a first end of the twenty-third capacitor is connected to the drain electrode of the thirteenth NMOS transistor (MN 13), and a second end of the twenty-third capacitor (C23) is connected to the gate electrode of the second NMOS transistor (MN 2) to output a second common mode feedback voltage; a twenty-fourth capacitor (C24), wherein a first end of the twenty-fourth capacitor (C24) is connected to the drain of the fourteenth NMOS transistor (MN 14), and a second end of the twenty-fourth capacitor (C24) is connected to the second end of the twenty-third capacitor (C23); a thirty-third switch (SW 33) controllably connected between the second terminal of the twenty-first capacitor (C21) and the second terminal of the twenty-third capacitor (C23) under the action of the first hold signal (Φa_hold); a thirty-fourth switch (SW 34) controllably connected between the first terminal of the twenty-first capacitor (C21) and the first reference voltage (Vref 1) under the action of the first sampling signal (Φa_sample); a thirty-fifth switch (SW 35) controllably connected between the first terminal of the twenty-second capacitor (C22) and the first reference voltage (Vref 1) under the action of the first sampling signal (Φa_sample); a thirty-sixth switch (SW 36) controllably connected between the second terminal of the twenty-first capacitor (C21) and the second reference voltage (Vref 2) under the action of the first sampling signal (Φa_sample).