CN104242936A - Pipelined analog-digital converter - Google Patents
Pipelined analog-digital converter Download PDFInfo
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- CN104242936A CN104242936A CN201310231648.5A CN201310231648A CN104242936A CN 104242936 A CN104242936 A CN 104242936A CN 201310231648 A CN201310231648 A CN 201310231648A CN 104242936 A CN104242936 A CN 104242936A
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- analog signal
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Abstract
The invention discloses a pipelined analog-digital converter. Each module comprises a first sample hold circuit, a second sample hold circuit and an operational amplifier with two differential input ends. The modules can work in a first sample hold mode and a second sample hold mode. In the first sample hold mode, the second sample hold circuits work in the sampling mode, the first sample hold circuits work in the amplification mode, and the operational amplifiers are connected with the first sample hold circuits, conduct allowance amplification and output analog signals; in the second sample hold mode, the first sample hold circuits work in the sampling mode, the second sample hold circuits work in the amplification mode, and the operational amplifiers are connected with the second sample hold circuits, conduct allowance amplification and output analog signals. By means of the pipelined analog-digital converter, the two sample hold modules can conduct sampling alternately, each operational amplifier can be connected with one sample hold module all the time and can work in an amplification period, idling of the operational amplifiers can be avoided, and the working speed of the whole ADC can be accordingly increased.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, particularly relate to a kind of production line analog-digital converter (ADC).
Background technology
Pipeline ADC is a kind of structure that can realize realizing again at a high speed suitable resolution, is widely used in electronic system, simultaneously also more and more higher to the requirement of performance.
As shown in Figure 1, be the structure chart of existing pipeline ADC; Module (S/H) 101 is kept to carry out analog input by sampling, input analog signal through multiple grades of modules (stage) as level module 1, level module i102i, level module n102n and flash level module 103 etc. carry out Analog-digital Converter, each grade of module generation 1 or multistation digital signal, as K
1bits, K
ibits, K
nbits, K
n+1bits, the digital signal obtained after conversion to be input in shift register 104 and by exporting after digital correction circuit 105, and clock generation circuit 106 is for generation of clock signal thus control the mode of operation of level module.
As shown in Figure 2, be the structure chart of level module in Fig. 1; Level module 102i comprises sub-ADCi104 and residue-gain-circuit (MDAC) 105, the analog signal V of input
indigital signal K is converted to through sub-ADCi104
ibits; Residue-gain-circuit 105 comprises sampling and keeps module 106, and subnumber weighted-voltage D/A converter (DAC) i107 and operational amplifier 108, sub-DACi107 is by digital signal K
ibits is converted into analog quantity, sampling keeps the analog signal Vin of module 106 to input to sample, the analog quantity that analog signal Vin and sub-DACi107 exports subtracts each other rear generation one surplus by subtraction block, and this surplus is undertaken amplifying rear outputting analog signal V by operational amplifier 108
out., analog signal V
outas the input analog signal of the level module of next stage.
In order to the effect in production line analog-digital converter of amplifier and operational amplifier is described, first analyze the course of work of MDAC105.As shown in Figure 2, the effect of residue-gain-circuit has 3 points: 1, subtraction function.Deduct this value with the analog output value Vin of previous stage to quantize to enter the analogue value after sub-DACi107 conversion again to obtain surplus through sub-ADCi104.2, gain function.Same reference voltage source can be used the surplus of every grade will to be multiplied by a suitable factor to make every grade.3, sampling keeps function.
In order to easy analysis, for the MDAC unit of 1.5 every grade.As shown in Figure 3A, the sampling configuration circuit diagram of level module when be MDAC in Fig. 2 being 1.5; Level module comprises electric capacity C
fand C
s, sub-DAC107a and operational amplifier 108a.Sub-DAC107a selects voltage V by three switches
ref, o and-V
refrealize, and output voltage signal V
dac.Switch 109 and 110 is controlled by clock signal one Φ 1, and switch 111 is controlled by clock signal two Φ 2.When sampling configuration, switch 109 and 110 is connected, input signal V
ibe sampled electric capacity C
fand C
s; Switch 111 disconnects, and now operational amplifier 108a leaves unused.Now the electric charge of amplifier input is:
Q
1＝-(C
s+C
f)V
i （1）
As shown in Figure 3 B, the Holdover mode of level module and amplification mode circuit diagram when be MDAC in Fig. 2 being 1.5; When amplification mode, switch 109 and 110 disconnects, and switch 111 is connected, capacitor C
ftop crown receives the output of operational amplifier 108a by switch 111, and amplifier is in running order.C
stop crown can receive output and the voltage signal V of sub-DAC107a
dac.Now the electric charge of amplifier input is:
Q
2＝(V
x-V
dac)C
s+(V
x-V
o)C
f （2）
V in formula (2)
o=A × (0-V
x), A is the finite DC gain of amplifier, V
xfor the input of operational amplifier 108a and the voltage of inverting input, the positive input end grounding of operational amplifier 108a.
By principle of charge conservation, Q
1=Q
2, can obtain:
In formula (3), β is that its value of feedback factor equals C
f/ (C
f+ C
s).
Again by first approximation A/ (β A+1) ≈ 1/ β × (1-1/ β A), bring in formula (3) and can obtain:
Suppose C
s=C
f, and electric capacity coupling, the multiplication factor A of operational amplifier 108a is tending towards infinitely great, as input signal V
ithe V when different value
dacoutput get different reference voltage (-Vref, 0, Vref), just can obtain formula (5):
In formula (5), Q corresponds to the digital signal formed after sub-ADC changes by input signal Vi.
As shown in Figure 3 C, be circuit timing diagram in Fig. 3 A and Fig. 3 B; Clock signal one Φ 1 and clock signal two Φ 2 is mutual not overlap signal, and wherein the time of the high level of clock signal one Φ 1 is less than the low level time of clock signal two Φ 2, the time of the high level of clock signal two Φ 2 is less than the low level time of clock signal one Φ 1.
As the above analysis, the level module work of production line analog-digital converter is when sampling configuration, and amplifier is left unused; When being operated in amplification mode, amplifier work.
As shown in Figure 4, be the operational amplifier configuration figure adopted in existing level module; Operational amplifier 108a adopts Telescopic folding cascodes, wherein NMOS tube M1 and M3 forms cascodes, NMOS tube M2 and M4 and also forms cascodes, the grid of NMOS tube M1 and M2 realizes the input of differential signal Vinp and Vinn, and the drain electrode of NMOS tube M3 and M4 realizes the output of differential signal Vout-and Vout+.PMOS M5 and M7 to be connected between the drain electrode of NMOS tube M3 and supply voltage VDD and as active load, PMOS M6 and M8 to be connected between the drain electrode of NMOS tube M4 and supply voltage VDD and as active load, the grid structure bias voltage Vb of PMOS M7 and M8.Booster amplifier A1 is to the gate bias of NMOS tube M3 and M4 and realize gain bootstrap, and booster amplifier A2 is to the gate bias of PMOS M5 and M6 and realize gain bootstrap.
In prior art, amplifier is idle in the sampling period, only plays a role in the amplification cycle.Not only fully do not use amplifier like this, and be unfavorable for the raising of ADC operating rate.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of production line analog-digital converter, and the amplifier of module at different levels can be made to always work in amplification mode, thus can improve the operating rate of overall ADC.
For solving the problems of the technologies described above, production line analog-digital converter provided by the invention comprises the Pipeline ADC structure be made up of multiple grades of modules, and described level module at different levels all comprises an input end of analog signal, digital signal output end and analog signal output.
The input end of analog signal of level module described in the first order connects external analog signal, and the input end of analog signal of other the described level module at different levels outside the first order connects the analog signal output of level module described in upper level.
Described level module at different levels comprises sub-adc converter and residue-gain-circuit, and input analog signal is converted to digital signal and exports by the sub-adc converter of described level module at different levels.
The residue-gain-circuit of described level module at different levels comprises subnumber weighted-voltage D/A converter, sampling hold circuit one, sampling hold circuit two and operational amplifier.
The described digital signal exported is changed into intermediate analog signal by described subnumber weighted-voltage D/A converter, obtains analog signal surplus and form outputting analog signal after this analog signal surplus being amplified by described operational amplifier after described input analog signal and described intermediate analog signal are subtracted each other by the residue-gain-circuit of described level module at different levels.
Described operational amplifier comprises two groups of differential input ends, input pipe respectively with the first switching tube series connection of first group of differential input end, and described first switching tube carries out switching over by the first clock signal; The input pipe of second group of differential input end is connected with second switch pipe respectively, and described second switch pipe carries out switching over by second clock signal, and described first clock signal and described second clock signal are mutual not overlapping clock signal.
The output of described sampling hold circuit one is connected to described first group of differential input end, and the output of described sampling hold circuit two is connected to described second group of differential input end.
The residue-gain-circuit of described level module at different levels comprises sampling Holdover mode one and sampling Holdover mode 2 two kinds of mode of operations, and two kinds of mode of operations are switched by described first clock signal and described second clock signal.
At described sampling Holdover mode for the moment, input pipe and described first switching tube of described first group of differential input end are connected, the input pipe of described second group of differential input end and described second switch pipe disconnect, described sampling hold circuit two is operated in sampling configuration, described sampling hold circuit one is operated in amplification mode, and described sampling hold circuit one to be sampled by described first group of differential input end and obtained analog signal surplus after the described input analog signal that obtains and described intermediate analog signal are subtracted each other and form outputting analog signal after amplifying by described operational amplifier.
When described sampling Holdover mode two, the input pipe of described second group of differential input end and described second switch pipe are connected, input pipe and described first switching tube of described first group of differential input end disconnect, described sampling hold circuit one is operated in sampling configuration, described sampling hold circuit two is operated in amplification mode, and described sampling hold circuit two to be sampled by described second group of differential input end and obtained analog signal surplus after the described input analog signal that obtains and described intermediate analog signal are subtracted each other and form outputting analog signal after amplifying by described operational amplifier.
Further improvement is, described sampling hold circuit one and described sampling hold circuit two all adopt identical sampling hold circuit cellular construction, and described sampling hold circuit cellular construction comprises: electric capacity one and electric capacity two.
The first end of described electric capacity one is connected with the first end of described electric capacity two and as the output of described sampling hold circuit cellular construction.
Second end of described electric capacity one connects described input analog signal by switch one, the second end of described electric capacity two connects described input analog signal by switch two, and the first end of described electric capacity one and described electric capacity two is by switch three ground connection.
Second end of described electric capacity one connects the output of described operational amplifier by switch four, the second end of described electric capacity two connects described intermediate analog signal by switch five.
Described switch one, described switch two, described switch three all connect first group of clock signal, and described switch four is all connected second group of clock signal with described switch five, and described first group of clock signal and described second group of clock signal are clock signal not overlapping each other.
Described switch one, described switch two and described switch three are connected, and when described switch four and described switch five disconnect, described sampling hold circuit cellular construction works in sampling configuration.
Described switch one, described switch two and described switch three disconnect, and when described switch four and described switch five are connected, described sampling hold circuit cellular construction works in amplification mode.
Described first group of clock signal that described sampling hold circuit one connects is described second clock signal, and described second group of clock signal that described sampling hold circuit one connects is described first clock signal.
Described first group of clock signal that described sampling hold circuit two connects is described first clock signal, and described second group of clock signal that described sampling hold circuit two connects is described second clock signal.
Further improvement is, described level module at different levels is fully differential structure, described input analog signal, described intermediate analog signal and described outputting analog signal all fully differential signals; The positive phase signals of described outputting analog signal is exported by the positive reversed-phase output of described operational amplifier respectively.
Described sampling hold circuit one and described sampling hold circuit two are made up of two described sampling hold circuit cellular constructions all respectively, are respectively for the signal annexation of two the described sampling hold circuit cellular constructions of any one in described sampling hold circuit one and described sampling hold circuit two:
First sampling hold circuit cellular construction connects the reversed-phase output of the normal phase input end in one group of differential input end of the positive phase signals of described input analog signal, the inversion signal of described intermediate analog signal, described operational amplifier, described operational amplifier respectively.
Second sampling hold circuit cellular construction connects the positive output end of the inverting input in one group of differential input end of the inversion signal of described input analog signal, the positive phase signals of described intermediate analog signal, described operational amplifier, described operational amplifier respectively.
Further improvement is, described operational amplifier adopts Telescopic folding cascodes.
Further improvement is, described operational amplifier comprises:
The first cascade be made up of the first NMOS tube, the second NMOS tube and the 3rd NMOS tube amplifies branch road, the normal phase input end that described first NMOS tube is input pipe, grid is first group of differential input end, the source ground of described first NMOS tube; Described second NMOS tube is the first switching tube, and the grid of described second NMOS tube connects the first clock signal, and the source electrode of described second NMOS tube connects the drain electrode of described first NMOS tube; The source electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described second NMOS tube, and the drain electrode of described 3rd NMOS tube, as the reversed-phase output of described operational amplifier, connects the first active load between the drain electrode of described 3rd NMOS tube and supply voltage.
The second cascade be made up of the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube amplifies branch road, the inverting input that described 4th NMOS tube is input pipe, grid is first group of differential input end, the source ground of described 4th NMOS tube; Described 5th NMOS tube is the first switching tube, and the grid of described 5th NMOS tube connects the first clock signal, and the source electrode of described 5th NMOS tube connects the drain electrode of described first NMOS tube; The source electrode of described 6th metal-oxide-semiconductor connects the drain electrode of described 5th NMOS tube, and the drain electrode of described 6th NMOS tube, as the positive output end of described operational amplifier, connects the second active load between the drain electrode of described 6th NMOS tube and supply voltage.
7th NMOS tube and the 8th NMOS tube, the 3rd cascade be made up of described 7th NMOS tube, described 8th NMOS tube and the 3rd NMOS tube amplifies branch road, the normal phase input end that described 7th NMOS tube is input pipe, grid is second group of differential input end, the source ground of described 7th NMOS tube; Described 8th NMOS tube is second switch pipe, and the grid of described 8th NMOS tube connects second clock signal, and the source electrode of described 8th NMOS tube connects the drain electrode of described 7th NMOS tube; The source electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described 8th NMOS tube.
9th NMOS tube and the tenth NMOS tube, the 4th cascade be made up of described 9th NMOS tube, described tenth NMOS tube and the 6th NMOS tube amplifies branch road, the inverting input that described 9th NMOS tube is input pipe, grid is second group of differential input end, the source ground of described 9th NMOS tube; Described tenth NMOS tube is second switch pipe, and the grid of described tenth NMOS tube connects second clock signal, and the source electrode of described tenth NMOS tube connects the drain electrode of described 9th NMOS tube; The source electrode of described 6th metal-oxide-semiconductor connects the drain electrode of described tenth NMOS tube.
First booster amplifier, the inverting input of described first booster amplifier connects the source electrode of described 3rd NMOS tube, the grid of described 3rd NMOS tube of positive output end connection, the grid that normal phase input end connects the source electrode of described 6th NMOS tube, reversed-phase output connects described 6th NMOS tube of described first booster amplifier.
Further improvement is, described first active load is made up of the first PMOS and the second PMOS, the drain electrode of described first PMOS connects the drain electrode of described 3rd NMOS tube, the source electrode of described first PMOS connects the drain electrode of described second PMOS, and the source electrode of described second PMOS connects supply voltage.
Described second active load is made up of the 3rd PMOS and the 4th PMOS, the drain electrode of described 3rd PMOS connects the drain electrode of described 6th NMOS tube, the source electrode of described 3rd PMOS connects the drain electrode of described 4th PMOS, and the source electrode of described 4th PMOS connects supply voltage; Described second PMOS is connected identical bias voltage with the grid of described 4th PMOS.
Second booster amplifier, the grid that normal phase input end connects the source electrode of described first PMOS, reversed-phase output connects described first PMOS of described second booster amplifier; The inverting input of described second booster amplifier connects the source electrode of described 3rd PMOS, the grid of described 3rd PMOS of positive output end connection.
Further improvement is, described operational amplifier also comprises the 11 NMOS tube and the 12 NMOS tube, the drain electrode of described 11 NMOS tube connects the source electrode of described first NMOS tube, the grid of described 11 NMOS tube connects the common mode feedback signal of described operational amplifier, the drain electrode of described 12 NMOS tube connects the source electrode of described 4th NMOS tube, the grid of described 12 NMOS tube connects reference signal, the source ground of described 11 NMOS tube and described 12 NMOS tube.
Module at different levels of the present invention is kept module by employing two sampling and the input of operational amplifier is set to two groups of differential input ends, can realize two samplings keeps modules to hocket sampling, and operational amplifier can keep model calling with a sampling and is operated in the amplification cycle all the time, so the present invention can avoid the idle of amplifier, make the amplifier of module at different levels always work in amplification mode, thus the operating rate of overall ADC can be improved.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation:
Fig. 1 is the structure chart of existing pipeline ADC;
Fig. 2 is the structure chart of the level module in Fig. 1;
The sampling configuration circuit diagram of level module that Fig. 3 A is the MDAC in Fig. 2 when being 1.5;
The Holdover mode circuit diagram of level module that Fig. 3 B is the MDAC in Fig. 2 when being 1.5;
Fig. 3 C is the circuit timing diagram in Fig. 3 A and Fig. 3 B;
Fig. 4 is the operational amplifier configuration figure adopted in existing level module;
Fig. 5 A is sampling Holdover mode one circuit diagram of the level module of embodiment of the present invention production line analog-digital converter;
Fig. 5 B is sampling Holdover mode two circuit diagram of the level module of embodiment of the present invention production line analog-digital converter;
Fig. 5 C is the circuit timing diagram in Fig. 5 A and Fig. 5 B;
Fig. 6 is the operational amplifier configuration figure adopted in the level module of the embodiment of the present invention.
Embodiment
As shown in Figure 5A, be sampling Holdover mode one circuit diagram of level module of embodiment of the present invention production line analog-digital converter; As shown in Figure 5 B, be sampling Holdover mode two circuit diagram of level module of embodiment of the present invention production line analog-digital converter.Embodiment of the present invention production line analog-digital converter comprises the Pipeline ADC structure be made up of multiple grades of modules, and described level module at different levels all comprises input end of analog signal, digital signal output end and analog signal output.
The input end of analog signal of level module described in the first order connects external analog signal, and the input end of analog signal of other the described level module at different levels outside the first order connects the analog signal output of level module described in upper level.
Described level module at different levels comprises sub-adc converter and residue-gain-circuit, and input analog signal inn and inp is converted to digital signal and exports by the sub-adc converter of described level module at different levels, and input analog signal inn and inp is a pair differential signal.
The residue-gain-circuit of described level module at different levels comprises subnumber weighted-voltage D/A converter, sampling hold circuit 1, sampling hold circuit 22 and operational amplifier 3.
The described digital signal exported is changed into intermediate analog signal Vdacn and Vdacp by described subnumber weighted-voltage D/A converter, and intermediate analog signal Vdacn and Vdacp is a pair differential signal.Obtain analog signal surplus after described input analog signal inn and inp and described intermediate analog signal Vdacn and Vdacp subtracts each other by the residue-gain-circuit of described level module at different levels and form outputting analog signal outn and outp after this analog signal surplus being amplified by described operational amplifier 3, outputting analog signal outn and outp is a pair differential signal.
Described operational amplifier 3 comprises two groups of differential input ends, and two groups of differential input ends are respectively first group of differential input end inn1 and inp1 and second group differential input end inn2 and inp2.Input pipe respectively with the first switching tube series connection of first group of differential input end inn1 and inp1, described first switching tube carries out switching over by the first clock signal phil; The input pipe of second group of differential input end inn2 and inp2 is connected with second switch pipe respectively, described second switch pipe carries out switching over by second clock signal phi2, and described first clock signal phil and described second clock signal phi2 is mutual not overlapping clock signal.
The output of described sampling hold circuit 1 is connected to described first group of differential input end inn1 and inp1, and the output of described sampling hold circuit 22 is connected to described second group of differential input end inn2 and inp2.
The residue-gain-circuit of described level module at different levels comprises sampling Holdover mode one and sampling Holdover mode 2 two kinds of mode of operations, and two kinds of mode of operations are switched by described first clock signal phil and described second clock signal phi2.
As shown in Figure 5A, at described sampling Holdover mode for the moment, input pipe and described first switching tube of described first group of differential input end inn1 and inp1 are connected, the input pipe of described second group of differential input end inn2 and inp2 and described second switch pipe disconnect, described sampling hold circuit 22 is operated in sampling configuration, described sampling hold circuit 1 is operated in amplification mode, described sampling hold circuit 1 to be sampled by described first group of differential input end and is obtained analog signal surplus after the described input analog signal inn and inp that obtains and described intermediate analog signal Vdacn and Vdacp subtracts each other and carry out amplifying rear formation outputting analog signal outn and outp by described operational amplifier 3.
As shown in Figure 5A, when described sampling Holdover mode two, the input pipe of described second group of differential input end inn2 and inp2 and described second switch pipe are connected, input pipe and described first switching tube of described first group of differential input end inn1 and inp1 disconnect, described sampling hold circuit 1 is operated in sampling configuration, described sampling hold circuit 22 is operated in amplification mode, described sampling hold circuit 22 to be sampled by described second group of differential input end inn2 and inp2 and is obtained analog signal surplus after the described input analog signal inn and inp that obtains and described intermediate analog signal Vdacn and Vdacp subtracts each other and carry out amplifying rear formation outputting analog signal outn and outp by described operational amplifier 3.
As shown in Figure 5A, described sampling hold circuit 1 and described sampling hold circuit 22 all adopt identical sampling hold circuit cellular construction 4, and described sampling hold circuit cellular construction 4 comprises: electric capacity 1 and electric capacity 26.
The first end of described electric capacity 1 is connected with the first end of described electric capacity 26 and as the output of described sampling hold circuit cellular construction 4.
Second end of described electric capacity 1 connects described input analog signal inn or inp by switch 1, the second end of described electric capacity 26 connects described input analog signal inn or inp by switch 28, and the first end of described electric capacity 1 and described electric capacity 26 is by switch 39 ground connection.
Second end of described electric capacity 1 connects the output of described operational amplifier 3 by switch 4 10, the second end of described electric capacity 26 connects described intermediate analog signal Vdacn or Vdacp by switch 5 11.
Described switch 1, described switch 28, described switch 39 all connect first group of clock signal, described switch 4 10 is all connected second group of clock signal with described switch 5 11, and described first group of clock signal and described second group of clock signal are clock signal not overlapping each other.
Described switch 1, described switch 28 and described switch 39 are connected, and when described switch 4 10 and described switch 5 11 disconnect, described sampling hold circuit cellular construction 4 works in sampling configuration.
Described switch 1, described switch 28 and described switch 39 disconnect, and when described switch 4 10 and described switch 5 11 are connected, described sampling hold circuit cellular construction 4 works in amplification mode.
Described first group of clock signal that described sampling hold circuit 1 connects is described second clock signal phi2, and described second group of clock signal that described sampling hold circuit 1 connects is described first clock signal phil; Namely the described switch 1 of described sampling hold circuit 1, described switch 28, described switch 39 all connect described second clock signal phi2, and described switch 4 10 is all connected described first clock signal phil with described switch 5 11.
Described first group of clock signal that described sampling hold circuit 22 connects is described first clock signal phil, and described second group of clock signal that described sampling hold circuit 22 connects is described second clock signal phi2.Namely the described switch 1 of described sampling hold circuit 22, described switch 28, described switch 39 all connect described first clock signal phil, and described switch 4 10 and described switch 5 11 are all connected described second clock signal phi2.
As fig. 5 a and fig. 5b, the at different levels described level module of the embodiment of the present invention is fully differential structure, described input analog signal inn and inp, described intermediate analog signal Vdacn and Vdacp and described outputting analog signal outn and outp all fully differential signals; The positive phase signals of described outputting analog signal outn and outp is exported by the positive reversed-phase output of described operational amplifier 3 respectively.
Described sampling hold circuit 1 and described sampling hold circuit 22 are made up of two described sampling hold circuit cellular constructions 4 all respectively, are respectively for the signal annexation of two the described sampling hold circuit cellular constructions 4 of any one in described sampling hold circuit 1 and described sampling hold circuit 22:
First sampling hold circuit cellular construction 4 connects the reversed-phase output outn of normal phase input end inp1 (corresponding to described sampling hold circuit 1) in one group of differential input end of the positive phase signals inp of described input analog signal, the inversion signal Vdacn of described intermediate analog signal, described operational amplifier 3 or inp2 (corresponding to described sampling hold circuit 1), described operational amplifier 3 respectively.
Second sampling hold circuit cellular construction 4 connects the positive output end outp of inverting input inn1 (corresponding to described sampling hold circuit 1) in one group of differential input end of the inversion signal inn of described input analog signal, the positive phase signals Vdacp of described intermediate analog signal, described operational amplifier 3 or inn2 (corresponding to described sampling hold circuit 1), described operational amplifier 3 respectively.
As described in Fig. 5 C, it is the circuit timing diagram in Fig. 5 A and Fig. 5 B; Described first clock signal phi1 and described second clock signal phi2 is mutual not overlap signal, and described first clock signal phi1 controls the first switching tube, and the signal corresponding to first group of differential input end inn1 and inp1 inputs.Described second clock signal phi2 controls second switch pipe, and the signal corresponding to second group of differential input end inp2 and inn2 inputs.Described first clock signal phi1 and described second clock signal phi2 also controls described sampling and keeps module 1 and the described all switches kept in module 22 of sampling, and all switches are described switch 1, described switch 28, described switch 39, described switch 4 10 and described switch 5 11 in each described sampling hold circuit cellular construction 4.In fig. 5, described first clock signal phi1 is high level, described second clock signal phi2 is low level, therefore described first group of differential input end inn1 and inp1 connects and realizes signal input, and described second group of differential input end inp2 and inn2 disconnects and inoperative, now described sampling keeps module 1 to be operated in amplification mode, and described sampling keeps module 22 to be operated in sampling configuration.In figure 5b, described first clock signal phi1 is low level, described second clock signal phi2 is high level, therefore described first group of differential input end inn1 and inp1 disconnects and inoperative, and described second group of differential input end inp2 and inn2 connection realizes signal input, now described sampling keeps module 1 to be operated in sampling configuration, and described sampling keeps module 22 to be operated in amplification mode.
As shown in Figure 6, be the operational amplifier configuration figure adopted in the level module of the embodiment of the present invention, described operational amplifier 3 adopts Telescopic folding cascodes, comprising:
The first cascade be made up of the first NMOS tube MN1, the second NMOS tube MN2 and the 3rd NMOS tube MN3 amplifies branch road, the normal phase input end inp1 that described first NMOS tube MN1 is input pipe, grid is first group of differential input end, the source ground of described first NMOS tube MN1; Described second NMOS tube MN2 is the first switching tube, and the grid of described second NMOS tube MN2 meets the first clock signal phil, and the source electrode of described second NMOS tube MN2 connects the drain electrode of described first NMOS tube MN1; The source electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described second NMOS tube MN2, the drain electrode of described 3rd NMOS tube MN3, as the reversed-phase output of described operational amplifier 3, connects the first active load between the drain electrode of described 3rd NMOS tube MN3 and supply voltage VDD.
The second cascade be made up of the 4th NMOS tube MN4, the 5th NMOS tube MN5 and the 6th NMOS tube MN6 amplifies branch road, the inverting input inn1 that described 4th NMOS tube MN4 is input pipe, grid is first group of differential input end, the source ground of described 4th NMOS tube MN4; Described 5th NMOS tube MN5 is the first switching tube, and the grid of described 5th NMOS tube MN5 meets the first clock signal phil, and the source electrode of described 5th NMOS tube MN5 connects the drain electrode of described first NMOS tube MN1; The source electrode of described 6th metal-oxide-semiconductor connects the drain electrode of described 5th NMOS tube MN5, the drain electrode of described 6th NMOS tube MN6, as the positive output end of described operational amplifier 3, connects the second active load between the drain electrode of described 6th NMOS tube MN6 and supply voltage VDD.
7th NMOS tube MN7 and the 8th NMOS tube MN8, the 3rd cascade be made up of described 7th NMOS tube MN7, described 8th NMOS tube MN8 and the 3rd NMOS tube MN3 amplifies branch road, the normal phase input end inp2 that described 7th NMOS tube MN7 is input pipe, grid is second group of differential input end, the source ground of described 7th NMOS tube MN7; Described 8th NMOS tube MN8 is second switch pipe, and the grid of described 8th NMOS tube MN8 meets second clock signal phi2, and the source electrode of described 8th NMOS tube MN8 connects the drain electrode of described 7th NMOS tube MN7; The source electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described 8th NMOS tube MN8.
9th NMOS tube MN9 and the tenth NMOS tube MN10, the 4th cascade be made up of described 9th NMOS tube MN9, described tenth NMOS tube MN10 and the 6th NMOS tube MN6 amplifies branch road, the inverting input inn2 that described 9th NMOS tube MN9 is input pipe, grid is second group of differential input end, the source ground of described 9th NMOS tube MN9; Described tenth NMOS tube MN10 is second switch pipe, and the grid of described tenth NMOS tube MN10 meets second clock signal phi2, and the source electrode of described tenth NMOS tube MN10 connects the drain electrode of described 9th NMOS tube MN9; The source electrode of described 6th metal-oxide-semiconductor connects the drain electrode of described tenth NMOS tube MN10.
Described first active load is made up of the first PMOS MP1 and the second PMOS MP2, the drain electrode of described first PMOS MP1 connects the drain electrode of described 3rd NMOS tube MN3, the source electrode of described first PMOS MP1 connects the drain electrode of described second PMOS MP2, and the source electrode of described second PMOS MP2 meets supply voltage VDD.
Described second active load is made up of the 3rd PMOS MP3 and the 4th PMOS MP4, the drain electrode of described 3rd PMOS MP3 connects the drain electrode of described 6th NMOS tube MN6, the source electrode of described 3rd PMOS MP3 connects the drain electrode of described 4th PMOS MP4, and the source electrode of described 4th PMOS MP4 meets supply voltage VDD; Described second PMOS MP2 is connected identical bias voltage Vb with the grid of described 4th PMOS MP4.
First booster amplifier A1, the inverting input Vi1-of described first booster amplifier A1 connects the source electrode of described 3rd NMOS tube MN3, the grid of the described 3rd NMOS tube MN3 of positive output end Vo1+ connection, the grid that normal phase input end Vi1+ connects the source electrode of described 6th NMOS tube MN6, reversed-phase output Vo1-connects described 6th NMOS tube MN6 of described first booster amplifier A1.Described first booster amplifier A1 is to the gate bias of described 3rd NMOS tube MN3 and described 6th NMOS tube MN6 and realize gain bootstrap.
The normal phase input end Vi2+ of the second booster amplifier A2, described second booster amplifier A2 connects the source electrode of described first PMOS MP1, the grid of the described first PMOS MP1 of reversed-phase output Vo2-connection; The inverting input Vi2-of described second booster amplifier A2 connects the source electrode of described 3rd PMOS MP3, the grid of the described 3rd PMOS MP3 of positive output end Vo2+ connection.Described second booster amplifier A2 is to the gate bias of described first PMOS MP1 and described 3rd PMOS MP3 and realize gain bootstrap.
Described operational amplifier 3 also comprises the 11 NMOS tube and the 12 NMOS tube, the drain electrode of described 11 NMOS tube connects the source electrode of described first NMOS tube MN1, the grid of described 11 NMOS tube meets the common mode feedback signal Vcmfb of described operational amplifier 3, the drain electrode of described 12 NMOS tube connects the source electrode of described 4th NMOS tube MN4, the grid of described 12 NMOS tube meets reference signal Vref, the source ground of described 11 NMOS tube and described 12 NMOS tube.Common mode feedback signal Vcmfb is formed after the common-mode signal feedback of outputting analog signal outn and outp that described operational amplifier 3 exports.The source electrode of described first NMOS tube MN1 and described 4th NMOS tube MN4 is respectively by described operational amplifier 3 common-mode signal can be made after the 11 NMOS tube and the 12 NMOS tube ground connection more stable.
Comparison diagram 5A and Fig. 5 B is known, the modules at different levels of the embodiment of the present invention are kept module 1 and 2 by employing two sampling and the input of operational amplifier 3 are set to two groups of differential input ends, can realize two samplings keeps modules 1 or 2 to hocket sampling, and operational amplifier 3 can keep module 1 or 2 be connected and be operated in the amplification cycle with a sampling all the time, so the embodiment of the present invention can avoid the idle of operational amplifier 3, make the operational amplifier 3 of module at different levels always work in amplification mode, thus the operating rate of overall ADC can be improved.
Above by specific embodiment to invention has been detailed description, but these are not construed as limiting the invention.Without departing from the principles of the present invention, those skilled in the art also can make many distortion and improvement, and these also should be considered as protection scope of the present invention.
Claims (7)
1. a production line analog-digital converter, it is characterized in that, production line analog-digital converter comprises the Pipeline ADC structure be made up of multiple grades of modules, and described level module at different levels all comprises an input end of analog signal, digital signal output end and analog signal output;
The input end of analog signal of level module described in the first order connects external analog signal, and the input end of analog signal of other the described level module at different levels outside the first order connects the analog signal output of level module described in upper level;
Described level module at different levels comprises sub-adc converter and residue-gain-circuit, and input analog signal is converted to digital signal and exports by the sub-adc converter of described level module at different levels;
The residue-gain-circuit of described level module at different levels comprises subnumber weighted-voltage D/A converter, sampling hold circuit one, sampling hold circuit two and operational amplifier;
The described digital signal exported is changed into intermediate analog signal by described subnumber weighted-voltage D/A converter, obtains analog signal surplus and form outputting analog signal after this analog signal surplus being amplified by described operational amplifier after described input analog signal and described intermediate analog signal are subtracted each other by the residue-gain-circuit of described level module at different levels;
Described operational amplifier comprises two groups of differential input ends, input pipe respectively with the first switching tube series connection of first group of differential input end, and described first switching tube carries out switching over by the first clock signal; The input pipe of second group of differential input end is connected with second switch pipe respectively, and described second switch pipe carries out switching over by second clock signal, and described first clock signal and described second clock signal are mutual not overlapping clock signal;
The output of described sampling hold circuit one is connected to described first group of differential input end, and the output of described sampling hold circuit two is connected to described second group of differential input end;
The residue-gain-circuit of described level module at different levels comprises sampling Holdover mode one and sampling Holdover mode 2 two kinds of mode of operations, and two kinds of mode of operations are switched by described first clock signal and described second clock signal;
At described sampling Holdover mode for the moment, input pipe and described first switching tube of described first group of differential input end are connected, the input pipe of described second group of differential input end and described second switch pipe disconnect, described sampling hold circuit two is operated in sampling configuration, described sampling hold circuit one is operated in amplification mode, and described sampling hold circuit one to be sampled by described first group of differential input end and obtained analog signal surplus after the described input analog signal that obtains and described intermediate analog signal are subtracted each other and form outputting analog signal after amplifying by described operational amplifier;
When described sampling Holdover mode two, the input pipe of described second group of differential input end and described second switch pipe are connected, input pipe and described first switching tube of described first group of differential input end disconnect, described sampling hold circuit one is operated in sampling configuration, described sampling hold circuit two is operated in amplification mode, and described sampling hold circuit two to be sampled by described second group of differential input end and obtained analog signal surplus after the described input analog signal that obtains and described intermediate analog signal are subtracted each other and form outputting analog signal after amplifying by described operational amplifier.
2. production line analog-digital converter as claimed in claim 1, it is characterized in that: described sampling hold circuit one and described sampling hold circuit two all adopt identical sampling hold circuit cellular construction, described sampling hold circuit cellular construction comprises: electric capacity one and electric capacity two;
The first end of described electric capacity one is connected with the first end of described electric capacity two and as the output of described sampling hold circuit cellular construction;
Second end of described electric capacity one connects described input analog signal by switch one, the second end of described electric capacity two connects described input analog signal by switch two, and the first end of described electric capacity one and described electric capacity two is by switch three ground connection;
Second end of described electric capacity one connects the output of described operational amplifier by switch four, the second end of described electric capacity two connects described intermediate analog signal by switch five;
Described switch one, described switch two, described switch three all connect first group of clock signal, and described switch four is all connected second group of clock signal with described switch five, and described first group of clock signal and described second group of clock signal are clock signal not overlapping each other;
Described switch one, described switch two and described switch three are connected, and when described switch four and described switch five disconnect, described sampling hold circuit cellular construction works in sampling configuration;
Described switch one, described switch two and described switch three disconnect, and when described switch four and described switch five are connected, described sampling hold circuit cellular construction works in amplification mode;
Described first group of clock signal that described sampling hold circuit one connects is described second clock signal, and described second group of clock signal that described sampling hold circuit one connects is described first clock signal;
Described first group of clock signal that described sampling hold circuit two connects is described first clock signal, and described second group of clock signal that described sampling hold circuit two connects is described second clock signal.
3. production line analog-digital converter as claimed in claim 2, is characterized in that: described level module at different levels is fully differential structure, described input analog signal, described intermediate analog signal and described outputting analog signal all fully differential signals; The positive phase signals of described outputting analog signal is exported by the positive reversed-phase output of described operational amplifier respectively;
Described sampling hold circuit one and described sampling hold circuit two are made up of two described sampling hold circuit cellular constructions all respectively, are respectively for the signal annexation of two the described sampling hold circuit cellular constructions of any one in described sampling hold circuit one and described sampling hold circuit two:
First sampling hold circuit cellular construction connects the reversed-phase output of the normal phase input end in one group of differential input end of the positive phase signals of described input analog signal, the inversion signal of described intermediate analog signal, described operational amplifier, described operational amplifier respectively;
Second sampling hold circuit cellular construction connects the positive output end of the inverting input in one group of differential input end of the inversion signal of described input analog signal, the positive phase signals of described intermediate analog signal, described operational amplifier, described operational amplifier respectively.
4. the production line analog-digital converter as described in claim 1 or 2 or 3, is characterized in that: described operational amplifier adopts Telescopic folding cascodes.
5. production line analog-digital converter as claimed in claim 4, is characterized in that: described operational amplifier comprises:
The first cascade be made up of the first NMOS tube, the second NMOS tube and the 3rd NMOS tube amplifies branch road, the normal phase input end that described first NMOS tube is input pipe, grid is first group of differential input end, the source ground of described first NMOS tube; Described second NMOS tube is the first switching tube, and the grid of described second NMOS tube connects the first clock signal, and the source electrode of described second NMOS tube connects the drain electrode of described first NMOS tube; The source electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described second NMOS tube, and the drain electrode of described 3rd NMOS tube, as the reversed-phase output of described operational amplifier, connects the first active load between the drain electrode of described 3rd NMOS tube and supply voltage;
The second cascade be made up of the 4th NMOS tube, the 5th NMOS tube and the 6th NMOS tube amplifies branch road, the inverting input that described 4th NMOS tube is input pipe, grid is first group of differential input end, the source ground of described 4th NMOS tube; Described 5th NMOS tube is the first switching tube, and the grid of described 5th NMOS tube connects the first clock signal, and the source electrode of described 5th NMOS tube connects the drain electrode of described first NMOS tube; The source electrode of described 6th metal-oxide-semiconductor connects the drain electrode of described 5th NMOS tube, and the drain electrode of described 6th NMOS tube, as the positive output end of described operational amplifier, connects the second active load between the drain electrode of described 6th NMOS tube and supply voltage;
7th NMOS tube and the 8th NMOS tube, the 3rd cascade be made up of described 7th NMOS tube, described 8th NMOS tube and the 3rd NMOS tube amplifies branch road, the normal phase input end that described 7th NMOS tube is input pipe, grid is second group of differential input end, the source ground of described 7th NMOS tube; Described 8th NMOS tube is second switch pipe, and the grid of described 8th NMOS tube connects second clock signal, and the source electrode of described 8th NMOS tube connects the drain electrode of described 7th NMOS tube; The source electrode of described 3rd metal-oxide-semiconductor connects the drain electrode of described 8th NMOS tube;
9th NMOS tube and the tenth NMOS tube, the 4th cascade be made up of described 9th NMOS tube, described tenth NMOS tube and the 6th NMOS tube amplifies branch road, the inverting input that described 9th NMOS tube is input pipe, grid is second group of differential input end, the source ground of described 9th NMOS tube; Described tenth NMOS tube is second switch pipe, and the grid of described tenth NMOS tube connects second clock signal, and the source electrode of described tenth NMOS tube connects the drain electrode of described 9th NMOS tube; The source electrode of described 6th metal-oxide-semiconductor connects the drain electrode of described tenth NMOS tube;
First booster amplifier, the inverting input of described first booster amplifier connects the source electrode of described 3rd NMOS tube, the grid of described 3rd NMOS tube of positive output end connection, the grid that normal phase input end connects the source electrode of described 6th NMOS tube, reversed-phase output connects described 6th NMOS tube of described first booster amplifier.
6. production line analog-digital converter as claimed in claim 5, is characterized in that:
Described first active load is made up of the first PMOS and the second PMOS, the drain electrode of described first PMOS connects the drain electrode of described 3rd NMOS tube, the source electrode of described first PMOS connects the drain electrode of described second PMOS, and the source electrode of described second PMOS connects supply voltage;
Described second active load is made up of the 3rd PMOS and the 4th PMOS, the drain electrode of described 3rd PMOS connects the drain electrode of described 6th NMOS tube, the source electrode of described 3rd PMOS connects the drain electrode of described 4th PMOS, and the source electrode of described 4th PMOS connects supply voltage; Described second PMOS is connected identical bias voltage with the grid of described 4th PMOS;
Second booster amplifier, the grid that normal phase input end connects the source electrode of described first PMOS, reversed-phase output connects described first PMOS of described second booster amplifier; The inverting input of described second booster amplifier connects the source electrode of described 3rd PMOS, the grid of described 3rd PMOS of positive output end connection.
7. production line analog-digital converter as claimed in claim 5, it is characterized in that: described operational amplifier also comprises the 11 NMOS tube and the 12 NMOS tube, the drain electrode of described 11 NMOS tube connects the source electrode of described first NMOS tube, the grid of described 11 NMOS tube connects the common mode feedback signal of described operational amplifier, the drain electrode of described 12 NMOS tube connects the source electrode of described 4th NMOS tube, the grid of described 12 NMOS tube connects reference signal, the source ground of described 11 NMOS tube and described 12 NMOS tube.
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| CN201310231648.5A CN104242936A (en) | 2013-06-09 | 2013-06-09 | Pipelined analog-digital converter |
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| CN201310231648.5A CN104242936A (en) | 2013-06-09 | 2013-06-09 | Pipelined analog-digital converter |
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| CN112152627A (en) * | 2020-08-25 | 2020-12-29 | 西安电子科技大学 | MDAC applied to driving of push-pull output stage of analog-to-digital converter (ADC) of GS/s assembly line |
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| CN112152627B (en) * | 2020-08-25 | 2023-02-24 | 西安电子科技大学 | MDAC applied to drive of push-pull output stage of analog-to-digital converter (ADC) of general packet radio service (GS/s) assembly line |
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