CN112152627B - MDAC applied to drive of push-pull output stage of analog-to-digital converter (ADC) of general packet radio service (GS/s) assembly line - Google Patents
MDAC applied to drive of push-pull output stage of analog-to-digital converter (ADC) of general packet radio service (GS/s) assembly line Download PDFInfo
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Abstract
According to the high-speed MDAC applied to the GS/s assembly line ADC push-pull output stage for driving, the push-pull output stage is added between the output end of the operational amplifier and the second stage of the assembly line ADC, and the operational amplifier and the second stage of the assembly line ADC are isolated by adding the push-pull output stage circuit, so that load capacitance driven by the operational amplifier is reduced. In addition, the push-pull output stage circuit has the characteristic of high capacitive load driving capability, so that the push-pull output stage circuit can quickly establish a residual signal transmitted by the operational amplifier on a second-stage sampling capacitor of the ADC of the assembly line. Compared with the traditional structure that the operational amplifier is directly connected with the sampling capacitor of the second stage of the assembly line, the invention shortens the time for establishing the whole MDAC and realizes the high-speed MDAC.
Description
Technical Field
The invention relates to the field of mixed signal integrated circuit design, in particular to an MDAC (design dependent logic controller) applied to the drive of a push-pull output stage of an ADC (analog to digital converter) of a GS/s assembly line.
Background
The assembly line ADC is a common structure for realizing the high-speed high-precision ADC, the output end of the first-stage MDAC in the structure is connected with a load capacitor CL, the load capacitor is also a sampling capacitor of the second stage of the assembly line ADC, and the operational amplifier directly drives the load capacitor CL.
Therefore, the invention provides a high-speed MDAC driven by a push-pull output stage of a GS/s pipeline, which is used for shortening the establishment time of an error signal between stages of an ADC of the pipeline.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an MDAC applied to the drive of the push-pull output stage of the GS/s pipeline ADC. The technical problem to be solved by the invention is realized by the following technical scheme:
the MDAC applied to the drive of the push-pull output stage of the ADC in the GS/s pipeline provided by the embodiments of the present invention includes a quantization module, a residual error amplification module, and a load capacitor CL, wherein the quantization module is configured to quantize and perform operation to generate a quantization result and a residual error signal that is not amplified, the residual error amplification module is configured to amplify the residual error signal and drive the load capacitor CL, and the residual error amplification module includes: the output end of the quantization module is connected with the input end of the inverting amplifier, the input end of the push-pull output stage circuit is connected with the output end of the inverting amplifier, and the push-pull output stage circuit comprises: first capacitor C1, second capacitor C2, first resistor R1, second resistor R2 and first MOS transistor M a And a second MOS transistor M b The first output end of the inverting amplifier is connected with one end of a first capacitor C1 and one end of a second capacitor C2, the other end of the first capacitor C1 is connected with one end of a first resistor R1 and a grid of a first MOS tube M1, the other end of the first resistor R1 is connected with a first bias voltage VB1, the other end of the second capacitor C2 is connected with one end of the second resistor R2 and a grid of the second MOS tube M2, the other end of the second resistor R2 is connected with a second bias voltage VB2, a source electrode of the first MOS tube M1 is connected with a source electrode of the second MOS tube M2 and one end of a load capacitor CL of a second stage of the pipeline ADC, a drain electrode of the first MOS tube M1 is connected with a power supply positive electrode VDD, a drain electrode of the second MOS tube M2 is connected with a digital ground GND, and the other end of the load capacitor CL is connected with the digital ground.
Optionally, the inverting amplifier is composed of a two-stage complementary common-source positive feedback operational amplifier, a third capacitor CS, and a fourth capacitor CF, a positive input end of a first-stage complementary common-source positive feedback operational amplifier in the two-stage complementary common-source positive feedback operational amplifier is connected to one end of the third capacitor CS and one end of the fourth capacitor CF, the other end of the third capacitor CS is connected to an output of the quantization module, an output end of the first-stage complementary common-source positive feedback operational amplifier is connected to an input end of a second-stage complementary common-source positive feedback operational amplifier, and the other end of the fourth capacitor CF is connected to an output end of the second-stage complementary common-source positive feedback operational amplifier, one end of the first capacitor C1, and one end of the second capacitor C2.
Optionally, any complementary common source positive feedback operational amplifier in the two complementary common source positive feedback operational amplifiers includes: a third MOS transistor M0, a fourth MOS transistor M1, a fifth MOS transistor M2, a sixth MOS transistor M3, a seventh MOS transistor M4, an eighth MOS transistor M5, a ninth MOS transistor M6, and a common mode feedback circuit, wherein an output terminal of the common mode feedback circuit is connected to a gate of the third MOS transistor M0, a source of the third MOS transistor M0 is connected to a power supply positive electrode VDD, a drain of the third MOS transistor M0 is connected to a source of the fourth MOS transistor M1 and a source of the fifth MOS transistor M2, respectively, a drain of the fourth MOS transistor M1 is connected to a drain of the sixth MOS transistor M3, a drain of the ninth MOS transistor M6, and a gate of the eighth MOS transistor M5, respectively, the gate of the fourth MOS transistor M1 is connected to the input terminal VIN and the gate of the sixth MOS transistor M3, the drain of the fifth MOS transistor M2 is connected to the drain of the eighth MOS transistor M5 and the drain of the seventh MOS transistor M4, the source of the fifth MOS transistor M2 is connected to the output terminal and the gate of the seventh MOS transistor M4, the source of the seventh MOS transistor M4 is connected to the source of the sixth MOS transistor M3, the source of the eighth MOS transistor M5, the source of the ninth MOS transistor M6, and the digital GND, and the output of the first stage complementary common source positive feedback operational amplifier is the input of the second stage complementary common source positive feedback operational amplifier.
Optionally, the first MOS transistor Ma is an N-channel MOS transistor, and the second MOS transistor Mb is a P-channel MOS transistor.
Optionally, the third MOS transistor (M0), the fourth MOS transistor (M1), and the fifth MOS transistor (M2) are P-channel MOS transistors, and the sixth MOS transistor (M3), the seventh MOS transistor (M4), the eighth MOS transistor (M5), and the ninth MOS transistor (M6) are N-channel MOS transistors.
Optionally, the quantization module is composed of a flash ADC and a capacitor DAC; or the quantization module is composed of a successive approximation type structure ADC and a capacitance structure DAC.
According to the high-speed MDAC applied to the GS/s assembly line ADC push-pull output stage for driving, the push-pull output stage is added between the output end of the operational amplifier and the second stage of the assembly line ADC, and the addition of the push-pull output stage circuit isolates the operational amplifier from the second stage of the assembly line ADC sampling capacitor, so that the load capacitor driven by the operational amplifier is reduced. In addition, the push-pull output stage circuit has the characteristic of high capacitive load driving capability, so that the push-pull output stage circuit can quickly establish a residual signal transmitted by the operational amplifier on a second-stage sampling capacitor of the pipeline ADC. Compared with the traditional structure that the operational amplifier is directly connected with the sampling capacitor of the second stage of the assembly line, the invention shortens the time for establishing the whole MDAC and realizes the high-speed MDAC.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic diagram of an MDAC structure applied to a push-pull output stage drive of a GS/s pipeline ADC according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a residual error amplifying module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first stage complementary common source positive feedback operational amplifier according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second stage complementary common source positive feedback operational amplifier provided in the embodiment of the present invention;
fig. 5 is a specific practical application circuit of a high-speed MDAC, in which a quantization module provided by the embodiment of the present invention is driven by a push-pull output stage formed by a flash ADC and a capacitor DAC;
fig. 6 is a schematic structural diagram of a two-way push-pull output stage circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
As shown in fig. 1 and fig. 2, an MDAC applied to driving a push-pull output stage of a GS/s pipeline ADC according to an embodiment of the present invention includes a quantization module, a residual amplifying module, and a load capacitor CL, where the quantization module is configured to quantize and perform an operation to generate a quantization result and an unamplified residual signal, and the residual amplifying module is configured to amplify the residual signal and drive the load capacitor CL, and the residual amplifying module includes: the output end of the quantization module is connected with the input end of the inverting amplifier, the input end of the push-pull output stage circuit is connected with the output end of the inverting amplifier, and the push-pull output stage circuit comprises: first capacitor C1, second capacitor C2, first resistor R1, second resistor R2 and first MOS transistor M a And a second MOS transistor M b The first output end of the inverting amplifier is connected with one end of a first capacitor C1 and one end of a second capacitor C2 respectively, the other end of the first capacitor C1 is connected with one end of a first resistor R1 and a grid of a first MOS tube M1 respectively, the other end of the first resistor R1 is connected with a first bias voltage VB1, the other end of the second capacitor C2 is connected with one end of the second resistor R2 and a grid of the second MOS tube M2 respectively, the other end of the second resistor R2 is connected with a second bias voltage VB2, a source electrode of the first MOS tube M1 is connected with a source electrode of the second MOS tube M2 and one end of a load capacitor CL of a second stage of the assembly line ADC respectively, a drain electrode of the first MOS tube M1 is connected with a power supply positive electrode VDD, a drain electrode of the second MOS tube M2 is connected with a digital ground GND, and the other end of the load capacitor CL is connected with the GND digitally.
Wherein, the first MOS transistor M a Is an N-channel MOS transistor, and the second MOS transistor M b Is a P-channel MOS tube.
In fig. 1, S/H represents a sample-and-hold circuit, a sub-ADC, a sub-DAC, an S/H sample-and-hold circuit, and an adder circuit, and the structure is the same as the prior art, and the specific principle thereof will not be described in detail here.
Referring to fig. 2, the operation principle of an MDAC applied to the push-pull output stage drive of the GS/s pipeline ADC according to the embodiment of the present invention is as follows:
the C1 and C2 capacitors of the push-pull output stage circuit can isolate an output common mode of the operational amplifier from a bias direct current level of the push-pull output stage circuit, and residual signals amplified by the operational amplifier are transmitted to gate ends of the M1 and M2, and the VB1 and VB2 are bias voltages for ensuring normal work of the push-pull output stage. The advantages of the push-pull output stage circuit access are described in detail below:
the first stage and the second stage of the operational amplifier and the capacitors CS and CF form a negative feedback amplifying loop to amplify residual signals, and the closed loop gain of the negative feedback amplifying loop is approximate to CS/CF. The gain of the push-pull output stage is approximately 1, and because the output impedance is low, which is similar to the voltage source principle, the lower the output impedance, the smaller the influence of the load on the output voltage is, so that the capacity of the push-pull output stage structure for driving the capacitive load is very strong, and the residual signal after the operational amplification can be quickly established on the second-stage input sampling capacitor CL of the pipeline ADC. The traditional operational amplifier directly drives the CL, and firstly, the capacitive driving capability of the transconductance operational amplifier is not good. Secondly, the tolerance of CL is large, typically in the order of hundreds of fF, which not only makes the setup time of the operational amplifier long, but also may affect the stability of the operational amplifier. After a push-pull output stage structure is connected behind the operational amplifier, according to the Miller's theorem and the series-parallel relation of capacitance, C1 and C2 are respectively connected with a gate-drain parasitic capacitance Cgs1 of a first MOS transistor Ma and a gate-drain parasitic capacitance Cgs2 of a first MOS transistor Mb in series and then connected in parallel, and the gate-drain parasitic capacitances of CF and Ma are not large, so that the load capacitance of the operational amplifier is approximately the sum of the capacitance value of CF and 2 times of the capacitance value of Cgs1, and is much smaller than the value of the load capacitance CL of the operational amplifier in the traditional structure, thereby greatly reducing the load to be driven by the operational amplifier and enabling an error signal after the operational amplifier to be established more quickly.
According to the high-speed MDAC applied to the GS/s assembly line ADC push-pull output stage for driving, the push-pull output stage is added between the output end of the operational amplifier and the second stage of the assembly line ADC, and the operational amplifier and the second stage of the assembly line ADC are isolated by adding the push-pull output stage circuit, so that load capacitance driven by the operational amplifier is reduced. In addition, the push-pull output stage circuit has the characteristic of high capacitive load driving capability, so that the push-pull output stage circuit can quickly establish a residual signal transmitted by the operational amplifier on a second-stage sampling capacitor of the pipeline ADC. Compared with the traditional structure that the operational amplifier is directly connected with the sampling capacitor of the second stage of the assembly line, the invention shortens the time for establishing the whole MDAC and realizes the high-speed MDAC. Example two
As shown in fig. 2, on the basis of the first embodiment, the inverting amplifier in the embodiment of the present invention is formed by a fully complementary common-source positive feedback high-speed amplifier, and fig. 2 shows a structure diagram of the fully complementary common-source positive feedback high-speed amplifier, where the inverting amplifier is formed by a two-stage complementary common-source positive feedback operational amplifier, a third capacitor CS, and a fourth capacitor CF, a positive input end of a first-stage complementary common-source positive feedback operational amplifier in the two-stage complementary common-source positive feedback operational amplifier is connected to one end of the third capacitor CS and one end of the fourth capacitor CF, respectively, another end of the third capacitor CS is connected to an output of the quantization module, an output end of the first-stage complementary common-source positive feedback operational amplifier is connected to an input end of the second-stage complementary common-source positive feedback operational amplifier, and another end of the fourth capacitor CF is connected to an output end of the second-stage complementary common-source positive feedback operational amplifier, one end of the first capacitor C1, and one end of the second capacitor C2, respectively.
According to the fully complementary common source positive feedback high-speed operational amplifier provided by the embodiment of the invention, firstly, the complementary common source is taken as an input stage, so that the gm value of an input tube can be increased, and thus the input noise can be reduced. And the complementary common source structure can also improve the bandwidth of the operational amplifier, and the secondary pole point can be far away from the original point due to the increase of the gm value in the two-stage structure, so that the requirement of phase margin can be met without Miller compensation, and the bandwidth of the operational amplifier is expanded. M5, M6, M12 and M13 are connected into an equivalent diode form, a negative resistor is provided to be connected with M3, M4, M10 and M11 resistors in parallel, and the output impedance is increased through the negative impedance generated by positive feedback, so that the gain of the operational amplifier is improved. In addition, the positive feedback branch consumes little current, and does not increase too much power consumption or influence the high-frequency characteristic of the operational amplifier. Compared with the operational amplifier with the traditional structure, the two-stage operational amplifier structure provided by the invention can meet the requirement of phase margin without using a Miller capacitor, so that the loss of bandwidth caused by the Miller capacitor is reduced. Compared with the traditional bootstrap gain operational amplifier structure, the invention does not need to increase a complex bootstrap gain operational amplifier circuit and a large number of bias circuits required by the operation of the bootstrap gain operational amplifier circuit, simplifies the circuit design, and greatly saves the chip area and the circuit power consumption.
EXAMPLE III
As shown in fig. 3 and 4, in the two complementary common-source positive feedback operational amplifiers provided in the embodiment of the present invention, a first stage complementary common-source positive feedback operational amplifier is shown in fig. 3, a second stage complementary common-source positive feedback operational amplifier is shown in fig. 4, and any one of the two complementary common-source positive feedback operational amplifiers includes: a third MOS transistor M0, a fourth MOS transistor M1, a fifth MOS transistor M2, a sixth MOS transistor M3, a seventh MOS transistor M4, an eighth MOS transistor M5, a ninth MOS transistor M6, and a common-mode feedback circuit, where an output terminal of the common-mode feedback circuit is connected to a gate of the third MOS transistor M0, a source of the third MOS transistor M0 is connected to a positive power supply VDD, a drain of the third MOS transistor M0 is connected to a source of the fourth MOS transistor M1 and a source of the fifth MOS transistor M2, a drain of the fourth MOS transistor M1 is connected to a drain of the sixth MOS transistor M3, a drain of the ninth MOS transistor M6, and a gate of the eighth MOS transistor M5, a gate of the fourth MOS transistor M1 is connected to an input terminal and a VIN gate of the sixth MOS transistor M3, a drain of the fifth MOS transistor M2 is connected to a drain of the eighth MOS transistor M5 and a drain of the seventh MOS transistor M4, a drain of the fifth MOS transistor M2 is connected to a drain of the eighth MOS transistor M5, a drain of the seventh MOS transistor M4, a drain of the fifth MOS transistor M2 is connected to a drain of the seventh MOS transistor M2, and a positive feedback amplifier, and a second-stage operational amplifier, a drain of the seventh MOS transistor M2 is connected to a source of the seventh MOS transistor M3, a positive feedback amplifier, a drain of the seventh MOS transistor M2 is connected to a first-stage operational amplifier, a drain of the seventh MOS transistor M3, a second-stage operational amplifier, and a second-stage operational amplifier, a second stage operational amplifier, and a second-stage operational amplifier, wherein the operational amplifier is connected to the seventh operational amplifier.
The third MOS transistor M0, the fourth MOS transistor M1, and the fifth MOS transistor M2 are P-channel MOS transistors, and the sixth MOS transistor M3, the seventh MOS transistor M4, the eighth MOS transistor M5, and the ninth MOS transistor M6 are N-channel MOS transistors.
For the purpose of distinction, the second stage complementary common source feedback operational amplifier and the first stage complementary common source feedback operational amplifier have the same structure, and elements for distinction are shown in fig. 4, where a third MOS transistor is shown by M7, a fourth MOS transistor is shown by M8, a fifth MOS transistor is shown by M9, a sixth MOS transistor is shown by M10, a seventh MOS transistor is shown by M11, an eighth MOS transistor is shown by M12, and a ninth MOS transistor is shown by M13. The input ends of the first stage complementary common source positive feedback operational amplifier are V1N and V1P, and the output end is VOUT 1N And VOUT 1P The input ends of the second stage complementary common source positive feedback operational amplifier are V2N and V2P, and the output end is VOUT 2N And VOUT 2P First-stage output terminal VOUT 1N Is connected with a second-stage input end V2N and a first-stage output end VOUT 1P The second stage input V2P is connected, and CMFB is a common mode feedback circuit, which is the same as the prior art and will not be described in detail here.
Example four
As an optional implementation manner of the present invention, the quantization module is composed of a flash-type structure ADC and a capacitor structure DAC; or, the quantization module is composed of a successive approximation type ADC and a capacitor DAC, but the quantization module of the present invention is not limited thereto, and all circuits applying the method of the present invention belong to the protection scope of the present patent.
Referring to fig. 5, fig. 5 shows a specific practical application circuit of a high-speed MDAC with a quantization module driven by a push-pull output stage formed by a flash ADC and a capacitor DAC, where the overall MDAC is formed by two modules, a quantization module and a residual error amplification module. The quantization module generates a quantization result and a residual error signal which is not amplified through quantization and operation, and the residual error amplification module rapidly amplifies the residual error generated by the quantization module and inputs the amplified residual error to the second stage of the assembly line ADC.
It can be understood that the first stage of the GSs pipeline is the MDAC, and a push-pull output stage circuit is added in the first embodiment of the present invention to drive a load capacitor CL, which is a sampling capacitor of the second stage of the GSs pipeline.
In fig. 5, the area marked by the core unit is the practical application circuit provided by the invention in combination with the first embodiment and the second embodiment, and the circuit shown in fig. 5 can shorten the time for establishing the whole MDAC and realize the high-speed MDAC. Of course, fig. 5 of the present invention shows only one of the actually applied circuits, and specifically, except for the core unit region, other regions may meet the requirements of the first stage of the GSs pipeline.
Referring to fig. 6 in conjunction with fig. 1-4, fig. 6 shows a circuit with two push-pull output stages, where fig. 4 shows a second stage complementary common-source positive feedback operational amplifier connected to the push-pull output stage circuit, where the second stage complementary common-source positive feedback operational amplifier includes two output terminals VOUT 2N And VOUT 2P Therefore, in the circuit schematic diagrams shown in fig. 1 and fig. 2, the push-pull output stage circuit connected to the inverting amplifier is connected to two paths, and the input terminal V2N and the output terminal VOUT of the first push-pull output stage circuit are connected to two paths 2N Input end V2P and output end VOUT of second push-pull output stage circuit 2P In this case, the two-way push-pull output stage circuit structure is the same as that shown in fig. 2, and is not described herein again.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations or positional relationships based on those shown in the drawings, merely for convenience of description and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, are not to be construed as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In the present invention, unless otherwise explicitly stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly, e.g., as being permanently connected, detachably connected, or integral; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
In the description of the specification, reference to the description of "one embodiment," "some embodiments," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a further detailed description of the invention in connection with specific preferred embodiments and it is not intended to limit the invention to the specific embodiments described. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. An MDAC for driving a push-pull output stage of a GS/s pipeline ADC, comprising a quantization module for performing quantization and operation to generate a quantization result and an unamplified residual signal, a residual amplification module for amplifying the residual signal and driving a load Capacitor (CL), and the load Capacitor (CL), wherein the residual amplification module comprises: the output end of the quantization module is connected with the input end of the inverting amplifier, the input end of the push-pull output stage circuit is connected with the output end of the inverting amplifier, and the push-pull output stage circuit comprises: the MOS transistor comprises a first capacitor (C1), a second capacitor (C2), a first resistor (R1), a second resistor (R2) and a first MOS transistor (M) a ) And a second MOS transistor (M) b ) A first output terminal of the inverting amplifier is connected to one terminal of the first capacitor (C1) and the output terminal of the inverting amplifierOne end of a second capacitor (C2) is connected, and the other end of the first capacitor (C1) is respectively connected with one end of the first resistor (R1) and the first MOS tube (M) a ) The other end of the first resistor (R1) is connected with a first bias voltage (VB 1), and the other end of the second capacitor (C2) is respectively connected with one end of the second resistor (R2) and the second MOS tube (M) b ) The other end of the second resistor (R2) is connected with a second bias voltage (VB 2), and the first MOS tube (M) a ) Respectively with the second MOS transistor (M) b ) Is connected with one end of a load Capacitor (CL) of the second stage of the assembly line ADC, the first MOS transistor (M) a ) Is connected with the power supply anode (VDD), and the second MOS tube (M) b ) Is connected to a digital Ground (GND), and the other end of the load Capacitance (CL) is connected to the digital Ground (GND).
2. The MDAC applied to the push-pull output stage drive of the GS/s pipeline ADC of claim 1, wherein the inverting amplifier is composed of two complementary common-source positive feedback operational amplifiers, a third Capacitor (CS) and a fourth Capacitor (CF), a positive input terminal of a first complementary common-source positive feedback operational amplifier in the two complementary common-source positive feedback operational amplifiers is respectively connected with one end of the third Capacitor (CS) and one end of the fourth Capacitor (CF), the other end of the third Capacitor (CS) is connected with an output terminal of the quantization module, an output terminal of the first complementary common-source positive feedback operational amplifier is connected with an input terminal of the second complementary common-source positive feedback operational amplifier, and the other end of the fourth Capacitor (CF) is respectively connected with an output terminal of the second complementary common-source positive feedback operational amplifier, one end of the first capacitor (C1) and one end of the second capacitor (C2).
3. The MDAC applied to the drive of the push-pull output stage of the GS/s pipeline ADC of claim 2, wherein any one of the two complementary common-source positive feedback operational amplifiers comprises: a third MOS transistor (M0), a fourth MOS transistor (M1), a fifth MOS transistor (M2)The output end of the common mode feedback circuit is connected with the grid electrode of the third MOS tube (M0), the source electrode of the third MOS tube (M0) is connected with a power supply positive electrode (VDD), the drain electrode of the third MOS tube (M0) is respectively connected with the source electrode of the fourth MOS tube (M1) and the source electrode of the fifth MOS tube (M2), the drain electrode of the fourth MOS tube (M1) is respectively connected with the drain electrode of the sixth MOS tube (M3), the drain electrode of the ninth MOS tube (M6) and the grid electrode of the eighth MOS tube (M5), the grid electrode of the fourth MOS tube (M1) is respectively connected with the output end VOUT IN The grid electrode of the sixth MOS tube (M3) is connected, the drain electrode of the fifth MOS tube (M2) is respectively connected with the drain electrode of the eighth MOS tube (M5) and the drain electrode of the seventh MOS tube (M4), and the grid electrode of the fifth MOS tube (M2) is respectively connected with the output end VOUT IP And the grid electrode of the seventh MOS tube (M4) is connected, the source electrode of the seventh MOS tube (M4) is respectively connected with the source electrode of the sixth MOS tube (M3), the source electrode of the eighth MOS tube (M5), the source electrode of the ninth MOS tube (M6) and the digital Ground (GND), and the output of the first stage complementary common source positive feedback operational amplifier is the input of the second stage complementary common source positive feedback operational amplifier.
4. MDAC applied to the drive of the push-pull output stage of the GS/s pipeline ADC of claim 1, wherein the first MOS transistor (M) is a MOS transistor a ) Is an N-channel MOS transistor, the second MOS transistor (M) b ) Is a P-channel MOS tube.
5. The MDAC applied to the drive of the push-pull output stage of the GS/s pipeline ADC of claim 3, wherein the third MOS transistor (M0), the fourth MOS transistor (M1) and the fifth MOS transistor (M2) are P-channel MOS transistors, and the sixth MOS transistor (M3), the seventh MOS transistor (M4), the eighth MOS transistor (M5) and the ninth MOS transistor (M6) are N-channel MOS transistors.
6. The MDAC applied to the push-pull output stage drive of the GS/s pipeline ADC in the claim 1, wherein the quantization module is composed of a flash-type structure ADC and a capacitor structure DAC, or; the quantization module is composed of a successive approximation type structure ADC and a capacitance structure DAC.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010864749.6A CN112152627B (en) | 2020-08-25 | 2020-08-25 | MDAC applied to drive of push-pull output stage of analog-to-digital converter (ADC) of general packet radio service (GS/s) assembly line |
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| CN202010864749.6A CN112152627B (en) | 2020-08-25 | 2020-08-25 | MDAC applied to drive of push-pull output stage of analog-to-digital converter (ADC) of general packet radio service (GS/s) assembly line |
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| CN113514761B (en) * | 2021-04-22 | 2024-02-27 | 常熟理工学院 | Detection circuit for constant current source output circuit breaking |
| CN113824415A (en) * | 2021-11-25 | 2021-12-21 | 山东汉芯科技有限公司 | Intelligent program-controlled high-gain amplifier with temperature compensation |
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