CN112152627B - MDAC Driven by GS/s Pipeline ADC Push-Pull Output Stage - Google Patents

Abstract

According to the high-speed MDAC applied to the GS/s assembly line ADC push-pull output stage for driving, the push-pull output stage is added between the output end of the operational amplifier and the second stage of the assembly line ADC, and the operational amplifier and the second stage of the assembly line ADC are isolated by adding the push-pull output stage circuit, so that load capacitance driven by the operational amplifier is reduced. In addition, the push-pull output stage circuit has the characteristic of high capacitive load driving capability, so that the push-pull output stage circuit can quickly establish a residual signal transmitted by the operational amplifier on a second-stage sampling capacitor of the ADC of the assembly line. Compared with the traditional structure that the operational amplifier is directly connected with the sampling capacitor of the second stage of the assembly line, the invention shortens the time for establishing the whole MDAC and realizes the high-speed MDAC.

Description

MDAC Driven by GS/s Pipeline ADC Push-Pull Output Stage

technical field

The invention relates to the field of mixed-signal integrated circuit design, in particular to an MDAC applied to GS/s pipeline ADC push-pull output stage drive.

Background technique

Pipeline ADC is a common structure for realizing high-speed and high-precision ADC. In this structure, the output terminal of the first-stage MDAC is connected to the load capacitor CL, which is also the sampling capacitor of the second-stage pipeline ADC. The op amp directly drives the load capacitor CL. , because the capacitive driving capability of the transconductance op amp is not good, and the capacitance of the load capacitor CL is generally on the order of hundreds of fF, which will not only make the settling time of the op amp very long, but also may affect the stability of the op amp However, it is very difficult to further increase the sampling rate.

In view of this, the present invention proposes a high-speed MDAC driven by a GS/s pipeline push-pull output stage, which is used to shorten the settling time of the pipeline ADC interstage error signal.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides an MDAC applied to drive the push-pull output stage of a GS/s pipeline ADC. The technical problem to be solved in the present invention is realized through the following technical solutions:

An MDAC applied to the push-pull output stage of a GS/s pipeline ADC provided by an embodiment of the present invention includes a quantization module, a residual amplification module, and a load capacitor CL. The quantization module is used for quantization and calculation to generate quantization results and future The amplified residual signal, the residual amplifying module is used to amplify the residual signal and drive the load capacitor CL, the residual amplifying module includes: an inverting amplifier and a push-pull output stage circuit, the The output end of the quantization module is connected to the input end of the inverting amplifier, the input end of the push-pull output stage circuit is connected to the output end of the inverting amplifier, and the push-pull output stage circuit includes: a first capacitor C1 , the second capacitor C2, the first resistor R1, the second resistor R2, the first MOS transistor _Ma and the second MOS transistor _Mb , the first output end of the inverting amplifier is respectively connected to one end of the first capacitor C1 and One end of the second capacitor C2 is connected, the other end of the first capacitor C1 is respectively connected to one end of the first resistor R1 and the gate of the first MOS transistor M1, and the other end of the first resistor R1 One end is connected to the first bias voltage VB1, the other end of the second capacitor C2 is respectively connected to one end of the second resistor R2 and the gate of the second MOS transistor M2, and the other end of the second resistor R2 One end is connected to the second bias voltage VB2, the source of the first MOS transistor M1 is respectively connected to the source of the second MOS transistor M2 and one end of the load capacitor CL of the second stage of the pipeline ADC, the first The drain of one MOS transistor M1 is connected to the positive power supply VDD, the drain of the second MOS transistor M2 is connected to the digital ground GND, and the other end of the load capacitor CL is connected to the digital ground GND.

Optionally, the inverting amplifier is composed of a two-stage complementary common-source positive feedback operational amplifier, a third capacitor CS, and a fourth capacitor CF, and the first stage of the two-stage complementary common-source positive feedback operational amplifier The positive input terminals of the complementary common-source positive feedback operational amplifier are respectively connected to one end of the third capacitor CS and one end of the fourth capacitor CF, and the other end of the third capacitor CS is connected to the output of the quantization module, so The output end of the first-stage complementary common-source positive feedback operational amplifier is connected to the input end of the second-stage complementary common-source positive feedback operational amplifier, and the other end of the fourth capacitor CF is respectively connected to the second-stage complementary common-source The output terminal of the positive feedback operational amplifier, one terminal of the first capacitor C1 and one terminal of the second capacitor C2 are connected.

Optionally, any one of the two complementary common-source positive feedback operational amplifiers includes: a third MOS transistor M0, a fourth MOS transistor M1, a fifth MOS transistor M2, and a sixth MOS transistor M3 , the seventh MOS transistor M4, the eighth MOS transistor M5, the ninth MOS transistor M6, and a common-mode feedback circuit, the output terminal of the common-mode feedback circuit is connected to the gate of the third MOS transistor M0, and the third MOS transistor M0 The source of the MOS transistor M0 is connected to the positive power supply VDD, the drain of the third MOS transistor M0 is respectively connected to the source of the fourth MOS transistor M1 and the source of the fifth MOS transistor M2, and the drain of the third MOS transistor M0 is connected to the source of the fifth MOS transistor M2. The drains of the four MOS transistors M1 are respectively connected to the drains of the sixth MOS transistor M3, the drain of the ninth MOS transistor M6, and the gate of the eighth MOS transistor M5, and the fourth MOS transistor M1 The gates of the gates are respectively connected to the input terminal VIN and the gate of the sixth MOS transistor M3, and the drains of the fifth MOS transistor M2 are respectively connected to the drains of the eighth MOS transistor M5 and the seventh MOS transistor The drain of M4 is connected, the source of the fifth MOS transistor M2 is respectively connected to the output terminal and the gate of the seventh MOS transistor M4, and the source of the seventh MOS transistor M4 is connected to the sixth MOS transistor M4 respectively. The source of the transistor M3, the source of the eighth MOS transistor M5, the source of the ninth MOS transistor M6 and the digital ground GND are connected, and the output of the first stage complementary common source positive feedback operational amplifier is the second Stage Complementary Common Source Positive Feedback Operational Amplifier Input.

Optionally, the first MOS transistor Ma is an N-channel MOS transistor, and the second MOS transistor Mb is a P-channel MOS transistor.

Optionally, the third MOS transistor (M0), the fourth MOS transistor (M1) and the fifth MOS transistor (M2) are P-channel MOS transistors, and the sixth MOS transistor (M3), The seventh MOS transistor (M4), the eighth MOS transistor (M5) and the ninth MOS transistor (M6) are N-channel MOS transistors.

Optionally, the quantization module is composed of a flash ADC and a capacitive DAC; or, the quantization module is composed of a successive approximation ADC and a capacitive DAC.

The embodiment of the present invention provides a high-speed MDAC applied to the push-pull output stage of the GS/s pipeline ADC for driving. By adding a push-pull output stage between the output terminal of the operational amplifier and the second stage of the pipeline ADC, the push-pull output stage circuit The addition of the op amp isolates the second-stage sampling capacitor of the pipeline ADC, thereby reducing the load capacitance driven by the op amp. In addition, the push-pull output stage circuit itself has the characteristics of high capacitive load driving capability, so the push-pull output stage circuit can quickly establish the residual signal transmitted by the operational amplifier on the second-stage sampling capacitor of the pipeline ADC. Compared with the traditional structure in which the operational amplifier is directly connected to the sampling capacitor of the second stage of the pipeline, the present invention shortens the establishment time of the overall MDAC and realizes a high-speed MDAC.

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

Description of drawings

FIG. 1 is a schematic structural diagram of an MDAC applied to a GS/s pipeline ADC push-pull output stage drive provided by an embodiment of the present invention;

FIG. 2 is a schematic structural diagram of a residual amplification module provided by an embodiment of the present invention;

3 is a schematic structural diagram of a first-stage complementary common-source positive feedback operational amplifier provided by an embodiment of the present invention;

4 is a schematic structural diagram of a second-stage complementary common-source positive feedback operational amplifier provided by an embodiment of the present invention;

5 is a specific practical application circuit of a high-speed MDAC driven by a push-pull output stage composed of a flash-type ADC and a capacitor-structure DAC in the quantization module provided by the embodiment of the present invention;

FIG. 6 is a schematic structural diagram of a two-way push-pull output stage circuit provided by an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.

Embodiment one

As shown in Figure 1 and Figure 2, an MDAC applied to the push-pull output stage of a GS/s pipeline ADC provided by an embodiment of the present invention includes a quantization module, a residual amplification module, and a load capacitor CL, and the quantization module Used for quantization and operation to generate quantized results and unamplified residual signals, the residual amplification module is used to amplify the residual signal, and drive the load capacitance CL, characterized in that the residual amplification module It includes: an inverse amplifier and a push-pull output stage circuit, the output end of the quantization module is connected to the input end of the inverse amplifier, and the input end of the push-pull output stage circuit is connected to the output end of the inverse amplifier , the push-pull output stage circuit includes: a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, a first MOS transistor M _a and a second MOS transistor M _b , the first inverting amplifier One output end is respectively connected to one end of the first capacitor C1 and one end of the second capacitor C2, and the other end of the first capacitor C1 is respectively connected to one end of the first resistor R1 and the first MOS transistor The gate of M1 is connected, the other end of the first resistor R1 is connected to the first bias voltage VB1, and the other end of the second capacitor C2 is connected to one end of the second resistor R2 and the second MOS transistor respectively. The gate of M2 is connected, the other end of the second resistor R2 is connected to the second bias voltage VB2, the source of the first MOS transistor M1 is connected to the source of the second MOS transistor M2 and the pipeline ADC One end of the load capacitor CL of the second stage is connected, the drain of the first MOS transistor M1 is connected to the positive power supply VDD, the drain of the second MOS transistor M2 is connected to the digital ground GND, and the other end of the load capacitor CL One end is connected to the digital ground GND.

Wherein, the first MOS transistor M _a is an N-channel MOS transistor, and the second MOS transistor M _b is a P-channel MOS transistor.

In FIG. 1, S/H represents a sample-and-hold circuit, sub-ADC, sub-DAC, S/H sample-and-hold circuit and an addition circuit. This structure is the same as that of the prior art, and its specific principle will not be described in detail here.

Referring to FIG. 2 , the working principle of an MDAC applied to the push-pull output stage of a GS/s pipeline ADC provided by an embodiment of the present invention is as follows:

The C1 and C2 capacitors of the push-pull output stage circuit can isolate the output common mode of the op amp from the bias DC level of the push-pull output stage circuit, and transmit the amplified residual signal of the op amp to the gate terminals of M1 and M2, VB1 and VB2 are bias voltages to ensure the normal operation of the push-pull output stage. The following details the advantages of the push-pull output stage circuit access:

The first and second stages of the operational amplifier and capacitors CS and CF form a negative feedback amplification loop to amplify the residual signal, and its closed-loop gain is approximately CS/CF. The gain of the push-pull output stage is approximately 1. Because of its low output impedance, it is similar to the principle of a voltage source. The lower the output impedance, the less the output voltage is affected by the load. Therefore, the push-pull output stage structure has a strong ability to drive capacitive loads, so It can quickly establish the residual signal amplified by the operational amplifier on the second-stage input sampling capacitor CL of the pipeline ADC. The traditional structure op amp directly drives CL. First, the capacitive drive capability of the transconductance op amp is not good. Secondly, the capacitance of CL is very large, generally on the order of hundreds of fF, which will not only make the settling time of the op amp very long, but may also affect the stability of the op amp. After the push-pull output stage structure is connected behind the operational amplifier, according to Miller's theorem and the series-parallel relationship of capacitors, C1 and C2 are respectively connected to the gate-drain parasitic capacitance Cgs1 of the first MOS transistor Ma and the gate-drain parasitic capacitance of the first MOS transistor Mb. Capacitor Cgs2 is connected in series, and then connected in parallel. CF and Ma gate-drain parasitic capacitances are not large, so the load capacitance of the op amp is approximately the sum of the capacitance of CF and twice the capacitance of Cgs1, which is the same as the value of the load capacitance CL of the traditional op amp. It is much smaller than that, which greatly reduces the load to be driven by the op amp, so that the error signal amplified by the op amp can be established faster.

The embodiment of the present invention provides a high-speed MDAC applied to the push-pull output stage of the GS/s pipeline ADC for driving. By adding a push-pull output stage between the output terminal of the operational amplifier and the second stage of the pipeline ADC, the push-pull output stage circuit The addition of the op amp isolates the second-stage sampling capacitor of the pipeline ADC, thereby reducing the load capacitance driven by the op amp. In addition, the push-pull output stage circuit itself has the characteristics of high capacitive load driving capability, so the push-pull output stage circuit can quickly establish the residual signal transmitted by the operational amplifier on the second-stage sampling capacitor of the pipeline ADC. Compared with the traditional structure in which the operational amplifier is directly connected to the sampling capacitor of the second stage of the pipeline, the present invention shortens the establishment time of the overall MDAC and realizes a high-speed MDAC. Embodiment two

As shown in Figure 2, on the basis of Embodiment 1, the inverting amplifier in the embodiment of the present invention is composed of a full-complementary common-source positive feedback high-speed amplifier, and Figure 2 shows the structure of a full-complementary common-source positive feedback high-speed amplifier As shown in the figure, the inverting amplifier is composed of a two-stage complementary common-source positive feedback operational amplifier, a third capacitor CS, and a fourth capacitor CF, and the first-stage complementary common-source in the two-stage complementary common-source positive feedback operational amplifier The positive input terminal of the positive feedback operational amplifier is respectively connected to one end of the third capacitor CS and one end of the fourth capacitor CF, the other end of the third capacitor CS is connected to the output of the quantization module, and the first The output end of the first-stage complementary common-source positive feedback operational amplifier is connected to the input end of the second-stage complementary common-source positive feedback operational amplifier, and the other end of the fourth capacitor CF is respectively connected to the second-stage complementary common-source positive feedback operational amplifier. The output terminal of the amplifier, one terminal of the first capacitor C1 and one terminal of the second capacitor C2 are connected.

In the fully complementary common-source positive feedback high-speed operational amplifier provided by the embodiment of the present invention, firstly, the complementary common-source is used as an input stage to increase the gm value of the input transistor so as to reduce input noise. Secondly, the complementary common source structure can also improve the bandwidth of the op amp. The two-stage structure can move the secondary pole away from the origin due to the increase of the gm value, so that the phase margin requirement can be met without Miller compensation, which also expands the bandwidth of the op amp. . M5, M6, M12 and M13 are connected in the form of an equivalent diode, and a negative resistance is provided in parallel with the resistances of M3, M4, M10 and M11, and the output impedance is increased through the negative resistance generated by positive feedback, thereby increasing the gain of the operational amplifier. In addition, the positive feedback branch consumes very little current, which will neither increase too much power consumption nor affect the high-frequency characteristics of the op amp. Compared with the operational amplifier with traditional structure, firstly, the two-stage operational amplifier structure proposed by the present invention can meet the requirement of phase margin without using Miller capacitor, so the loss of bandwidth caused by Miller capacitor is reduced. The present invention adopts a positive feedback structure to replace the traditional bootstrap gain operational amplifier structure to increase the gain. Compared with the latter, the present invention does not need to add a complex bootstrap gain operational amplifier circuit and a large number of bias circuits necessary for its work, and simplifies the circuit Design, greatly saving chip area and circuit power consumption.

Embodiment three

As shown in Figure 3 and Figure 4, two complementary common-source positive feedback operational amplifiers provided by the embodiment of the present invention, wherein the first-stage complementary common-source positive feedback operational amplifier is shown in Figure 3, and the second-stage complementary common-source positive feedback operational amplifier The polar positive feedback operational amplifier is shown in Figure 4. Any complementary common-source positive feedback operational amplifier in the two complementary common-source positive feedback operational amplifiers includes: the third MOS transistor M0, the fourth MOS transistor M1, the fifth MOS transistor M2, The sixth MOS transistor M3, the seventh MOS transistor M4, the eighth MOS transistor M5, the ninth MOS transistor M6, and a common-mode feedback circuit, the output terminal of the common-mode feedback circuit is connected to the gate of the third MOS transistor M0 , the source of the third MOS transistor M0 is connected to the positive power supply VDD, the drain of the third MOS transistor M0 is respectively connected to the source of the fourth MOS transistor M1 and the source of the fifth MOS transistor M2 connected, the drain of the fourth MOS transistor M1 is respectively connected to the drain of the sixth MOS transistor M3, the drain of the ninth MOS transistor M6 and the gate of the eighth MOS transistor M5, the The gate of the fourth MOS transistor M1 is respectively connected to the input terminal VIN and the gate of the sixth MOS transistor M3, and the drain of the fifth MOS transistor M2 is respectively connected to the drain of the eighth MOS transistor M5 and the gate of the sixth MOS transistor M3. The drain of the seventh MOS transistor M4 is connected, the source of the fifth MOS transistor M2 is respectively connected to the output terminal and the gate of the seventh MOS transistor M4, and the source of the seventh MOS transistor M4 is respectively connected to the The source of the sixth MOS transistor M3, the source of the eighth MOS transistor M5, the source of the ninth MOS transistor M6 are connected to the digital ground GND, and the first stage complementary common source positive feedback operational amplifier The output of is the input of the second stage complementary common source positive feedback operational amplifier.

Wherein, the third MOS transistor M0, the fourth MOS transistor M1, and the fifth MOS transistor M2 are P-channel MOS transistors, and the sixth MOS transistor M3, the seventh MOS transistor M4, and the The eighth MOS transistor M5 and the ninth MOS transistor M6 are N-channel MOS transistors.

In order to distinguish, the structure of the second-stage complementary common-source positive feedback operational amplifier is exactly the same as that of the first-stage complementary common-source positive feedback operational amplifier. In order to distinguish the original components of the two, in Figure 4, the third MOS tube is M7 Indicates that the fourth MOS tube is represented by M8, the fifth MOS tube is represented by M9, the sixth MOS tube is represented by M10, the seventh MOS tube is represented by M11, the eighth MOS tube is represented by M12, and the ninth MOS tube is represented by M13. The input terminals of the first-stage complementary common-source positive feedback operational amplifier are V1N and V1P, and the output terminals are VOUT _1N and VOUT _1P . The input terminals of the second-stage complementary common-source positive feedback operational amplifier are V2N and V2P, and the output terminal is VOUT _2N and VOUT _2P , the first-stage output terminal VOUT _1N is connected to the second-stage input terminal V2N, the first-stage output terminal VOUT _1P is connected to the second-stage input terminal V2P, and CMFB is a common-mode feedback circuit. The technology is the same, and will not be described in detail here.

Embodiment four

As an optional implementation of the present invention, the quantization module is composed of a flash structure ADC and a capacitive structure DAC; or, the quantization module is composed of a successive approximation structure ADC and a capacitive structure DAC, but the quantization of the present invention The module is not limited thereto, and all circuits applying the method of the present invention belong to the protection scope of this patent.

Referring to Figure 5, Figure 5 shows a high-speed MDAC specific practical application circuit in which the quantization module is driven by a push-pull output stage composed of a flash-type ADC and a capacitive structure DAC. The overall MDAC is composed of two modules, the quantization module and the residual amplification module. The quantization module generates a quantization result and an unamplified residual signal through quantization and operation, and the residual amplification module quickly amplifies the residual generated by the quantization module and inputs it to the second stage of the pipeline ADC.

It can be understood that the first stage of the GSs pipeline is an MDAC. Embodiment 1 of the present invention adds a push-pull output stage circuit to drive a load capacitor CL, which is the sampling capacitor of the second stage of the GSs pipeline.

In FIG. 5 , the area marked by the core unit is the actual application circuit given by the present invention in combination with the first embodiment and the second embodiment. The circuit shown in FIG. 5 can shorten the overall MDAC setup time and realize high-speed MDAC. Of course, what is shown in FIG. 5 of the present invention is only one of the actual application circuits. Specifically, except for the core unit area, other areas can meet the requirements of the first stage of the GSs pipeline.

Combining Figure 1-Figure 4, referring to Figure 6, there are two push-pull output stage circuits in Figure 6, the second stage complementary common source positive feedback operational amplifier shown in Figure 4 is connected to the push-pull output stage circuit, the second stage The complementary common-source positive feedback operational amplifier includes two output terminals VOUT _2N and VOUT _2P . Therefore, in the circuit diagrams shown in Figure 1 and Figure 2, there are two circuits connected to the push-pull output stage circuit connected to the inverting amplifier. The first The input terminal V2N of the first push-pull output stage circuit is connected to the output terminal VOUT _2N , and the input terminal V2P of the second push-pull output stage circuit is connected to the output terminal VOUT _2P . The structure of the two push-pull output stage circuits is the same as that shown in Figure 2 , which will not be repeated here.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as limiting the invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

Although the present application has been described in conjunction with various embodiments here, however, in the process of implementing the claimed application, those skilled in the art can understand and Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (6)

1. A kind of MDAC that is applied to GS/s pipeline ADC push-pull output stage drive, comprises quantization module, residual amplification module and load capacitance (CL), and described quantization module is used for quantization and calculation and produces quantization result and unamplified The residual signal, the residual amplification module is used to amplify the residual signal, and drive the load capacitance (CL), characterized in that the residual amplification module includes: an inverting amplifier and a push-pull output stage circuit, the output end of the quantization module is connected to the input end of the inverting amplifier, the input end of the push-pull output stage circuit is connected to the output end of the inverting amplifier, and the push-pull output stage circuit includes: The first capacitor (C1), the second capacitor (C2), the first resistor (R1), the second resistor (R2), the first MOS tube (M _a ) and the second MOS tube (M _b ), the inverting amplifier The first output end of the first capacitor (C1) is respectively connected to one end of the first capacitor (C1) and one end of the second capacitor (C2), and the other end of the first capacitor (C1) is respectively connected to the first resistor (R1 ) is connected to the gate of the first MOS transistor ( _Ma ), the other end of the first resistor (R1) is connected to the first bias voltage (VB1), and the second capacitor (C2) The other end is respectively connected to one end of the second resistor (R2) and the gate of the second MOS transistor (M _b ), and the other end of the second resistor (R2) is connected to the second bias voltage (VB2 ), the source of the first MOS transistor (M _a ) is respectively connected to the source of the second MOS transistor (M _b ) and one end of the load capacitance (CL) of the second stage of the pipeline ADC, and the first The drain of a MOS transistor (M _a ) is connected to the positive power supply (VDD), the drain of the second MOS transistor (M _b ) is connected to the digital ground (GND), and the other end of the load capacitor (CL) is connected to Connect to digital ground (GND). 2. a kind of MDAC that is applied to GS/s pipeline ADC push-pull output stage drive according to claim 1 is characterized in that, described reverse amplifier is made of two-stage complementary common source positive feedback operational amplifier, the 3rd electric capacity (CS) and a fourth capacitor (CF), the positive input terminals of the first-stage complementary common-source positive feedback operational amplifier in the two-stage complementary common-source positive feedback operational amplifier are respectively connected to the third capacitor (CS) ) is connected to one end of the fourth capacitor (CF), the other end of the third capacitor (CS) is connected to the output of the quantization module, and the output terminal of the first-stage complementary common source positive feedback operational amplifier It is connected with the input terminal of the second-stage complementary common-source positive feedback operational amplifier, and the other end of the fourth capacitor (CF) is respectively connected to the output terminal of the second-stage complementary common-source positive feedback operational amplifier, the first capacitor One end of (C1) is connected to one end of the second capacitor (C2). 3. a kind of MDAC that is applied to GS/s pipeline ADC push-pull output stage drive according to claim 2 is characterized in that, any complementary common source positive feedback operation in two complementary common source positive feedback operational amplifiers The amplifier includes: the third MOS transistor (M0), the fourth MOS transistor (M1), the fifth MOS transistor (M2), the sixth MOS transistor (M3), the seventh MOS transistor (M4), and the eighth MOS transistor (M5) , the ninth MOS transistor (M6) and a common-mode feedback circuit, the output terminal of the common-mode feedback circuit is connected to the gate of the third MOS transistor (M0), and the source of the third MOS transistor (M0) It is connected to the positive pole of the power supply (VDD), and the drain of the third MOS transistor (M0) is respectively connected to the source of the fourth MOS transistor (M1) and the source of the fifth MOS transistor (M2), so The drain of the fourth MOS transistor (M1) is respectively connected to the drain of the sixth MOS transistor (M3), the drain of the ninth MOS transistor (M6) and the gate of the eighth MOS transistor (M5). The gate of the fourth MOS transistor (M1) is connected to the output terminal VOUT _IN and the gate of the sixth MOS transistor (M3) respectively, and the drain of the fifth MOS transistor (M2) is connected to the gate of the sixth MOS transistor (M2) respectively. The drain of the eighth MOS transistor (M5) is connected to the drain of the seventh MOS transistor (M4), and the gate of the fifth MOS transistor (M2) is connected to the output terminal VOUT _IP and the seventh MOS transistor (M4) respectively. The gate of the MOS transistor (M4) is connected, and the source of the seventh MOS transistor (M4) is respectively connected to the source of the sixth MOS transistor (M3), the source of the eighth MOS transistor (M5), The source of the ninth MOS transistor (M6) is connected to the digital ground (GND), and the output of the first-stage complementary common-source positive feedback operational amplifier is the input of the second-stage complementary common-source positive feedback operational amplifier. 4. A kind of MDAC that is applied to GS/s pipeline ADC push-pull output stage drive according to claim 1, is characterized in that, described first MOS transistor (M _a ) is N-channel MOS transistor, and described first The second MOS transistor (M _b ) is a P-channel MOS transistor. 5. A kind of MDAC applied to the push-pull output stage drive of GS/s pipeline ADC according to claim 3, characterized in that, the third MOS transistor (M0), the fourth MOS transistor (M1) and The fifth MOS transistor (M2) is a P-channel MOS transistor, the sixth MOS transistor (M3), the seventh MOS transistor (M4), the eighth MOS transistor (M5) and the ninth MOS transistor (M5) The MOS transistor (M6) is an N-channel MOS transistor. 6. A kind of MDAC that is applied to GS/s pipeline ADC push-pull output stage drive according to claim 1, is characterized in that, described quantization module is made of flash structure ADC and capacitor structure DAC, or; The quantization module is composed of successive approximation structure ADC and capacitance structure DAC.

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